WO2002032116A1

WO2002032116A1 - Adaptive synchronization mechanism for digital video decoder

Info

Publication number: WO2002032116A1
Application number: PCT/US2000/028057
Authority: WO
Inventors: Takaaki Ota
Original assignee: Sony Electronics Inc
Current assignee: Sony Electronics Inc
Priority date: 2000-10-11
Filing date: 2000-10-11
Publication date: 2002-04-18
Anticipated expiration: 2003-04-11
Also published as: AU2001213313A1

Abstract

An adaptive clocking mechanism is provided for a digital display system. The digital display system includes a clock recovery system, for recovering a system, for recovering a system time clock from a video bit-stream generated at an encoder, and a decoding system for decoding an decompressing the video bit-stream at a frame rate. The adaptive clocking mechanism operates to determine, from video format information transmitted from the encoder, the occurrence of a frame rate at which a transmitted signal is encoded that differs from a frame rate expected by the decoder. Upon such a determination, the adaptive clocking mechanism further operates to select a modifier (22) from a group of modifiers based on format information derived from the video bit-stream, including the encoded frame rate. The selected modifier is ten applied to a synchronisation function of the decoder in a manner to bring the decoder operation into synchronisation with the non-expected encoder frame rate.

Description

ADAPTIVE SYNCHRONIZATION MECHANISM FOR DIGITAL VIDEO DECODER

FIELD OF THE INVENTION

The invention relates generally to video decoders. More specifically, the invention relates to modifying the clock mechanism of a digital video decoder to allow for synchronization of decoded and encoded standard definition (SD) and high definition (HD) video signals that may have multiple formats and/or frame rates.

BACKGROUND OF THE INVENTION

With ever increasing demand for video throughput and a relatively finite transmission infrastructure, compression of video signal information to be transmitted has become essential. Fortunately, the coincident vast increase in digital processing capability has rendered practical the digitization of such video signal information followed by application of various compression algorithms to the digitized data. In the operation of that compression process, the digitized video signal information is operated on by an encoder at the transmission site, which carries out the desired compression algorithms and produces as an output a video bitstream requiring substantially less transmission bandwidth that would have been required for the original video signal information. After transmission of that compressed video bitstream to a receiving site, that bitstream is operated on by a decoder which reverses the compression process and restores the original video signal information. A widely-accepted standard for the encoding and transport of such digitized

video signal information is the MPEG-2 Standard, the details of which are set forth in the International Organisation for Standardisation's International Standard

Document ISO/IEC 13818-1, Information Technology — Generic Coding of

Moving Pictures and Associated Audio Information: Systems (November 1994),

which Standard Document is incorporated by reference herein. The discussion

herein is based on the application MPEG-2 encoded video signals and MPEG-2

compliant decoders, but it should be understood that the invention described herein

is not limited to a particular encoding/decoding method or standard.

Digital video decoders such as found in digital television receivers or in set-

top boxes (STB), require accurate synchronization between the encoding rate of the

incoming video signals — i.e., the rate at which an input video bitstream is encoded

by at a transmission site, and the decoding rate of such signals — i.e., the rate at

which the input video bit-stream is decoded by the digital video decoder receiving

the encoded video bitstream. Because the received data is expected to be processed

at a particular rate — to match the rate at which it is generated and transmitted, a

loss of synchronization between the decoder and the encoder leads to either buffer

overflow or underflow at the decoder, and as a consequence, loss of presentation

and/or display synchronization.

Generally, synchronization in such video decoders occurs in a two-stage

process. In the first stage, a digital, video decoder analyzes the incoming video bit stream transmitted by the encoder to determine the clock frequency, or base clock,

of the encoder. A standard method of clock-recovery at the decoder with respect to MPEG-2 digital video signals is described below in the Detailed Description. In the second stage of synchronization, the decoder uses the recovered base clock rate of the encoder to reproduce video frames at exactly the same rate as that of the transmitter's encoder. This decoder processing includes an extraction of fields from the video bitstream containing decoding and presentation time stamps as well as various video format attributes. For an MPEG-2 compressed video signal, such attributes include the number of pixels per line, the number of lines per frame, and the number of frames per second. These attributes, and thus the respective video formats, differ for standard definition (SD) video and high definition (HD) video. In particular, it is noted that the "normal" frame rates for the HD and SD video formats are respectively 30 Hz and 29.94 Hz. Note also that 29.94 Hz is the frame rate for the analog NTSC video system and that the SD video format supports corresponding pixels/line and lines/frame rates to those of the NTSC system. Thus, the 29.94 Hz frame rate may be viewed as being somewhat of an artifact from the analog NTSC video system.

A synchronization issue for the decoder is, however, presented by these different frame rates because the MPEG-2 standard permits the application of either frame rate to either the HD or SD video format ~ reflecting both an expectation that some NTSC-produced program material will be transmitted using the HD video format, and the possibility that, in the long run, the SD video format may utilize primarily the 30 Hz frame rate. However, for the indefinite period during which both HD and SD formatted programming is transmitted at both the 30 Hz and the 29.94 Hz frame rates, a necessity exists for the decoder to adapt to the "non-standard" frame rate for a video bitstream in which it occurs. For example, a decoder processing an HD bitstream which was encoded and transmitted using the 29.94 Hz frame rate will experience input buffer underflow and loss of presentation and/or display synchronization unless such an adaptation is made from the expected 30 Hz frame rate for that format. In the alternate case of processing an SD bitstream encoded and transmitted at a 30 Hz frame rate, input buffer overflow would be experienced, along with similar loss of presentation and/or display synchronization.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the invention to provide a mechanism to achieve decoder synchronism in the circumstance of the encoded frame rate being other than the frame rate expectation of the decoder for the video format being processed. To that end, a method of employing an adaptive synchronization mechanism to modify the frame rate of a decoding system of a digital display system is disclosed which includes the following steps. In one step, format information, including the encoded frame rate, is derived from a video bit-stream received by the digital display device. In another step, a modifier is determined based on the format information derived from the video bit-stream. Finally, the frame rate is modified by applying the determined modifier to one or more members of the group consisting of horizontal pixel rate and vertical line rate. BRIEF DESCRD?TION OF THE DRAWINGS

FIG. 1 is a block diagram of a known clock recovery system in a digital

video decoder.

FIG. 2 is a block diagram showing an embodiment of the adaptive

synchronization mechanism of the invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Exemplary embodiments of the timing synchronization mechanism of the

invention will now be described in detail with reference to the accompanying

drawings. It will be appreciated by one skilled in the art that the inventive concepts

disclosed and discussed in detail with reference to the exemplary embodiments

herein can be employed to synchronize the frame rate of a digital video decoder

which is either integrated within a digital display device — e.g., an integrated

digital television receiver/decoder, or which is in a device which is in

communication with (although not necessarily physically connected to) a display

device - e.g. , a digital set-top box (STB). It will also be understood that the

inventive concepts herein are intended to apply to environments where, for

example, either or both the clock recovery process and the bitstream decoding

process may occur within the digital display device itself (e.g., within an integrated

digital television receiver/decoder), or in a digital STB or other similar digital

decoding device. For simplicity of illustration, the inventive concepts herein are discussed with reference to a digital video decoding device that includes both the

system clock recovery mechanism and decoding mechanism. For the clock-recovery step of the two step decoder synchronization process

described in the Background section, an established method of recovering the base

clock with respect to MPEG-2 video signals and systems is set forth in Annex D of

the ISO/LEC 13818-1 standard (specifically, Section D.0.3 System Time Clock

Recovery in the Decoder). It will be understood that, although this is currently the

accepted standard method for decoder timing synchronization with the base clock

of MPEG-2 signals (such as used in the transmission of digital television in the

U.S.), reference to this method is merely for illustrative purposes, and the subject

invention is not limited to such method or to digital television systems.

The operation of the ISO IEC 13818-1 standard clock recovery system is

depicted schematically in Figure 1. As will be seen from the figure, either the

system clock reference (SCR) or the program clock reference (PCR) is used as a

reference signal for the clock recovery system. As is known, the SCR is a time

stamp referenced to the encoder clock which recurs in packets of an MPEG-2

program stream at intervals up to 700 ms. The PCR is a corresponding time stamp

that recurs in packets of an MPEG-2 transport stream at intervals up to 100 ms.

The transport stream is an alternate MPEG-2 bitstream construct which generally

provides increased error detection capability relative to the program stream. The

SCR and PCR are generally considered to be equivalent time references and,

although the discussion following will, for convenience of nomenclature, be based

on use of the SCR time stamp, it should be understood that an equivalent clock

recovery process would be carried out in the case of the PCR time stamp being

provided to the decoder. With further reference to Figure 1, an SCR time stamp is received at the

decoder and provided as an input to Subtractor 10. At the same time, the SCR

input signal is provided as a Load signal to Counter 12, causing the current value of

Counter 12, representing the current frequency of the decoder System Time Clock

(STC), to be output therefrom and provided as a second input to Subtractor 10. A

difference is determined by Subtractor 10 between the input SCR value and the

current STC value, and an error signal, e, corresponding to that difference is output

from Subtractor 10. After amplification and filtering of that error signal by Low-

Pass Filter & Gain 14, the output thereof,/, is provided as input to Noltage-

Controlled Oscillator 16. The output of the Voltage-Controlled Oscillator 16 is

provided to other decoder stages as the current value of the decoder STC and is

also fed back to the input of the clock recovery circuit via Counter 12. Thus, as a

new SCR time stamp value arrives at the input to Subtractor 10, a new error signal

will be generated based on the difference between that new SCR value and the

then-current STC value from Counter 12, which error signal is ultimately translated

into a new STC value by Voltage-Controlled Oscillator 16, thereby maintaining the

decoder STC in synchronism with the encoder clock, as represented by the

currently received SCR value. (As is well-known, the standard system clock

frequency under the ISO/IEC 13818-1 (MPEG-2) standard is 27 MHz; however, it

will be understood that the principle and operation of clock recovery as described

herein is independent of such specific frequency and any other frequency may also

be used). In the second stage of synchronization, the decoder uses the recovered base clock rate of the encoder along with decoding and presentation time stamps extracted from fields of the video bitstream to reproduce video frames at exactly the same rate as that of the transmitter's encoder. Various video format attributes are also extracted from fields of the video bitstream which provide essential input data to the synchronization process. For an MPEG-2 compressed video signal, such attributes include the number of pixels per line, the number of lines per frame, and the number of frames per second. And as already noted, these attributes differ as between MPEG-2 video formats, particularly as between standard definition (SD) video and high definition (HD) video, as discussed below.

The MPEG-2 encoding standard contemplates the encoding and transmission of both high definition (HD) video signals and standard definition (SD) video signals. While MPEG-2 permits multiple video formats for both HD and SD, only a single HD encoding format and a single SD format will be discussed herein — the two formats so discussed representing a preponderance of presently-realized applications of MPEG-2 encoding. As will be apparent to those skilled in the art, however, the principles discussed will be equally applicable to others of the permitted MPEG-2 video formats.

The video formats for MPEG-2 are characterized by a horizontal scanning rate, expressed as a number of pixels per line, a vertical scanning rate, expressed as a number of lines per frame, and a frame rate, expressed as a number of frames per second. A specific HD video format which can be implemented under MPEG-2 is characterized by a horizontal scanning rate of 2200 pixels per line, a vertical scanning rate of 1125 lines per frame, and a frame rate of 30 frames per second,

hereafter denoted 30 Hz. [Note that this format is also covered by the Society of

Motion Picture and Television Engineers Standard 240M- TeZevώz^'ø/ϊ - Signal

Parameters - 1125 -Line High-Definition Production Systems (hereafter SMPTE

240M)] This scanning format, which also constitutes one of the defined picture

formats in the Advanced Television Systems Committee Digital Television Standard

(hereafter ATSC Standard), can accommodate 1920 active pixels per line and 1080

active lines per frame, in accordance with the ATSC Standard (and, as well, the

SMPTE Standard 274M Television - 1920x 1080 Scanning and Interface

(hereafter SMPTE 274M)).

The SD video format used herein is characterized by a horizontal scanning

rate of 858 pixels per line, a vertical scanning rate of 525 lines per frame, and a

frame rate of 29.97 frames per second, hereafter denoted 29.97 Hz. This scanning

format also constitutes one of the defined picture formats in the ATSC Standard

(and is also defined in the standard: ITU-R BT.601-4 , Encoding parameters of

digital television for studios), and can accommodate 720 active pixels per line and

480 active lines per frame.

It is noted that, although 30 Hz is the "normal" frame rate for the MPEG-2

HD and 29.97 Hz is the "normal" frame rate for MPEG-2 SD, the MPEG-2

standard permits either frame rate to be used with either video format. Note also

that the 29.97 Hz frame rate is commonly denoted in the art as "30/1.001," and that convention will generally be used herein. As is well known, the conversion of an analog video signal to a digital bit stream is carried out by sampling the analog signal at a sampling rate at least twice the signal frequency. In the usual case where the sampling rate is selected such that

each digital bit corresponds to one pixel of video information, that sampling rate corresponds to the total number of pixels processed in a unit of time. Thus, using the video format parameters described above, that sampling rate, which is also characterized as the pixel clock, will be the product of the horizontal scanning rate, the vertical scanning rate and the frame rate. In the case of the HD video format, this pixel clock would be derived as:

30 Hz x 1125 x 2200 = 74.25 MHz.

Similarly, the pixel clock for the SD video format would be derived as:

30/1.001 Hz x 525 x 858 = 13.5 MHz. In the operation of the video decoder, these sampling/scanning frequencies - i.e. the pixel clock rate, the horizontal scanning rate and the frame rate, must be derived from the decoder STC. For example, considering the case of the HD video format, extraction of the video format attributes from an MPEG-2 video bit-stream begins with the derivation of the pixel clock, which is typically derived by multiplying the recovered 27 MHz base clock by 11 and then dividing by 4. Thus,

the pixel clock rate for this format is derived as: 27 MHz x 11/4 = 74.25 MHz. The horizontal scanning rate for each frame is then derived by dividing the pixel clock by the total number of pixels per line, which is a constant for a given video format. Thus a divider is implemented in the decoder having as its dividend the pixel clock rate (here, 74.25 MHz) and as its divisor the pixels per line for the video format being decoded (here, 2200). The output of the divider, representing

the derived horizontal scanning rate, will be: 74.25 MHz/2200 = 33.75KHz. The

frame rate can then be generated in a second divider by dividing the horizontal

frequency by the total number of scanning lines per frame. For this exemplary HD

video format, the decoder frame rate will be derived as 33.75KHz ÷ 1125

lines/frame = 30 Hz.

Correspondingly for the SD video format case, the pixel clock for the SD

video is derived by dividing by 2, the 27 MHz system clock recovered in the first

synchronization stage, to obtain a 13.5MHz pixel clock. The horizontal scanning

frequency can then be derived by dividing this pixel clock by the total number of

pixels per line. For the exemplary SD format described here, the 3.5MHz pixel

clock will be divided by 858 pixels per line to obtain a horizontal scanning

frequency of 15.734KHz. The frame rate is then derived by dividing this horizontal

scanning frequency by the total number of scanning lines per frame, here the ATSC

standard of 525, to arrive at the current standard frame rate for SD of 29.97 Hz

(30/1.001).

Although as set forth above, the standard decoder operations for SD and

HD video are arranged to develop frame rates of 30/1.001 and 30 respectively, the

ATSC standard allows for transmission frame rates of 30 and 30/1.001 for all

standard formats. Thus, despite the fact that digital video decoders normally

decode an HD video signal at a frame rate of 30 frames/second, such signal can

instead be transmitted at a 30/1.001 frames/second rate. Similarly, while a decoder

normally decodes an SD video signal at a frame rate of 30/1.001 frames/second, the ATSC standard allows for transmission of such SD signal at 30 frames per second rate. In such case, the SD and HD signals decoded and reproduced by the decoder will not be synchronized with the signals transmitted by the encoder. It will be appreciated that without such synchronization, significant errors in the reconstruction of the digital video signal can occur. For example, it is known that each digital display device decoder has a bitstream buffer at its input, which is filled for some period of time before the first picture is removed for decoding. If the decoder rate is faster than the encoder rate, less than the entire bitstream is decoded from the bitstream buffer by the digital display device. This is referred to as bitstream buffer underflow. Conversely, if the decoder rate is slower than the encoder rate, then bitstream buffer overflow occurs. Bitstream buffer underflow is likely to cause the resulting picture to freeze while an overflow will result in data loss and could have disastrous results.

According to the invention, a methodology is provided to maintain decoder synchronization in the circumstance of an incoming SD or HD signals being encoded and transmitted at a frame rate different from the decoders normal expectation (based on the video format being processed). In the implementation of that methodology, a modification is made to the pixel-number and the line-number parameters which are used by the decoder in its derivation of the horizontal scan rate and frame rate for decoding the input video bitstream.

The methodology of this embodiment will be better understood by reference to Figure 2, which depicts functionally the portion of the decoder operation directed to the derivation of those rates. As can be seen from the figure, the decoder system-time-clock (STC) frequency from the clock recovery system is applied as an input to a Pixel Clock Derivation function 20, which applies a Pixel Clock Multiplier to that frequency, producing as an output the Pixel Clock Rate. The Pixel Clock Multiplier is determined by Parameter Selection function 22 based on video format attributes extracted from the input bitstream to the decoder, and provided as input to Parameter Selection function 22. In a preferred embodiment, the Parameter Selection function will be carried out by software running on the decoder's main processor, that software operating to process the input video format attributes to determine an appropriate multiplier for the STC, for deriving the pixel clock rate for that video format. That multiplier can either be computed directly by the software, or a table can be created and stored in an associated memory means to include a plurality of such multipliers as appropriate for each of a set of particular video formats. In the latter case, the software would do a table lookup based on the input video format attributes, select the correct multiplier, and output that multiplier to Pixel Clock Derivation function 20.

Once the Pixel Clock Rate has been determined, it is applied as an input to Horizontal Frequency Derivation function 24 which operates to divide the input pixel clock rate by another input parameter, No. of Pixels per Line, provided by Parameter Selection function 22. That division operation produces as an output the Horizontal Scan Rate for the video format being processed. That horizontal scan rate is then provided as an input to Frame Rate Derivation function 26, which operates to divide the input horizontal scan rate by another input parameter, No. of Lines per Frame (as provided by Parameter Selection function 22), to produce as an output the Frame Rate for the video format being processed.

It will be understood by those skilled in the art that the operation of the Parameter Selection software in the determination of the No. of Pixels per Line (as input to Horizontal Frequency Derivation 24) and of the No. of Lines per Frame (as input to Frame Rate Derivation 26) is carried out in a corresponding manner to that described above for determination of the Pixel Clock Multiplier.

As already noted, a single HD video format and a single SD video format are considered herein to illustrate the principles of the invention. For the selected HD format, the pixel clock multiplier is 11/4, the number of pixels per line is 2200, and the number of lines per frame is 1125. The corresponding values for the selected SD format are: pixel clock multiplier = 1/2; pixels per line = 858; and lines per frame = 525. As will be apparent to those skilled in the art, these values would be determined for a given one of those selected video formats by Parameter Selection function 22, preferably through a table lookup from a table into which such values had previously been stored, as corresponding to the selected video format. However, as also indicated in the preceding discussion, these values provide the correct decoder synchronization only in the case of the encoder operating at the "standard" frame rate for the selected video format. To correct the decoder synchronization problem arising with the encoding/transmission of a video format using a non-standard frame rate, the method of the invention operates on the input parameters to the Horizontal Frequency Derivation function 24 and the Frame Rate Derivation function 26. As discussed in detail above, the frame rates by which synchronization is achieved are typically derived using standard arithmetic operations on the pixel clock frequency, which is itself derived from the base clock frequency. Rather than adapt the clock rate, however, this embodiment employs the discovery that approximations of the total number of pixels per scanning line (hereafter "H divider") and the total number of scanning lines per frame (hereafter "N divider") can be used in place of the standard, known values, in order to derive the appropriate synchronization frequencies.

Experimentation with different modified H and N dividers was carried out and preferred values for these modified values were determined. These preferred values are set forth in Table 1 below, along with the frame rate achieved by using these modified H and N divider values (the first row corresponding to the HD format and the second row to the SD format):

TABLE 1

To implement the methodology of the invention, the Parameter Selection software is modified to specifically capture the encoding frame rate from the video format attributes inputted from the decoder input bitstream and to distinguish between the "standard" and "non-standard" frame rates for the video format being processed. The lookup table associated with that function will also be modified to

include the modified H and N Dividers of Table 1 (such H and N Dividers corresponding to No. of Pixels per Line and No. of Lines per Frame, respectively).

In the operation of the inventive methodology, upon detection by Parameter

Selection software of a "non-standard" frame rate, a table lookup will be made for

the H and N Divider parameters corresponding to that "non-standard" frame rate

for the video format being processed. Such parameters will be selected from the

table and outputted respectively to Horizontal Frequency Derivation 24 and Frame

Rate Derivation 26. From that point, decoder synchronization will be carried

forward in the same manner as for a "standard" frame rate. Table 2 shows the

application of the modified H and N Dividers of Table 1 to achieve SD and HD

decoder outputs at both ATSC-accepted frame rates.

TABLE 2

While details of the invention are discussed herein with reference to

particular examples to which the principles of the present invention can be applied,

the applicability of the invention to other devices and equivalent components

thereof will become readily apparent to those of skill in the art. Accordingly, it is intended that all such alternatives, modifications, permutations, and variations to the exemplary embodiments can be made without departing from the scope and spirit of the present invention.

Claims

I CLAIM:

1. In a digital display device including a clock recovery system for recovering

a system time clock reference from a video bit-stream generated at an encoder to

produce a decoder system clock frequency, and a decoding system for decoding

and decompressing the video bitstream at a frame rate, an adaptive synchronization

mechanism for said decoding system comprising:

means for extracting from said video bitstream attributes of a video format

transmitted via said bitstream;

selecting means, cooperatively linked with said decoding system, for

selecting a modifier from a group of modifiers based on video format attributes

derived from said video bit-stream; and

modifying means, cooperatively linked with said selecting means and said

decoding system, for modifying one or more synchronization parameters of said

decoding system with said selected modifier prior to decoding said video bit-

stream.

2. The adaptive synchronization mechanism of claim 1, wherein said selecting

means comprises a software routine, the group of modifiers consists of modified

horizontal pixel-rate values and modified vertical line-rate values, and the

modifying means comprises a software routine operative to modify one or both of

horizontal frequency derivation and frame rate derivation synchronization functions of said decoding system by causing at least one of a selected one of said

modified horizontal pixel-rate values and a selected one of said modified vertical line-rate values to be applied by said horizontal frequency derivation and frame rate derivation synchronization functions, respectively, of said decoding system.

3. The adaptive synchronization mechanism of claim 2, wherein said modified horizontal pixel-rate value is related to a difference between a frame rate used by said encoder and a frame rate expected by said decoder for said transmitted

bitstream.

4. The adaptive synchronization mechanism of claim 2, wherein said modified vertical line-rate value is related to a difference between a frame rate used by said encoder and a frame rate expected by said decoder for said transmitted bitstream.

5. A method for providing synchronization of a video decoder for an input video bitstream encoded in respect to a given video format, where said given video format may be characterized by a preferred frame rate or by an alternate frame rate, said method comprising the steps of: operating on said input video bitstream to derive therefrom one or more attributes of said given video format, said attributes having a known relationship to said given video format; detecting from said derived attributes an identify of said given video format and an indication of whether said encoded input video bitstream is characterized by said preferred frame rate or said alternate frame rate; where said encoded input video bitstream is characterized by said alternate frame rate, selecting a modifier for application to a synchronization function of said decoder, said modifier being related to a differential between said preferred frame rate and said alternate frame rate; and applying said modifier to said decoder synchronization function.

6. The video decoder synchronization method of claim 5 wherein said attributes of said given video format include an encoded pixel rate, line rate and frame rate for said input video bitstream.

7. The video decoder synchronization method of claim 6 wherein each said given video format is characterized by a unique combination of the said encoded pixel rate, line rate and frame rate.

8. The video decoder synchronization method of claim 5 wherein said the selected modifier is selected from at least one member of a group consisting of a horizontal pixel-rate value and a vertical line-rate value.

9. The video decoder synchronization method of claim 5 wherein said synchronization function is selected from at least one member of the group consisting of a horizontal frequency derivation function and a frame rate derivation function of said decoding system.

10. The video decoder synchronization method of claim 9 wherein said step of

applying said modifier is carried out by providing a value of said modifier as an

input to said selected synchronization function.

11. The video decoder synchronization method of claim 5 wherein values of

said preferred frame rate and of said alternate frame rate are related according to a

known ratio.

12. The video decoder synchronization method of claim 11 wherein said

known ratio is 1000/1001.

13. The video decoder synchronization method of claim 11 wherein said known ratio is 1001/1000.

14. The video decoder synchronization method of claim 11 wherein said

modifier is proportional to said known ratio.

15. A frame rate modifier for a digital display device comprising:

means for selecting a modifier based on format information values from a

video bitstream received by the digital display device, said format information

values including a horizontal pixel-rate value, and a vertical line-rate value; and,

means for modifying at least one of said format information values, by

applying said selected modifier, in order to adjust a frame rate at which input information is operated on by a decoding device associated with said digital display device.

16. A frame rate modifier as claimed in claim 15, wherein said means for selecting is further defined by means for selecting said modifier from modified horizontal pixel-rate values.

17. A frame rate modifier as claimed in claim 15, wherein said means for selecting is further defined by means for selecting said modifier from modified vertical line-rate values.

18. In a digital display system including a clock recovery system for recovering a system time clock reference from a video bit-stream generated at an encoder to produce a system clock frequency, and a decoding system for decoding and decompressing the video bit-stream at a frame rate, a method of adapting a synchronization mechanism of the digital display system to modify a frame rate of the decoding system based on video format information derived from the video bit- stream comprising the following steps: deriving video format information from the video bit-stream; selecting a modifier based on the format information derived from the video bit-stream; and, modifying the frame rate by applying the selected modifier to a member of the group of synchronization functions consisting of a horizontal frequency derivation function and a frame rate derivation function of a decoding system associated with said digital display system.