HK1063403B - Video signal compression apparatus and compression method thereof - Google Patents

Description

Video signal compression apparatus and compression method thereof

The present invention is a divisional application of a patent application having the same name and having an application number of 01143527.5, which is filed on 12/5 of 1994.

Technical Field

The invention relates to the technical field of providing synchronization of transmitted data packet information by using auxiliary data fields.

Background

The compressed video signal generation and transmission system may operate at several synchronization levels, or more appropriately, at several pacing states. For example, the actual compression means will be synchronized, at least in part, to the vertical frame rate of the source video signal, and may also be synchronized to the color sub-carriers. Once the video signal is compressed and formed into a particular signal protocol (e.g., MPEG1), it may be further processed into transport packets for transmission. The transport packets may be time division multiplexed with packets from other video or data sources. The packetization and multiplexing may be performed synchronously with the compression operation or asynchronously. These transport packets (whether multiplexed or not) may then be sent to a modem for data transmission. The modem may or may not operate synchronously with the system described above.

At the receiver of a fully multiplexed transmitted compressed signal, it is generally necessary for the various subsystems to operate synchronously with the inverse function of their respective parts of the encoding end of the system. Synchronous operation in this case may generally refer to operation of each subsystem at very close proximity to the same frequency of its counterpart subsystem. The decompressor should provide the video signal at the frame rate of the video signal source used to provide it at the compressor and be synchronized with the associated audio signal. Synchronization of the video/audio decompression portion of the system may be achieved by inserting presentation time samples in the video/audio signal being compressed at the encoder, such samples indicating the correlation multiple of the generation/reproduction of the respective signal segments. Such a display time reference (PTR' S) can be used to compare the timing of the associated audio and video signals for synchronization purposes and for proper sequencing and continuity.

The receiver modem must of course operate at the frequency used precisely for the transmit modulation decoder. The receiver modem typically has a phase locked loop responsive to the transmit carrier frequency to generate a synchronized clock signal.

The synchronization of multiplexing and or transmitting data packetizing means tends to be more complex for two reasons. First, the multiplexed data may arrive discretely; second, to minimize manufacturing costs, rate buffering is typically employed between the modem and the decompressor, and measures must be taken to ensure that its rate buffer neither overflows nor underflows, with the constraint of actual manufacturing costs of keeping the buffer as small as possible.

Disclosure of Invention

The present invention is an apparatus for synchronizing an intermediate layer of a transport or multiplex layer signal such as a multi-layer compressed video signal. At the encoding end of the system, a modulo-K counter is clocked in response to the system clock and embeds a count value in the transport layer signal according to a predetermined protocol. At the receiving end of the system, a similar counter is responsive to a controlled receiver clock signal, and the count value of the counter is sampled upon arrival of the count value embedded in the transport layer. The difference of the count values of successive samples of the receiver counter is compared with the difference of corresponding successive values of the count values embedded in the transport layer to provide a signal to control the receiver clock signal.

A video signal compression apparatus according to the present invention includes:

-a source of video signals;

-a clock signal source;

-a counter for counting said clock signal modulo N, where N is an integer;

-means responsive to the time of occurrence of a frame of said video signal for capturing a number of count values provided by said counter as a display time reference;

-means for compressing said video signal and formatting compressed video data using said display time reference, which display time reference is comprised in said compressed video signal;

-a transport processor coupled to receive formatted compressed video data including said presentation time reference from said compression means for segmenting said compressed video data into transport packets containing said compressed video data and a payload of said presentation time reference concatenated with a transport header;

-means responsive to the timing of the transmission of the data packets for periodically capturing a further count value provided by said counter as a program clock reference; and is

Wherein the program clock reference) is included in the payload of some of the transport packets as auxiliary data in addition to the compressed video data; and

-means for setting up said transmission data packet for transmission.

A compression method for a video signal, comprising the steps of:

-modulo-N counting a clock signal from a clock signal source in a counter, where N is an integer;

-capturing a number of the count values provided by the counter as a display time reference, said capturing being in response to the time of occurrence of a frame of the video signal;

-compressing said video signal and formatting compressed video data using said display time reference, which display time reference is comprised in said compressed video signal;

-receiving said formatted compressed video data including said display time reference in a transport processor for segmenting said compressed video data into transport packets containing said compressed video data and a payload of said display time reference concatenated with a transport header;

-periodically capturing a further count value provided by the counter as a program clock reference, the periodic capturing being in response to the timing of transmission of data packets,

wherein the program clock reference is included in the payload of some of the transport packets as auxiliary data in addition to the compressed video data; and

-setting the transmission data packet for transmission.

An apparatus according to the present invention for synchronizing at least a portion of a compressed video signal receiving system that processes transport packets including compressed video and/or data signals and a first count value periodically derived from a counter, where N is an integer, the counter being disposed in an encoding system to count modulo-N pulses of an encoding system clock, said apparatus comprising:

-a source of said transmission data packets;

-a locked loop for providing a receiver system clock, said loop comprising:

a controlled oscillator responsive to a first control signal,

a receiver counter arranged to count pulses of said receiver system clock signal by the same modulo-N as said coding system, and a controller for generating an error signal representing a difference between the frequency of said coding system clock and the frequency of the output of said receiver counter;

-means responsive to each occurrence of a transmission data packet including said first count value for providing a second control signal,

wherein the means for synchronizing the receiver counter with the coding system counter comprises:

-means for storing a first count value received by said receiver; and

-means responsive to said second control signal for storing a second count value output by said receiver counter (36),

wherein the controller forms the error stop from a difference between a currently received first count value and a previously received first count value, and a difference between a current second count value and a previously received second count value.

A video encoder according to the present invention comprises:

a compressor for compressing the video signal;

a formatter for formatting said video signal into at least one transport packet for transmission over a network; and

a transport processor operable to incorporate into said transport data packet an auxiliary data field having a program clock reference field representing a time stamp, said auxiliary data field providing information for deriving decoder timing at the decoder; and is operable to incorporate into the transport packet a control field indicating whether the auxiliary data field in the transport packet containing the clock reference field is defined in the transport packet.

A method according to the invention for synchronizing timing in an encoder from said encoder to a decoder, comprises the steps of:

compressing the video signal;

formatting the video signal into at least one transport packet for transmission over a network;

incorporating into said transport packet an auxiliary data field having a program clock reference field representing a time stamp, said auxiliary data field providing information for deriving decoder timing at a decoder; and

incorporating into the transport packet a control field indicating whether the auxiliary data field in the transport packet containing the clock reference field is defined in the transport packet.

Drawings

Fig. 1 is a block diagram of a compressed video encoding/decoding system employing a clock recovery apparatus of the present invention.

Fig. 2 is a block diagram of a signal multiplexing apparatus useful for representing the formation of multiplexed data from different signal sources.

Fig. 3 and 5 are block diagrams of two further embodiments of clock recovery apparatus for transmitted compressed video signal data.

Fig. 4 is a block diagram of a signal multiplexing apparatus including a system for enhancing a timing reference within a multiplexed signal.

Fig. 6 and 7 are diagrammatic representations of a transmission data block and an auxiliary signal transmission data block.

Fig. 8 is a flowchart of the operation of the transport processor in fig. 2.

Detailed Description

Fig. 1 shows an exemplary system to which the present invention is applicable, which belongs to a compressed digital video signal transmission apparatus. In the present system, a video signal from a source 10 is fed to a compression unit 11 comprising a motion compensated predictive coder using a discrete cosine transform. The compressed video signal is supplied from unit 11 to formatter 12. The formatter 12 arranges the compressed video signal and other auxiliary data according to a certain signal protocol, for example a standard MPEG as proposed by the international standardization organization. The normalized signal is sent to the transmit processor 13 which divides the signal into data packets and adds some other data to provide noise immunity for transmission purposes. Transmission data packets, which typically occur at non-uniform rates, are applied to a rate buffer 14 which conducts at a relatively constant rate to provide output data for efficient use of a relatively narrow bandwidth transmission channel. The buffered data is applied to a modem 15 which performs signal transmission.

The system clock 22 provides clocking signals to operate most of the devices including at least the transport processor. The clock will operate at a fixed frequency, for example 27 MHz. However, as shown therein, it is used to generate timing information. The clock of the system is fed to the clock input of a counter 23 which can be set to a count modulo 230, for example. The count value output by the counter is fed to two latches 24 and 25. The latch 24 is set by the video signal source to latch the count value at each occurrence of a frame interval. These count values are used to represent display time samples (PTR's) and are included in the compressed video signal data stream by formatter 12 and are used by the receiver to provide lip-synchronization (lip-synchronization) of the associated audio and video information. The latch 25 is set by the transmission processor 13 (or the system controller 21) to latch the count value according to a predetermined procedure. These count values are used as a representation of the program clock references (PCR's). And embedded as auxiliary data in each auxiliary transmission data packet.

System controller 21 is a variable state machine programmed to coordinate the various processing units. It should be noted that the controller 21, compressor 11 and transport processor 13 may or may not be synchronized via a common clocking arrangement, as long as proper interactive communication is provided between the processing units.

The units 16-26 in fig. 1 comprise the receiving end of the transmission system, wherein the modem 16 performs the inverse function of the modem 15, and the rate buffer 17 actually performs the inverse function of the rate buffer 14. The data from the rate buffer 17 is sent to an opposite transport processor 18 which sends the compressed video signal to a decompressor 19 according to the system protocol. The decompressor generates uncompressed video signals in response to the compressed video signals for display on the device 20 or for storage in a suitable device.

The inverse processor 18 also supplies the PCR's from the auxiliary transmission data and control signals to the system clock generator 27. A clock generator responsive to these signals generates a system clock signal that is at least synchronized with the transport processor operation. The system clock signal is fed to the receiver system controller 26 to control the timing of the appropriate processing unit.

Referring to fig. 2, there is shown an apparatus that may be included, for example, in a transmission modem 15. The modem may receive data from a plurality of signal sources, the data being all data to be transmitted on a common transmission channel. This can be achieved by time division multiplexing of the various signals from the various signal sources. Furthermore, multiplexing may be done in layers. For example, the video programs Pi may be generated in different studios and coupled to the first multiplexer 55. These programs are time-division multiplexed and provided as a source signal Sl in accordance with well-known techniques.

The signal Sl is fed to a second layer multiplexer 56, along with source signals Si from other sources, where the signal Si is time division multiplexed according to well known techniques and predetermined protocols. Finally, there may be other forms of multiplexing within each program itself. The multiplexing thus performed may take the form of commercial programs inserted into the program content or stored programs inserted between the base segments of the live programming. In these latter two cases, it is assumed that the commercial or stored program has been pre-encoded with PTR's and PCR's, respectively. In this case, the PTR's and PCR's of the stored program would then be independent of the real-time PTR's and PCR's of the live program. As for PTR's, since the video signal will include parameters that cause the decompressor to restart the new signal. Their PTR's cause no problems in particular. The opposite is true. The lack of correlation between the stored and real-time PCR's, which can be completely interrupted, causes the rate buffer inverse transport processor unit of the receiver system to lose synchronization,

it is assumed in fig. 2 that the transport processor 53 comprises multiplexing means that are operationally similar to the respective multiplexers 55 and 56.

There are additional problems in multiplexing systems. In order for each multiplexing device not to lose data, it is necessary to provide a degree of signal buffering in the multiplexer if the data arrives simultaneously from multiple signal sources. These buffers will be delayed by T ± δ T, where δ T represents an unstable component. Assume that the program passes through the multiplexer 100 times (an exaggerated number for practical problems) and that each multiplexing adds a delay of 1 second ± 1 microsecond. The final delay result is a delay of 100 seconds ± 100 microseconds. Since the compressed video signal, and thus the PTR's, already experience the same delay, this 100 second in time is not a problem for the decompressor, and the 100 microsecond unstable component must be dealt with, otherwise the decoder's buffer may overflow or underflow.

Fig. 3 shows a first embodiment of a receiver clock generator. In this embodiment, the transmit processor may be placed before the rate buffer 17 in the signal path to eliminate variable delays that may be incurred in the receiver rate buffer. Data from the receiver modem is sent to the reverse transport processor 32 and an auxiliary packet detector 31. The reverse transport processor 32 separates transport header data from the payload of each transport packet. In response to the transmission header data, the processor 32 passes the video signal payload (shown here as traffic data 1) to, for example, a decompression device (not shown) and the auxiliary data (shown as traffic data 2) to a suitable auxiliary data processing unit (not shown). The PCR's placed in the auxiliary data are routed and stored in the memory unit 34.

The auxiliary packet detector 31, which may be a matched filter, identifies codewords indicating auxiliary transmission packets containing PCRs, generates a control pulse upon the occurrence of a transmission packet containing such data. This control pulse is used to store the count value currently being counted by the local counter 36 in the latch 35. The local counter 36 is used to count pulses generated by, for example, a voltage controlled oscillator 37. This counter 36 is designed to have the same modulo counting number as its corresponding counter in the encoder (counter 23).

The compression oscillator 37 is controlled by a low pass filtered error signal provided by a clock controller 39. The error signal is generated as follows. The PCR arriving at time n is designated PCRn and the count value currently latched in latch 35 is designated Ln. The clock controller reads successive values of PCR's and L's and forms an error signal E proportional to the difference:

E→|PCRn-PCRn-1|-|Ln-Ln-1|

the error signal E is used to adjust the voltage controlled oscillator 37 to a frequency that tends to equalize the difference. The error signal generated by the clock controller 39 may be in the form of a pulse width modulated signal. Which may be provided as an analog error signal by the analog component implemented in the low pass filter 38.

The constraint of the system is that the counters at both ends of the system count the same frequency or even multiple frequencies. This requires that the defined frequency of the voltage controlled oscillator be a frequency that is fairly close to the frequency of the encoder system clock.

The foregoing scheme provides fairly fast synchronization but introduces long term errors. This long term error LTE is proportional to the following difference:

LTE→|Ln-Lo|-|PCRn-PCRo|

where PCRo and Lo may be, for example, the first occurrence of a PCR and the corresponding latched value of the receiver counter. By definition, the error signals E and LTE will change in discrete steps. Thus, once the system is "synchronized," the error signal will dither by one unit around the zero point. The best synchronization method is to use the error signal E to initially control the voltage controlled oscillator until a unit of high frequency jitter occurs in the error signal E and then switch to using the long term error signal LTE to control the voltage controlled oscillator.

In order to adjust the delay T + -deltat introduced during the multiplexing, the transport processor at the encoder generates an auxiliary field in the auxiliary transport packet, which contains information about the variable delay. Procedures are developed to modify this variable delay information at different multiplex locations. Referring to fig. 6 and 7, fig. 6 shows one type of transport packet that is used in a high definition television system developed by the advanced television research association. The transmission data contains a prefix that has, among other things, a global identifier to indicate which service the payload contained in the data packet is for. The field CC is a continuous detection value that is included for error detection purposes. The HD field is a service description header that illustratively defines the payload. For example, if a particular service is indicated to provide a television program, each payload of the transport data packets for that service type may contain audio data, video data or associated ancillary data. The HD field thus indicates the type of particular payload for a particular packet,

fig. 7 shows a transmission data packet containing auxiliary data. The amount of data contained in each data set and the current system requirements, the payload of an ancillary transmission packet may include one or more ancillary data sets. In the transport packet shown in fig. 7, there are two auxiliary data groups containing data about the program clock references AUX1 and AUX 2. The auxiliary data set AUX1 includes data about variable delays, while the data set AUX2 includes the PCR itself. Each data set comprises an ancillary data set prefix and a data block of ancillary data. The prefix includes field MF, CFF, AFID, and AFS. The field MF is a 1-bit field that indicates whether the data in the packet is correctable (1 being correctable and 0 being not). The CFF is a 1-bit field that indicates whether ancillary data is defined for the data set. The AFID is a 6-bit field indicating the type of auxiliary data, such as time code, scrambling key, copyright, etc., contained in the data set, and the AFS is an 8-bit field defining the number of bytes of auxiliary data contained in the data set.

The AUX1 data group is shown as being correctable and the AUX2 data group is shown as being uncorrectable. The AUX2 data is shown as PCR data, i.e. a program clock reference. The AUX1 data is indicated as DPCR data, which is here an abbreviation for different program clock references. The PCR data is obtained under the control of a programmer controlling the transport processor in the encoder. The acquisition of DPCR data will be explained with reference to the description of figure 4.

The device of fig. 4 is a typical device that is part of a multiplexer circuit shown in fig. 2. Associated with each input bus is a buffer memory 67, which may be of the FIFO type. When program data arrives and its multiplexer is currently accessing a different input bus, the data is stored therein. Subsequently, the program data is read out from the buffer memory 67 in accordance with the program of the multiplexer.

Each transmission packet of program data includes an auxiliary data set containing PCR and DPCR data. It should be noted that the value of the PCR data is determined with respect to the timing of the transmitted data packet containing the auxiliary timing information. When the PCR data is output by the multiplexer, it may be erroneous due to any delay incurred by contention for the signals in the multiplexing process. The delay time T ± δ T taken through the buffer memory is used to modify the DPCR data to subsequently correct for such errors. An auxiliary data packet detector 61 arranged to detect the presence of transport data packets containing DPCR data is connected to the program data input bus. This detector function resets and starts a counter 62 to count the counting pulses of the local clock 60. The local clock 60 may be a crystal oscillator having a clock frequency very close to the encoder system clock frequency, or may be a frequency that is locked to the encoder clock frequency whenever the apparatus of fig. 3 or 5 is operating. Another auxiliary data packet detector 63 is coupled to the output bus of buffer memory 67 for storing the current count value output by counter 62 in latch 68 when an auxiliary data packet containing DPCR data emerges from the buffer. The output of the counter at this point will appear as a count of a few units of the clock frequency period, i.e. the transit time of the buffer through a particular data packet. It should be noted that the auxiliary packet detector must be used to detect and respond to the first occurring packet if it is possible that multiple auxiliary packets may occur adjacent to each other such that more than one packet may pass to the buffer 67 simultaneously.

The auxiliary data packet detector 61 also provides a control signal that is used to set the latch 64 to store the DPCR value contained in the auxiliary data packet. This value is fed to an input port of an adder 65 and the local count value stored in latch 68 is added to a second input of the adder 65. Adder 65 adds the DPCR data from the current auxiliary data packet to the local count value to provide a refreshed DPCR value DPCR'. The program data from buffer 67 and the output of adder 65 are coupled to input ports of a 2-to-1 multiplexer 66. The multiplexer 66 is set by the auxiliary packet detector 63 so as to normally transmit the program data. However, when DPCR data contained in the program data emerges from the buffer, the multiplexer 66 is set to transfer the refreshed DPCR' data from the adder, and then switches back to transfer the data from the buffer 67.

When the multiplexer 66 is set to transmit data from the adder, the output signal from the adder corresponds to the sum of the DPCR data included in the auxiliary data packet and the count value in the counter 62 when the DPCR data emerges from the buffer. Therefore, the data substitution for the DPCR data by the multiplexer 66 precedes the DPCR data correction for its transmission time in the buffer 67. It should be noted that it is provided that the auxiliary data packet detector is programmed to change the program data only in dependence of the appropriate modification flag MF with the auxiliary data set.

Returning again to fig. 2, the transport processor 53 will create DPCR auxiliary data sets and typically insert a zero value as DPCR data corresponding to the new program. However, it is contemplated that stored data from the data storage medium 51 may be inserted between live data segments, and that the stored data may be previously encoded using PCR and DPCR codes. When the transport processor 53 inserts the stored data between base sections of live data, it accesses the PCR code of the stored data and subtracts the PCR value from the current count value presented by the counter 23 and/or latch 25. The transport processor then adds this difference to the DPCR value in the secondary packet storing the data. The new DPCR value inserted in the stored data between live data now contains a reference to the current time. This process is illustrated in the flow chart of fig. 8, which has been described in itself.

The use of DPCR data in the receiver is illustrated in fig. 5. In fig. 5, components having the same reference numerals as those in fig. 3 except that the function of the unit 32 has been improved are similar components and perform similar functions. The improvement involves the inclusion of an adder 45 for summing the corresponding PCR and DPCR values achieved in the associated auxiliary data set. The sum value provided by the adder corresponding to the original PCR value is increased by any delay introduced, such as during multiplexing. These sum values are placed in memory 46 from which clock controller 39 can obtain the sum values as values for the corrected PCRs for synchronization of the system clock.

Claims (5)

1. A video encoder, comprising:

a compressor (11) for compressing the video signal;

a formatter (12) for formatting said video signal into at least one transport packet for transmission over a network; and

a transport processor (13) operable to incorporate into said transport data packet an auxiliary data field having a program clock reference field representing a time stamp, said auxiliary data field providing information for use in deriving decoder timing at the decoder; and is operable to incorporate into the transport packet a control field indicating whether the auxiliary data field in the transport packet containing the clock reference field is defined in the transport packet.

2. A method for synchronizing timing in an encoder from the encoder to a decoder, comprising the steps of:

compressing the video signal;

formatting the video signal into at least one transport packet for transmission over a network;

incorporating into said transport packet an auxiliary data field having a program clock reference field representing a time stamp, said auxiliary data field providing information for deriving decoder timing at a decoder; and

incorporating into the transport packet a control field indicating whether the auxiliary data field in the transport packet containing the clock reference field is defined in the transport packet.

3. The method of claim 2, wherein the video signal is incorporated into a plurality of transport packets.

4. The method of claim 3, wherein the auxiliary data field is present in selected ones of the plurality of transport packets.

5. The method of claim 3, wherein the program clock reference field is present in selected ones of the plurality of transport packets.