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WO2002009191A3 - Non-volatile memory element - Google Patents

Non-volatile memory element Download PDF

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Publication number
WO2002009191A3
WO2002009191A3 PCT/US2001/022569 US0122569W WO0209191A3 WO 2002009191 A3 WO2002009191 A3 WO 2002009191A3 US 0122569 W US0122569 W US 0122569W WO 0209191 A3 WO0209191 A3 WO 0209191A3
Authority
WO
WIPO (PCT)
Prior art keywords
accommodating buffer
buffer layer
layer
silicon
amorphous interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/022569
Other languages
French (fr)
Other versions
WO2002009191A2 (en
Inventor
Jeffrey M Finder
Kurt Eisenbeiser
Jerald A Hallmark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to AU2001273553A priority Critical patent/AU2001273553A1/en
Publication of WO2002009191A2 publication Critical patent/WO2002009191A2/en
Publication of WO2002009191A3 publication Critical patent/WO2002009191A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H10P14/69398—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0415—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having ferroelectric gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/701—IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
    • H10P14/6329—
    • H10P14/6332—
    • H10P14/6339—
    • H10P14/69215—

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

High quality epitaxial layers (26) of compound semiconductor materials can be grown overlying large silicon wafers (22) by first growing an accommodating buffer layer (24) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Utilizing this technique permits (20) the fabrication of thin film non-volatile memory elements on a monocrystalline silicon substrate.
PCT/US2001/022569 2000-07-24 2001-07-18 Non-volatile memory element Ceased WO2002009191A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001273553A AU2001273553A1 (en) 2000-07-24 2001-07-18 Non-volatile memory element on a monocrystalline semiconductor substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62475400A 2000-07-24 2000-07-24
US09/624,754 2000-07-24

Publications (2)

Publication Number Publication Date
WO2002009191A2 WO2002009191A2 (en) 2002-01-31
WO2002009191A3 true WO2002009191A3 (en) 2002-05-23

Family

ID=24503188

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/022569 Ceased WO2002009191A2 (en) 2000-07-24 2001-07-18 Non-volatile memory element

Country Status (3)

Country Link
AU (1) AU2001273553A1 (en)
TW (1) TW503580B (en)
WO (1) WO2002009191A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019066959A1 (en) * 2017-09-29 2019-04-04 Intel Corporation Ferroelectric neurons and synapses
DE102020127831A1 (en) 2020-05-29 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. MEMORY ARRAY GATE STRUCTURES
US11695073B2 (en) 2020-05-29 2023-07-04 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array gate structures
DE102021101243A1 (en) 2020-05-29 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. MEMORY BLOCK CHANNEL REGIONS
US11710790B2 (en) 2020-05-29 2023-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Memory array channel regions
US11640974B2 (en) 2020-06-30 2023-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array isolation structures
US11729987B2 (en) 2020-06-30 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Memory array source/drain electrode structures
US11647634B2 (en) 2020-07-16 2023-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
US11355516B2 (en) 2020-07-16 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
CN117016050A (en) * 2021-08-27 2023-11-07 华为技术有限公司 Ferroelectric memory, method of forming the same, and electronic equipment
US20230200081A1 (en) * 2021-12-21 2023-06-22 Intel Corporation Transistor devices with perovskite films
CN116056551A (en) * 2023-03-31 2023-05-02 北京航空航天大学 A kind of antiferromagnetic tunnel junction and its preparation method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5248564A (en) * 1992-12-09 1993-09-28 Bell Communications Research, Inc. C-axis perovskite thin films grown on silicon dioxide
US5418389A (en) * 1992-11-09 1995-05-23 Mitsubishi Chemical Corporation Field-effect transistor with perovskite oxide channel
US5959879A (en) * 1997-06-09 1999-09-28 Samsung Electronics Co., Ltd. Ferroelectric memory devices having well region word lines and methods of operating same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5418389A (en) * 1992-11-09 1995-05-23 Mitsubishi Chemical Corporation Field-effect transistor with perovskite oxide channel
US5248564A (en) * 1992-12-09 1993-09-28 Bell Communications Research, Inc. C-axis perovskite thin films grown on silicon dioxide
US5959879A (en) * 1997-06-09 1999-09-28 Samsung Electronics Co., Ltd. Ferroelectric memory devices having well region word lines and methods of operating same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
RAMESH R ET AL: "FERROELECTRIC LA-SR-CO-O/PB-ZR-TI-O/LA-SR-CO-O HETEROSTRUCTURES ON SILICON VIA TEMPLATE GROWTH", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 63, no. 26, 27 December 1993 (1993-12-27), pages 3592 - 3594, XP000416479, ISSN: 0003-6951 *

Also Published As

Publication number Publication date
AU2001273553A1 (en) 2002-02-05
TW503580B (en) 2002-09-21
WO2002009191A2 (en) 2002-01-31

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