WO2002063675A1

WO2002063675A1 - Integrated circuit, method of testing integrated circuit and method of manufacturing integrated circuit

Info

Publication number: WO2002063675A1
Application number: PCT/JP2001/000756
Authority: WO
Inventors: Masayoshi Hishinuma; Masayuki Satoh
Original assignee: Hitachi, Ltd.
Priority date: 2001-02-02
Filing date: 2001-02-02
Publication date: 2002-08-15
Also published as: TWI246735B; JPWO2002063675A1

Abstract

A spiral conductor pattern is formed on an insulating film over an integrated circuit chip. One end of the pattern is connected to an input and output terminal of a test circuit. The test circuit has input and output circuits that include a transmitting circuit for driving the conductor pattern as an induction coil or an antenna to transmit a signal, and a receiving circuit for detecting the changes in current or voltage of the conductor pattern to discriminate an external signal to the induction coil or the antenna. Data is transferred to and from an external control device in noncontact manner.

Description

Description: Semiconductor integrated circuit, inspection method, and manufacturing method

The present invention relates to a semiconductor integrated circuit and a test technique and a manufacturing technique thereof, and more particularly to a technique for facilitating exchange of test data with an external control device in a semiconductor integrated circuit having a built-in test circuit. The present invention relates to a technology effective when applied to a semiconductor integrated circuit such as a large-scale integrated circuit), an inspection method and a manufacturing method thereof. Background art

Conventionally, as a design method for testability in a logic LSI called a system LSI equipped with a RAM (random access memory) or CPU, a flip-flop that constitutes an internal logic circuit is connected serially. A scan path method is often used in which test data is input and the internal logic circuit is operated to output the logic state serially for inspection.

In addition to the above-mentioned scan path method, there is a BIST (built-in-in-self-test) method in which a random pattern generator and a signature compressor are mounted on a chip as a test circuit.

By the way, in the scan test method, at least four test terminals are required for controlling a scan path. Also, in the BIST method, several test terminals are required to activate the test circuit in the chip and to output test results. In each of the test methods, a device called a tester is connected to the test terminal, and the test is executed.

Conventionally, logic LSIs equipped with the test circuit described above are tested by contacting the probe with the pads of the semiconductor chip at the wafer stage, as well as by testing when the semiconductor chip is sealed in a package. Software provided on the The test was conducted in two stages of the burn-in test, in which the IC was inserted into the socket. In the burn-in test, an LSI is generally mounted on each of a plurality of sockets provided on a test board, and a plurality of LSIs are simultaneously tested.

However, as described above, each chip has at least a few test terminals, and these test terminals must be connected to external test equipment. In testing, when testing many chips at the same time, it is necessary to bring an enormous number of probes into contact with the corresponding pads of the chips, making alignment extremely difficult and ensuring that each probe is sufficiently tested. It is also difficult to make contact with a high pressure. Also, in the inspection using a test board, the device encapsulated in the package has a much larger volume than the chip, which lowers the mounting density and increases the number of test terminals on the board. Since the number of wirings to be increased increases, the number of LSIs that can be tested at one time is limited, which has led to an increase in test costs.

An object of the present invention is to provide a semiconductor integrated circuit capable of operating a test circuit inside a chip and obtaining the test result without providing a test terminal (pad or pin) on each chip, and a test method and manufacturing method thereof. It is to provide a method.

Another object of the present invention is to reduce the number of terminals (pads and pins) that need to be connected at the time of testing, and to greatly increase the number of chips that can be tested simultaneously. And a test method and a manufacturing method thereof.

It is still another object of the present invention to provide a semiconductor integrated circuit capable of performing the same test in a state of a wafer and in a state of being sealed in a package, a test method thereof, and a manufacturing method thereof.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The outline of a representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a semiconductor integrated circuit having a built-in test circuit is provided with a circuit for transmitting and receiving data to and from an external control device in a non-contact manner and a transmitting and receiving means. Specifically, for example, a spiral conductive layer pattern is formed on a semiconductor integrated circuit chip via an insulating film, and one end thereof is connected to the input / output terminal of the test circuit and the input / output terminal of the test circuit is connected to the input / output section of the test circuit. Is a transmission circuit that transmits a signal by driving the conductive layer pattern as an induction coil or an antenna, and detects a change in current or voltage flowing in the conductive layer pattern and detects a signal transmitted from the outside to the induction coil or the antenna. A receiver circuit for discriminating signals is provided to transmit and receive data to and from an external control device in a non-contact manner. Further, an opposing electrode may be provided instead of an induction coil or an antenna to transmit and receive data using electrostatic capacitive coupling, or a light emitting element and a light receiving element may be provided to transmit and receive data by an optical signal.

According to the above-described means, the test circuit inside the chip can be operated and the test result can be obtained without providing a test terminal (pad or pin) on each chip. The number of probes from the test equipment that need to be contacted during the test can be reduced. In addition, since the positioning between the tip and the prober is easy and a large contact pressure is not required, more chips can be tested at the same time, thereby greatly reducing the test cost. be able to. Furthermore, since the chip can be tested in a non-contact manner, the same test can be performed in a wafer state and in a packaged state, and the reliability of the product can be improved. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a plan view showing a configuration example at a wafer level on which a semiconductor integrated circuit according to the present invention is formed.

Fig. 2 is a perspective view showing an example of the configuration of an apparatus for inspecting each semiconductor chip on a wafer. is there.

FIG. 3 is a perspective view showing another configuration example of an apparatus for inspecting each semiconductor chip on a wafer.

FIG. 4 is a flowchart showing an outline of a procedure for inspecting each semiconductor chip on a wafer.

FIG. 5 is an explanatory diagram showing a display example in the case of displaying a result of inspection of each semiconductor chip on a wafer.

FIG. 6 is a block diagram showing a first embodiment of a system LSI as an example of a semiconductor integrated circuit suitable for applying the present invention.

FIG. 7 is a block diagram showing a configuration example of the interface circuit 200 using the TAP shown in FIG.

FIG. 8 is a block diagram showing another configuration example of the transmission / reception circuit provided in the TAP 200.

FIG. 9 is a plan view and a cross-section showing a device structure of an embodiment in which the present invention is a semiconductor device having a CSP (chip size package) structure in which different semiconductor memories such as a flash memory and a SRAM are stacked. FIG.

FIG. 10 is a flowchart showing the procedure of developing and manufacturing the system LSI shown in FIG. 6 as an example of a semiconductor integrated circuit device.

FIG. 11 is a flowchart showing a more detailed test procedure in the wafer test in step S18 of FIG. 10 and the port test in step S22. The best form to cool the invention

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1A shows a first embodiment of the present invention. In FIG. 1A, WF is a single semiconductor wafer such as single crystal silicon, and 100 is a semiconductor integrated circuit formed on the wafer WF. A plurality of semiconductor integrated circuits 100 are simultaneously formed on a wafer WF by a known semiconductor manufacturing technique, and are cut along a grid-like scribe area provided between circuits in a final step of the process. Independent After being made into chips, they are packaged or molded with resin before being shipped as products. Hereinafter, a semiconductor integrated circuit before being cut and a semiconductor integrated circuit before being cut and sealed in a package are referred to as chips.

As shown in FIG. 1A, in the present embodiment, a spiral pattern 11 used as an induction coil described later is formed for each chip. The spiral pattern 11 is composed of a conductive layer such as aluminum formed on each chip via an insulating film. The end of the spiral pattern 11 is connected to a later-described transmitting / receiving circuit provided on the chip. In this embodiment, power is supplied via a power supply pad 21 provided for each chip. FIG. 1 (B) shows a second embodiment of the present invention. In this embodiment, a common power supply pad 22 for receiving the supply of a test power supply voltage is provided on the periphery of the wafer WF. Although not shown, a power supply line for supplying power to each chip from the power supply pad 22 is provided, for example, in a scribe area between each chip 100 of the wafer, and one end of this power supply line is connected to the common power supply pad 22. The other end is connected to the power pad of each chip. The power supply pad 22 and the power supply line can also be formed by the conductive layer constituting the spiral pattern 11.

FIG. 1 (C) shows a third embodiment of the present invention. In the embodiment of FIG. 1 (A), spiral patterns 11 serving as induction coils are formed corresponding to the respective chips 100 on the wafer WF, whereas the spiral pattern 11 of FIG. 1 (C) is formed. In the embodiment, one spiral pattern 11 is formed in common to all chips, that is, one spiral pattern is formed on the whole wafer. The terminals of the transmitting and receiving circuits of each chip are commonly connected to the spiral pattern 11 via wiring formed in the scribe area. Further, a power supply pad 22 common to each chip is provided on a peripheral portion of the wafer WF to receive a power supply voltage for testing. In addition, since the inductive coil can be used not only for transmitting and receiving signals but also for supplying power, it is possible to provide a power supply circuit including a rectifier circuit on each chip and omit a common power supply pad 22 for testing. .

FIG. 2 shows a schematic configuration example of an apparatus for detecting each chip on the wafer WF. FIG. 2 shows an example of the configuration of a test apparatus corresponding to the embodiment of FIG. 1 (A). FIG. 3 shows an example of the configuration of a test apparatus corresponding to the embodiment of FIG. 1 (C).

In FIG. 2, reference numeral 300 denotes a control device, 310 denotes a cable extending from the control device 300, and 320 denotes a probe card provided at the tip of the cable 310. A pair of probes 3 21 for supplying a power supply voltage are mounted on the lower surface of 320, and a coil 3 222 is mounted in the center of the card.

In the test apparatus shown in FIG. 2, the diameter of the coil 32 2 provided on the probe card 320 is substantially the same as the diameter of the coil (1 1) provided on the chip 100. The wafer WF is placed on an XY stage 400 that can move in the orthogonal X-axis and Y-axis directions, respectively, and the probe card 300 approaches the chip 1 The probe 3 2 1 to the power pad (2 1) of the chip. At this time, positioning is performed such that the center of the coil 3222 coincides with the center of the spiral pattern (11) provided on the chip to be tested. When the test of one chip is completed, the stage 400 is skipped by one chip, and the coil (3 1 2) of the probe card 3 2 0 faces the coil (1 1) of the next chip, and the probe 3 2 1 is also contacted with the power supply pad (2 1) of the next chip.

In the test apparatus of FIG. 3, the diameter of the coil 32 provided on the probe card 320 is substantially the same as the diameter of the coil provided on the wafer WF. The stage 400 on which the wafer WF is mounted may be a fixed type. The probe 3221 provided on the probe card 320 is provided so as to be able to contact the common power supply pad 22 on the wafer WF.

Although not shown, the test apparatus corresponding to the embodiment of FIG. 1B has a configuration having both the configuration of the apparatus of FIG. 2 and the configuration of the apparatus of FIG. That is, two probe cards are provided, and one of the cards is provided with a small-diameter coil 32, which is almost the same as the coil 11 on the chip 100, as in the apparatus of FIG. And the probe card 320 are relatively movable. The other card is provided with a pair of probes 3 21 that can contact the power pad 22 common to each chip on the wafer WF, and cannot move relative to the stage 400, that is, the stage And power is supplied to the wafer at all times. FIG. 4 shows a test procedure performed by the test apparatus shown in FIG. During the test, the probe 321 of the probe card 3 20 connected to the controller 300 is brought into contact with the power supply pad 21 of each chip or the common power supply pad 22 on the wafer WF to supply the power supply voltage to each chip. Then, the test circuit inside the chip is started and the self test is started (Step S1). When the test is completed, each chip outputs a test end signal via the coil 11 or 12 (step S 2), and then outputs a signal indicating the test result (defect “absent” or “absent”). (Step S3). In addition, when the test is performed by the test apparatus of FIG. 3, the identification code is stored in each chip, and each chip outputs the chip identification code together with the test result.

Upon receiving the test end signal, control device 300 stores the test result transmitted subsequently to the memory for each chip. Then, for example, as shown in Fig. 5, the test results of each chip are mapped and displayed on the screen of the display device using the symbols 〇 and X corresponding to the chip positions on the wafer, or printed on paper by a printer. It is configured to print and output.

FIG. 6 shows a first embodiment of a system LSI as an example of a semiconductor integrated circuit suitable for applying the present invention.

6, reference numerals 110 to 180 denote internal circuits formed in the semiconductor chip 100, and 190 denotes input / output of signals between these internal circuits and other external semiconductor integrated circuits and the like. The interface circuit, BUS, is an internal path connecting the internal circuits 110 to 180 and between the internal circuits 110 to 180 and the interface circuit 180.

Of the above internal circuits 110 to 180, 110 and 120 are custom logic circuits, such as user logic circuits, that constitute the logic functions required by the user, of which 120 constitutes arbitrary logic It consists of a possible FPGA (field 'programmable' gate 'array). In this embodiment, a test circuit is configured in the FPGA 120, and user logic is configured after the test is completed. However, this FPGA 120 may be left as it is without configuring the user logic. 1 20 Is a CPU (Central Processing Unit) that decodes program instructions and executes corresponding processing and operations; 130 and 140 are static RAMs (random 'access'memories); and 150 to 170 are dynamic RAMs. The interface circuit 190 is not particularly limited, but the interface circuit 5V I / F for transmitting / receiving signals to / from the 3I system 3I and the signal between the 3.3V system LSI and Interface circuit for transmitting and receiving 3.3 Includes 3V I / F.

Furthermore, the system LSI of this embodiment is specified by the IEEE 1149.1 standard in order to input and output signals to and from external test equipment when testing the internal circuits 110 to 180. A test interface circuit (hereinafter referred to as TAP) 200 is added to the TAP '(test' access' port), which adds a circuit that enables transmission and reception via a coil. Because of the provision of the TAP 200, the test device (control device 300 in FIG. 2) connected to the semiconductor integrated circuit of the present embodiment is a high-performance device such as a conventional logic LSI or memory tester. Instead, a device capable of writing and reading data and simple data processing may be used. For example, a personal computer may be used as the control device 300.

In the LSI of this embodiment, one end of a spiral conductive layer pattern 11 provided for each chip is connected to the input / output terminal of the TAP 200, and the conductive layer pattern 1 is connected to the TAP 200. A transmission circuit that transmits a signal by driving 1 as a coil, and a reception circuit that detects a change in current or the like flowing through the conductive layer pattern and discriminates a signal sent from the outside to the coil, It is configured to be able to send and receive data to and from external test equipment without contact.

The static RAMs 140 and 150 and the dynamic RAMs 160 to 180 include memory peripheral circuits such as an address decoder that selects a corresponding memory cell when an address signal is given via the internal path BUS. Including. Further, the dynamic RAMIs 60 to 180 include a refresh control circuit that performs pseudo-selection periodically so that the information charges of the memory cells are not lost even when the non-access time is long. In addition, although not particularly limited, in this embodiment, the dynamic RAMIs 60 to 180 include, when there is a defective bit in the memory array, the defective bit. A so-called redundant circuit is provided to replace a memory row or a memory column containing a with a spare memory row 161-181 or a spare memory row 162-182.

In this embodiment, by using the FPGA 120, a logic test circuit for testing the custom logic circuit 110, the CPU 130, and the like, and a memory test circuit for testing SRAM and DRAM can be configured. . In addition, instead of configuring a test circuit with the FPGA 120, the CPU 130 is tested using the test circuit configured in the FPGA 120, and then a test pattern is generated in the CPU 130 according to a predetermined algorithm. A test circuit composed of an ALPG (algorithmic pattern generator) may be configured to test the custom logic circuit 11 ◦ and the memories 140 to 180.

In addition, instead of configuring a test circuit with the FPGA 120 and CPU 130, a block is created for each circuit block such as custom logic circuit 10, CPU 130, SRAMI 40, 150, and DRAM 160 to 180. A BIST circuit that performs a test in units is provided, and the BIST circuit is connected to the TAP 200, so that signals can be exchanged between the BIST circuit and external test equipment via the TAP 200. May be. Further, it is also possible to provide a test scan path for the entire chip or for each circuit block, and to perform a test using the scan path control function of the TAP 200.

The technology that enables the test to be constructed by using an FPGA formed on a chip to construct an AL PG that generates a test pattern for testing a logic circuit or memory according to a predetermined algorithm has already been proposed by the present applicant. For example, it is disclosed in International Publication WO 00/62339 and the like, and its technology can be used. The invention of the prior application is intended to reduce the hardware overhead associated with mounting the test circuit by configuring a user logic circuit in the FPGA after the test is completed. Similarly, in the example LSI, the hardware overhead can be reduced by configuring the user logic circuit in FPGA after the test is completed. FIG. 7 shows a configuration example of the TAP 200 shown in FIG. TAP is a scan test and a control circuit for the BIST circuit specified in the IEEE 1149.1 standard. In this embodiment, the original TAP specified in the IEEE 1149.1 standard is used. TAP section 210 composed of a TAP section 210 and a pair of terminals P 1 and P 2 to which a coil composed of a spiral pattern is connected. And a transmission / reception unit 220 that transmits and receives data to and from the transmission / reception unit.

Of these, the TAP section 210 is a bypass register 211 used to shift test data from an input port to an output port, a data register 211 used to transmit a specific signal to a circuit, and a chip. Device ID register 2 13 for setting a unique manufacturing identification number, Instruction register 2 14 used to control data register selection and internal test methods, Controller for controlling the entire TAP section 210 It consists of 2 15 etc.

The above data register 2 1 2 is a register treated as an option. In addition, four mandatory instructions and three optional instructions are prepared for instructions set in the instruction register 214. The test mode select signal TMS, test clock TCK, and reset signal TRST for specifying the test mode are input to the controller 215 from three dedicated external terminals, and based on these signals, The control signals for the registers 211 to 214 and the selector circuits 211 to 218 are formed.

The TAP section 210 is provided with an input terminal for test data TDI and an output terminal for test result data TDO. The input test data TDI is supplied to each register 2 through the selector circuit 2 16. Supplied to 11 to 2 14 or internal scan path Iscan, Bscan. In addition, the contents of the registers 211 to 214 and the scan-out data from the internal circuit are output to the outside of the chip via the selector circuits 217 and 218. Further, a signal to the internal BIST circuit is formed and supplied to the TAP section 210 according to the contents of the data register 212 and the instruction register 214, and the test result output from the BIST circuit is shown. The signal is configured to be output as test result data TDO through the selector circuits 217 and 218.

The transmission / reception unit 220 is provided between the TAP unit 210 and the external terminals Pl and P2 to which the spiral pattern 11 is connected. Driving and transmitting signals, detecting changes in the current flowing through the coil and discriminating signals sent from outside, TD I, TR S Τ, TMS and TCK according to TAP standards Is a circuit that generates.

Specifically, the transmitting / receiving unit 220 includes a switching circuit 22 1 connected to the external terminals P 1 and P 2 to which the spiral pattern 11 is connected via a mutual inductive coupling MIC including a pair of inductors. Demodulation circuit 222 demodulates carrier and data from the signal, source circuit 231 synchronizes the carrier signal demodulated by source oscillator 231 and demodulator circuit 22 2 with the oscillation signal of source oscillator 231, oscillation signal of source oscillator 231 A clock generation circuit 223 composed of a doubling circuit 233, etc., which multiplies the frequency of the input signal, a test mode select signal TMS for the test input data TDI and the TAP controller 215 by decoding the input data demodulated by the demodulation circuit 222 And a decoder circuit 224 that generates a reset signal TR ST and a scan clock BCLK, a ROM 225 storing the chip identification code, and test result data from the TAP section 210. Enko one hard circuit 226 for adding an identification code to the TDO, and a like modulation circuit 22 7 for outputting put the code generated by Enko one hard circuit 2 26 on a carrier wave.

The second clock of the source oscillation signal generated by the click generation circuit 223 is supplied to the TAP controller 215 as a test clock TCK, and the source oscillation signal is supplied to the modulation circuit 226 as a carrier. As the modulation method in the modulation circuit 230, for example, ASK modulation (amplitude modulation) or PSK modulation (phase modulation) can be used.

In the system LSI of the embodiment shown in FIG. 6, the self-test circuit built on the FPGA 120 and the CPU 130 is regarded as a BIST circuit, and the signal input / output function for the BIST circuit included in the TAP 200 is used. , For FPGA 120 and CPU 130 Input the setting signal and data for the self-test, and output the test result.

In FIG. 7, "Iscan" is a test path for diagnosing the internal logic circuit by using a shift register in which flip-flops constituting the internal logic circuit are connected in a chain as a scan path for test data. means. "Bscan" uses a flip-flop, which is provided in the signal input / output section (interface circuit 190 in FIG. 6), in a chain form as a scan path, and uses it as a scan path. A test path for diagnosing the connection status with the semiconductor integrated circuit (boundary scan test).

In a semiconductor integrated circuit using a TAP defined by the IEEE 1149.1 standard, the configuration of a test circuit in an internal circuit and the loading of a test program in a chip are performed through the TAP. A semiconductor integrated circuit device that requires only a few (4 to 5) terminals required for testing can be realized. In other words, the TAP is a standardized circuit, and the self-test can be executed with 4 to 5 test terminals.By applying the TAP, the number of terminals required for testing is small, and the LSI The number of terminals can be reduced. Further, in the interface circuit 200 using the TAP of this embodiment, a computer generation circuit 223 is internally provided, and a decoder circuit ′ 2 for decoding received data and generating a control signal is provided. By providing 24, complete serial I / O is possible, and the only required terminals are the terminals P 1 and P 2 to which the spiral pattern 11 as a coil is connected. FIG. 8 shows another embodiment of the transmission / reception circuit 220 provided in the TAP 200.

In FIG. 8, reference numeral 2 28 denotes a diode bridge connected between both terminals of the coil spiral pattern 11 1) and rectifying an AC signal input from the coil 11 1 to generate a DC power supply voltage. A rectifier circuit 229 monitors a voltage output from the rectifier circuit 228, detects that a signal has been input to the coil (11), and generates a start signal ST. Is a data receiving circuit that is connected between both terminals of the coil (11) and shapes and outputs the input AC signal waveform. On the basis of the adjusted signal, a pair of drive MOS FETs Qdl and Qd2, each having a drain terminal connected to each terminal of the coil (11) via capacitances Ct1 and Ct2, are turned on. This is a data transmission circuit consisting of a drive circuit that transmits data by switching off the resonance circuit consisting of the capacitances Ct1, Ct2 and the coil (11) when the device is turned off and switches between the resonance state and the nonresonance state.

The capacitances Ct1 and Ct2 may be formed in a chip, but may be formed in a scribe area between chips in order to suppress an increase in chip size. Further, in the above-described embodiment, the power supply pad 22 is provided from the power supply pad 21 of the chip or on the wafer, and the power supply voltage for the test is supplied from the power supply pad 22. A voltage limiter circuit that generates a power supply voltage Vcc of a predetermined potential by absorbing a change in the voltage rectified by the rectifier circuit in a stage subsequent to 228, and a series regulator that stabilizes the power supply voltage Vcc generated by the limiter circuit. A power supply stabilization circuit consisting of a power supply and the like is provided, and the power supply voltage output from this power supply stabilization circuit is supplied to each circuit inside the chip. You may comprise so that a voltage may be given.

FIG. 9 shows a device structure of an embodiment in which the present invention is a semiconductor device having a CSP (chip size'package) structure in which different semiconductor memories such as a flash memory and an SRAM are overlapped.

In FIG. 9, reference numeral 500 denotes an insulating substrate on which printed wiring is formed, reference numeral 501 denotes a bump formed on the lower surface of the substrate 500, and reference numeral 520 denotes a first memory such as a flash memory mounted on the upper surface of the insulating substrate 500. The memory 530 is a second memory such as an SRAM mounted on the memory 520. Between the flash memory 520 and the insulating substrate 500, the SRAM 530 and the flash memory 520 are respectively connected by an adhesive or the like. Although not shown, a test circuit and a transmission / reception circuit are provided inside the chips of the flash memory 520 and the SRAM 530, respectively.

The SR AM 530 has a smaller chip size than the flash memory 520, and the flash memory 520 protrudes outside the SRAM 530 with the SRAM 530 mounted on the flash memory 520. Pad rows 52 1, 522 are formed between the pad rows 521, 522 and the corresponding pad sections on the insulating substrate 500 and pads IJ53 1, 532 and corresponding pad portions on the insulating substrate 500 are electrically connected by bonding wires 541 to 544, respectively.

In this embodiment, a spiral pattern 11 made of a conductive layer is formed on the surface of or in the insulating substrate 500 below the memory chip, and connection wires 11a, 11a and 11a are formed from both ends of the spiral pattern 11 respectively. lib is drawn out, and the pads 551, 552 provided at the ends of these wirings 11a, 11b and the input / output terminals of the transmission / reception circuits provided on the chips 520, 530 (FIG. 7) Terminals F1 and P2) are also connected by bonding wires.

Therefore, the spiral pattern 11 on the substrate is used as a common coil of the flash memory chip 520 and the SRAM chip 530, and a signal for test is input / output to each chip via this coil. . In this way, even if signals are input / output via the common coil, different identification codes are stored in each chip, and the identification codes are transmitted together with the test results during transmission / reception. The test equipment can identify which chip is the test result.

Next, the procedure of developing and manufacturing the system LSI shown in FIG. 6 as an example of a semiconductor integrated circuit device will be described with reference to FIG.

In the development of a semiconductor integrated circuit device, first, the logic function of the semiconductor integrated circuit to be developed is designed (step S11). This logic function design is generally performed using HDL. Note that EDA vendors provide a support tool (program) for automatically creating HDL descriptions from state transition diagrams and flowcharts, so that HDL descriptions can be performed efficiently. The design data described in HDL is subjected to a virtual test for verifying proper operation by a verification program that generates a test pattern called a test vector. If any defects are found by the virtual test, correct the HDL description. Next, circuit design at the logic gate level is performed based on the data designed in step SI1 (step S12). Specifically, cells such as logic gates and flip-flops that constitute a circuit having a desired function are designed. Then, based on this design data, logic synthesis is performed to create design data in which connection information between each logic gate and cell is described in the form of a netlist (step S13). When a desired logic function is configured on an LSI for which a logic gate circuit has already been designed, such as a gate array, the circuit design in step S12 can be omitted. Also here, a program called Logic Synthesis Tool that converts design data described in HDL into design data at the logic gate level and synthesizes it is provided by the EDA vendor. . The generated logic gate-level design data is verified again by the test 'vector (virtual tester). If a defect is found by the virtual tester, correct the design data at the logic gate level.

Next, element-level layout data is generated by a program called an automatic layout tool based on the logic gut-level design data described in the netlist format (step S14). These automated layout tools are also provided by several EDA vendors. Then, the layout of the chips on the wafer is determined (step S15). At this time, the layout of the spiral pattern of the coil formed on each chip and the layout of the wiring connecting the coil and the transmitting / receiving circuit in the chip are also determined. Then, mask pattern data is generated by an artwork based on the determined layout data, and a mask is created based on the data (step S16).

After that, a semiconductor integrated circuit is formed by performing processing such as diffusion processing and wiring pattern formation on the semiconductor wafer in the previous process (step S17). Then, the test is started by setting the wafer in the test apparatus and facing the probe card (step S18). In this embodiment, the test apparatus shown in FIG. 2 is used for this wafer test. At this time, the probe of the probe card is brought into contact with the power supply pad of each chip on the wafer and the coil is opposed, so that the wafer test is disconnected. It is done by touch. Then, when the wafer test is completed, dicing for dividing the wafer into chips is performed (step S19).

The divided chips are sealed in a package with a sealing material such as resin (Step S20). At this time, the chips determined to be defective in the wafer test in step S18 are removed in advance. Then, the semiconductor integrated circuit device package state, from being placed at a high temperature. Under the aging (or burn) device, a test is performed again by the test device package one di state (step S 21, S 22) ₀ The The test content at this time is almost the same as the content of the wafer test performed in step S18, and the power supply voltage from the socket mounted on the test board to the device under test is the same as in the wafer test. The test data is transmitted to the device under test and the test result is received from the device under test via the coils facing each other. Those that are determined to be defective in this test are marked on the package surface (step S23), removed in the sorting process, and only non-defective products are packed and shipped (step S24).

FIG. 11 shows a more detailed test procedure in the wafer test in step S18 and the board test in step S22.

In each test, first, it is checked whether the FPGA 120 operates normally, and it is determined whether or not there is a defect. If there is a defect, the defect is avoided (step S101, step S101).

~ S 103). Next, a test circuit (AL PG) for testing the SRAMs 140 and 150 is constructed in a portion of the FPGA 120 excluding the above-mentioned defective portion, and the tests of S, RAMI 40 and 150 are sequentially executed. (Steps S104, S1

05).

If no defect is found in the SRAMIs 40 and 150, a test circuit for testing the custom logic circuit 110 and the CPU 130 is provided in the portion of the FPGA 120 except for the defect. A logic tester is constructed, and the tests of the custom logic circuit 110 and the CPU 130 are executed (steps S106 to S108). At this time, a test pattern or a test pattern generation program is stored using the SRAM that has already been tested. If no defect is found, a test circuit (ALPG) for testing the DRAMs 160 to 180 is constructed in the portion of the FPGA 120 excluding the above-mentioned defective parts, and the test of the DRAMs 160 to 180 is performed. It is executed sequentially (steps S109, S110). If a defective part is found, it is stored in the SRAM 40 or 150 or an external storage device, and then the redundant circuit provided in the DRAMs 160 to 180 is used. A rescue program for relieving a defective bit is read into the CPU 130, and the program is executed by the CPU 130 to perform bit rescue (steps S111, S112).

After that, for the non-defective product, a part of the custom logic such as the user logic is configured in a portion excluding the defective portion in the FPGA 120, and is completed as a system LSI (step S113). In this step S113, using the information indicating the defective part obtained in step S101, the data constituting the user interface so as to avoid the defective part is stored in the FPGA 120. The desired logic is constructed by writing to the connection information storage memory cell.

By the procedure described above, LSI system LSI is constructed in this way _c to be built with the desired functionality, RAM Ya by avoiding the defective portion to F PGA 1 20 within structure made test circuit Since the DRAM, CPU, and A / D conversion circuit tests are performed, highly reliable test results can be obtained without using a sophisticated external tester, and the yield is improved. In addition, since the test is performed by contact, there is no need to provide test terminals on the chip in advance, and the number of external terminals (pins) can be reduced. Furthermore, after the self-test is completed by the test circuit configured in the FPGA 120, the custom logic is configured in the FPGA 120, which reduces unnecessary circuits and suppresses unnecessary chip size increase. . Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor.

For example, in the above embodiment, the TAP is provided to input and output signals between the test circuit inside the chip and the external control device. However, the present invention is not limited to this. However, the configuration may be such that the signal of the scan path inside the chip is input / output from the coil or the antenna by the transmitting / receiving circuit directly from the test circuit without providing the TAP. When signals are transmitted and received by radio waves using the spiral conductive layer pattern as an antenna as in the above embodiment, the input / output terminals of the transmission / reception circuit are connected to one end of the pattern instead of both ends. Just do it. When signals are transmitted and received by radio waves, the conductive layer pattern serving as the antenna may be not a spiral shape but a ring shape or an S shape.

Further, in the above-mentioned embodiment, a signal is transmitted / received by utilizing a mutual induction phenomenon between a coil on a wafer or chip side and a coil on a probe force side, or transmitted / received using radio waves. However, other than that, for example, a light emitting diode and a light receiving element are combined to transmit and receive an optical signal, or a signal is transmitted via a capacitive coupling in which two electrodes face each other at an appropriate interval. It can also be configured to transmit and receive. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention can be widely used for not only a system LSI but also a semiconductor integrated circuit having a built-in test circuit, a method for inspecting the same, and a method for manufacturing the same.

Claims

The scope of the claims

1. A semiconductor integrated circuit device formed on a semiconductor chip and encapsulated in a package, in which a test circuit or a circuit capable of forming a test circuit and signals between the test circuit and an external control device are contactlessly contacted. A transmission circuit for transmitting a signal, and storage means for storing a code for identifying a chip. A conductive layer pattern for transmission connected to an output terminal of the transmission circuit is provided inside the package. A semiconductor integrated circuit device configured to output the identification code when a test result is output by a test circuit.

2. The semiconductor integrated circuit device according to claim 1, wherein the conductive layer pattern is formed on a semiconductor chip via an insulating film.

3. The semiconductor integrated circuit device according to claim 1, wherein a plurality of semiconductor chips are sealed in the package.

4. The plurality of semiconductor chips are sealed in a package while mounted on an insulating substrate, and the conductive layer pattern is formed on the insulating substrate or inside the insulating substrate. 3. The semiconductor integrated circuit device according to 1.

5. A test circuit or a circuit capable of forming a test circuit formed on the surface of the semiconductor chip and having a transmitting and receiving circuit for transmitting and receiving signals between the test circuit and an external control device in a non-contact manner A transmission / reception conductive layer pattern connected to the input / output terminal of the transmission / reception circuit via an insulating film is provided above the semiconductor chip, and the semiconductor integrated circuit is inspected in a wafer state. A probe substrate provided with a coil or antenna corresponding to the conductive layer pattern, sequentially facing the coil or antenna on the semiconductor chip, and contacting the probe substrate on the semiconductor wafer in a non-contact manner from the probe substrate. Sends test signals to semiconductor chips The test circuit in each semiconductor chip performs a test of the circuit in each chip, and the test result transmitted from the conductive layer pattern is received by the probe substrate, and the test control device checks whether the test result is normal. A method for inspecting a semiconductor integrated circuit, comprising: determining whether or not the semiconductor integrated circuit is defective.

6. The probe substrate is provided with a power supply probe corresponding to the power supply pad provided on the semiconductor chip, and is used when the probe substrate faces the coil or antenna on the semiconductor wafer. 6. The inspection method for a semiconductor integrated circuit device according to claim 5, wherein the probe is sequentially brought into contact with a power supply pad of the semiconductor chip to be supplied with power to operate the test circuit.

7. The probe substrate is provided with a power supply probe corresponding to a power supply pad common to each chip provided on the semiconductor wafer, and the probe substrate is opposed to a coil or an antenna on the semiconductor wafer. 6. The inspection method for a semiconductor integrated circuit device according to claim 5, wherein the probe is brought into contact with a power supply pad of the semiconductor chip corresponding to the power supply to supply power and operate the test circuit. .

8. The method for testing a semiconductor integrated circuit according to claim 5, wherein a driving power is supplied by an AC signal from the coil or the antenna to operate an internal test circuit.

9. A test circuit or a circuit capable of configuring a test circuit inside, a transmission circuit that transmits signals between the test circuit and an external control device in a non-contact manner, and a code for identifying a chip. A test method of a semiconductor integrated circuit having a storage means for storing a semiconductor integrated circuit in a wafer state, comprising: receiving a test result and an identification code transmitted by the transmission circuit after the test by the test circuit is completed. And determining whether each of the semiconductor integrated circuits on the wafer is normal.

10. The test result and the identification code transmitted by the transmission circuit are received, and the test result is displayed on a display device in correlation with the position of each semiconductor integrated circuit on the wafer. A method for inspecting a semiconductor integrated circuit according to claim 9.

1 1. A conductive layer pattern to be a coil or an antenna is formed on a semiconductor wafer on which a plurality of semiconductor chips each having a test circuit or a circuit capable of forming a test circuit are formed, and connected to a test control device. A probe substrate provided with a coil or antenna corresponding to the conductive layer pattern is opposed to the coil or antenna on the semiconductor wafer, and a signal for a test is transmitted from the probe substrate to a semiconductor chip on the semiconductor wafer in a non-contact manner. The test circuit in the semiconductor chip performs a test of the circuit in each chip, the test result transmitted from the conductive layer pattern is received by the probe substrate, and the test control device determines the test result. Semiconductor chips that are judged to be good products are selected as products. Method for producing a body integrated circuit device.

1 2. The conductive layer pattern is formed as a coil or antenna common to a plurality of semiconductor chips on the wafer over substantially the entire semiconductor wafer, and the conductive layer pattern is removed after testing of all the chips on the wafer is completed. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 11, wherein the method is performed.

13 3. On the semiconductor wafer, a conductive layer pattern as a coil or an antenna is formed for each semiconductor chip on the wafer, and a probe for power supply is provided on the probe substrate. When the probe is brought into contact with a power supply pad provided on a semiconductor chip corresponding to a coil or an antenna on a semiconductor wafer, power is supplied by bringing the probe into contact with the power supply and a test circuit is operated. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 11, wherein

1 4. The probe substrate is provided with a power supply probe and the semiconductor The wafer is provided with a power supply pad common to each chip and a power supply wiring for supplying power to each chip from the power supply pad. When the probe substrate is opposed to the coil or antenna on the semiconductor wafer, a conductor is provided. 13. The semiconductor according to claim 11, wherein the probe is brought into contact with a common power supply pad on a wafer to supply power to each semiconductor chip to operate a test circuit. Manufacturing method of integrated circuit device.

15 5. After the test of each semiconductor chip in the above-mentioned wafer state, the semiconductor wafer is cut into each semiconductor chip, each chip is sealed in a package, and each chip is mounted on a test pod. The probe substrate provided with the coil or antenna corresponding to the conductive layer pattern connected to the test control device is brought close to the coil or antenna on the semiconductor chip side, and the semiconductor is contactlessly contacted with the probe substrate. A test signal is transmitted to a semiconductor chip on a wafer, a test circuit in each chip is executed by a test circuit in the semiconductor chip, and a test result transmitted from the conductive layer pattern is received by a probe substrate. Then, a semiconductor chip determined as good by the test control device is selected as a product. The method of manufacturing a semiconductor integrated circuit device according to claim 1 1, 1 2, 1 3 or 1 4, characterized in that the.