JP2004260188A - Manufacturing method for semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for semiconductor integrated circuit devices, which enables to test the semiconductor integrated circuit devices without the use of an expensive tester, thus reduces the total costs needed for the test. <P>SOLUTION: According to the manufacturing method, a plurality of semiconductor chips having desired functions are formed on a semiconductor wafer. On a probing board having the size corresponding to the wafer, conductive needles are formed in the arrangement corresponding to that of the electrode pads of the semiconductor chips, and a test circuit, which is connected to the needles and operates according to a program to test the semiconductor chips, is mounted on the probing board. The probing board is superimposed on the wafer so that the needles touch the corresponding electrode pads of the semiconductor chips, and the semiconductor chips are tested with the test circuit, then a semiconductor chip judged to be nondefective is selected as a product. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a technology effective when applied to a test of a semiconductor integrated circuit device and a manufacture of the semiconductor integrated circuit device, and particularly to a technology effective when applied to a test at a wafer stage.

  As a test method of a semiconductor device such as a logic integrated circuit (hereinafter, referred to as a logic IC), a test pattern data is generated by a device called a tester and input to the logic IC, and a data signal output from the logic IC and an expected value are output. Is generally determined by comparing. There is also a BIST (Built in self test) type test technique in which a pattern generation circuit for generating a random test pattern such as a pseudo random number generation circuit is built in a semiconductor device.

  In a test method in which test pattern data is externally input to a logic IC by a tester, a scan path designed in advance to operate as a shift register by connecting flip-flops provided in a semiconductor integrated circuit device is provided. A shift scan method is used in which test data is directly input to the back of the IC from this scan path or a test result is output to reduce the amount of test patterns.

  In the BIST method, a tester function including a test pattern generation circuit, a test output compression circuit, a test result determination circuit, and the like is incorporated in a chip of a semiconductor integrated circuit device, and a test is executed by the semiconductor integrated circuit device itself. And a self-test for outputting the result.

  Incidentally, the above-described logic IC test is provided on a test board at a stage when the semiconductor chip is sealed in a package, in addition to a probe test performed by bringing a probe into contact with a pad of the semiconductor chip at a wafer stage. It has been performed in two stages of a burn-in test in which an IC is inserted into a socket. In the burn-in test, a plurality of ICs can be mounted on a test board and the test can be performed simultaneously.

  As a well-known example which describes in detail a test method for this type of semiconductor integrated circuit device, there is a publication published by Ohm Co., Ltd. on November 30, 1984, the Institute of Electronics and Communication Engineers (ed.), "LSI Handbook", page 165. , Page 166, and this document describes the configuration of various scan path systems and the like.

However, the present inventor has found that the above-described test method for a semiconductor integrated circuit device has the following problems.
That is, in the shift scan method or the BIST method, it is necessary to form a circuit (scan path) and a test circuit configuring a test function inside the semiconductor integrated circuit device to be tested, so that the chip size becomes large and the semiconductor integrated circuit becomes large. It becomes difficult to reduce the size of the circuit device.

  In addition, IC inspection is performed at the wafer stage and at the package stage, respectively, and it is difficult to apply probes to the electrode pads of all chips on the wafer at the same time in a test using a prober at the wafer stage. Although a method of sequentially measuring individual semiconductor chips is employed, the test time becomes extremely long. In addition, when testing semiconductor chips one by one, there is a problem in that the cost efficiency does not increase because the use efficiency of an expensive tester deteriorates, and the TAT (turn around time) is not shortened. In addition, the speed of operation and the increase in the number of pins associated with the miniaturization of semiconductor integrated circuit devices are rapidly progressing, and the usefulness of expensive testers is rapidly reduced. But it has increased further.

An object of the present invention is to provide a test technique that can test a semiconductor chip in a short time without using an expensive tester.
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device capable of performing a test of the semiconductor integrated circuit device without using an expensive tester, thereby reducing the total cost required for the test. is there.

Another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device in which a high-precision test can be performed in a test at a wafer stage, thereby shortening a time required from the start of design to completion of the semiconductor integrated circuit device. Is to provide.
Another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device capable of performing a test efficiently while suppressing an increase in overhead of a test circuit in a semiconductor chip.

Still another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device which can perform a test of a semiconductor chip without using an expensive tester and which does not hinder the manufactured semiconductor integrated circuit device. Is to provide.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
That is, the test system of the present invention includes a probe card having conductive needles formed in accordance with the arrangement of electrode pads of a semiconductor chip formed on a wafer, and a probe card mounted on the probe card and based on a test program. And a control device for rewriting a test program in the test circuit and storing a test result output from the test circuit.

  In addition, a method of manufacturing a semiconductor integrated circuit device according to the present invention includes forming a plurality of semiconductor chips having desired functions on a semiconductor wafer, and having a size corresponding to the wafer and forming electrode pads of the semiconductor chips. A test circuit for testing the semiconductor chip connected to the needle and operating according to a program is mounted on a probe substrate formed with conductive needles in accordance with the arrangement, and the probe substrate is connected to the semiconductor chip by the needle. And the semiconductor chip is tested by the test circuit, and a semiconductor chip determined as a non-defective product is selected as a product.

  According to the above-described means, the test of the semiconductor chip on the wafer can be performed by the test circuit mounted on the probe substrate, so that the test can be performed without using an expensive tester, thereby reducing the total cost required for the test. Can be reduced. In addition, since a highly accurate test can be performed in the test at the wafer stage, it is not necessary to perform the test again after packaging, or the test after packaging can be simplified. Thus, the time required from the start of the design to the completion of the semiconductor integrated circuit device can be reduced.

  Preferably, a programmable logic IC (FPGA) capable of configuring an arbitrary logic is provided on the probe substrate in correspondence with the semiconductor chip, and the programmable logic IC is configured based on design data described in a hardware description language. The test circuit is configured in an IC, and the semiconductor chip is tested by the test circuit. As a result, the test circuit can be efficiently configured, and the test circuit suitable for another semiconductor chip can be reconfigured by rewriting the programmable logic IC, so that the probe substrate can be reused, and the total cost can be further reduced. Can be lowered.

  More preferably, the test circuit is a test signal generation circuit (ALPG) configured to generate a test signal supplied to a semiconductor chip to be tested according to a predetermined algorithm. As a result, a test circuit optimal for the semiconductor chip to be tested can be formed, and the test can be performed efficiently while suppressing an increase in the overhead of the test circuit.

  According to a second method of manufacturing a semiconductor integrated circuit device according to the present invention, a test circuit module that operates according to a program and tests the semiconductor chip is formed together with the semiconductor chip on a wafer on which the designed semiconductor chip is formed, and A power supply voltage is externally supplied to the test circuit module, the semiconductor chips on the same wafer are tested by the test circuit module, and a semiconductor chip determined as a non-defective product is selected as a product.

  According to the above-described means, the test of the semiconductor chip can be performed at the wafer stage by the test circuit module formed on the wafer, so that the test can be performed without using an expensive tester, and the test at the wafer stage can be performed. Since a highly accurate test can be performed, the time required from the start of the design to the completion of the semiconductor integrated circuit device can be reduced.

  Preferably, the connection between the test circuit module and the semiconductor chip to be tested is made by a wiring formed in a scribe area of a wafer or a wiring layer dedicated to the test. Further, the test wiring for connecting the test circuit module to the semiconductor chip to be tested is formed so as to meander in the scribe area of the wafer. This makes it possible to simplify the structure of the probe board, and to cut the test wiring reliably during dicing, and to minimize the residual wiring after cutting, thereby avoiding the adverse effects of the residual wiring. You.

The effects obtained by typical aspects of the invention disclosed by the present application will be briefly described as follows.
That is, according to the present invention, a test of a developed semiconductor chip can be performed without using an expensive tester, whereby the total cost required for the test can be significantly reduced. Further, according to the present invention, it is possible to perform a test at the wafer stage, and by performing this wafer test in an aging apparatus, the test after packaging can be simplified or omitted, and the test time can be greatly reduced. Can be increased. Further, the time required from the start of the design to the completion of the semiconductor integrated circuit device can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is an explanatory diagram showing a first embodiment of a test system to which the present invention is applied, and FIG. 2 is an explanatory diagram showing an example of a mounting structure of a test IC in the test system of the first embodiment.

  In the present embodiment, the test system 1 includes a probe card 2 having a size corresponding to the semiconductor wafer W and a control device 3 for controlling the probe card 2, as shown in FIG. In the probe card 2, a test IC 5 is provided on the insulating substrate 4 corresponding to each semiconductor chip CH on the semiconductor wafer W, and the test IC and each semiconductor chip CH are mounted on the lower surface of the insulating substrate 4. A needle 6 for electrical connection is provided, and the test IC 5 is configured to test each semiconductor chip CH. The control device 3 controls writing of data to the test IC 5 and control of the test operation.

  The insulating substrate 4 has the same size and shape as the semiconductor wafer W, and is provided on the surface opposite to the surface on which the test IC is provided with the electrode pads of all the semiconductor chips CH formed on the semiconductor wafer W. Conductive needles 6 are arranged according to the arrangement. The needle 6 is formed on the entire surface of the insulating substrate 4 by a technique such as a microprobe. Wirings and through holes are formed on the surface of the insulating substrate 4 and inside the substrate for connecting the terminals of the test IC 5 to the needles corresponding to the terminals by the printed wiring technology.

  On the surface of the insulating substrate 4, test ICs 5 are mounted corresponding to the individual semiconductor chips CH on the wafer W. The test IC 5 is composed of an FPGA (Field Programmable Gate Array) or the like. FPGAs having a 130K gate scale are currently available on the market. However, if it is not sufficient to configure a test circuit, as shown in FIG. 2, a plurality of (three in the figure) FPGAs 7 to 7 are used. It is preferable to use a configuration in which the components 9 are stacked and mounted.

  In this embodiment, the test IC 5 generates a predetermined test pattern according to a predetermined algorithm including a microprogram written by the control device 3 based on tester construction data described in HDL (Hardware Description Language). Then, the semiconductor chip CH is configured to make a test determination. The test IC 5 may be a semiconductor device such as a microcomputer that can understand the HDL for the tester instead of the FPGA. In this case, the microcomputer mounted on the probe card 2 operates so as to supply a predetermined test pattern to the corresponding semiconductor chip CH by generating an output signal according to a microprogram given from the control device 3.

  When the test IC 5 is composed of a plurality of FPGAs, any one of the FPGAs 7 to 9 may be an analog FPGA. As a result, analysis tests such as DC measurement and analog waveform characteristic analysis can be performed. For example, even if the semiconductor integrated circuit device to be tested is a mixed digital / analog type semiconductor integrated circuit device, the test is efficiently performed. be able to.

Next, the relationship between the test circuit constructed in the test IC 5 and the HDL description for constructing the test circuit will be described.
FIG. 3 shows a conceptual diagram of a general tester. As shown in FIG. 3, the tester T includes a power supply unit 12 that supplies a power supply voltage to the semiconductor integrated circuit device TIC to be tested, a driver 14 that inputs a test signal to an input pin of the semiconductor integrated circuit device TIC, A comparator 15 for comparing a signal output from an output pin of the integrated circuit device TIC with an expected value signal, a signal generator (a so-called test pattern) input to the semiconductor integrated circuit device TIC, and a pattern generator 10 for generating an expected value signal; The semiconductor integrated circuit device TIC comprises a timing generator 11 for generating an application timing of a signal to be input to the semiconductor integrated circuit device TIC, and a CPU 16 as a controller for controlling these circuits.

  The CPU 16 reads a test program from an external storage device, interprets the test program by an OS (operating system), determines the generation of a test signal (a so-called test pattern), and performs a predetermined test. Have been. The tester T includes a DC test circuit 13 for performing a DC test such as a voltage level detection of an output pin of the semiconductor integrated circuit device TIC and an analog signal generating an analog waveform applied to an analog input terminal of the semiconductor integrated circuit device TIC. There may be provided a waveform generation unit, a waveform observation unit for observing the output waveform of the analog output terminal of the semiconductor integrated circuit device TIC, and the like. In FIG. 3, the illustration of the analog waveform generation unit and the waveform observation unit is omitted.

  By the way, conventionally, the function of each of the blocks 10 to 16 of the tester T as shown in FIG. 3 and the function of the semiconductor integrated circuit device TIC to be tested are described by HDL, and the HDL description is written by a hardware emulator. A tool called a virtual tester for simulating and verifying is known.

  The HDL description sentence input to the hardware emulator can be generated by, for example, a function entry tool. The function entry tool is a support tool that supports creation of an HDL description sentence, and includes a function of each block of the tester T represented by a logical transition diagram, a flowchart, and the like on a screen of a computer display device, and a half to be tested. The function of the integrated circuit device TIC is converted into an HDL description. As such a function entry tool, for example, there is “Visual Test” provided by an EDA (Engineering Design Automation) vendor such as AT Service Co., Ltd.

  The virtual tester logically synthesizes the tester and the semiconductor integrated circuit device from the HDL description generated by the above function entry tool, mounts the tester on a hardware emulator, and performs verification by using a hardware emulator. It is used as a tool that enables debugging of test programs in a short time. The inventors of the present invention have taken a step forward from the technology of the virtual tester, and have conceived that it is possible to construct a tester in an FPGA based on the description of the HDL and perform a test of a semiconductor integrated circuit device in a wafer state using the tester. With this, the present invention has been developed.

  In the present embodiment, when constructing a tester in the FPGA from the HDL description, the tester is configured by an ALPG (Algorithmic Memory Pattern Generator) that generates a test pattern according to a known algorithm. According to the verification by the present inventors, it has been found that an ALPG can be constructed with about several hundred K gates in terms of the number of logic gates. Therefore, the ALPG can be constructed from several FPGAs as shown in FIG. It is fully possible to build in a semiconductor device.

  Here, a specific procedure for constructing the ALPG in the FPGA will be briefly described. In order to construct an ALPG in an FPGA, it is necessary to first create data for constructing the ALPG.

  In the creation of the ALPG construction data, first, the logic configuration of the semiconductor integrated circuit device to be tested and the test program used by the virtual tester are analyzed to generate a test pattern to be input to the semiconductor integrated circuit device to be tested. The format, that is, the schematic configuration (architecture) of the ALPG to be extracted and constructed is determined. For example, if the semiconductor device to be tested is a memory, it depends on the semiconductor integrated circuit device to be tested, such as an ALPG that generates an address and data, or a logic LSI, such as an ALPG that generates input data and expected value data. The algorithm and the form of the ALPG that embodies it will be determined.

  Existing testers can generally carry out as many different test items as necessary so that a wide variety of newly developed semiconductor devices can be tested with a single tester, and can also test semiconductor devices to be tested. It is configured to support a wide range of operating frequencies and the expected maximum number of pins in terms of device performance and pin count, etc., and is provided as a highly versatile device. ing. However, as in the present embodiment, the ALPG (test circuit) for only the semiconductor integrated circuit device to be tested requires a small-scale configuration, and can be built in several FPGAs.

  Next, the ALPG having the determined architecture is described in HDL. The description of the ALPG in the HDL may be manually performed by a testing engineer, but is called, for example, the above-mentioned “Visual Test”. It can be done efficiently by using the function entry tool.

  After that, an ALPG is constructed in the FPGA using the data described in the HDL. As an FPGA that can configure arbitrary logic, for example, a one-chip LSI with a 130K gate scale (model number EPF10K130E) is provided by Altera, and an ALPG can be constructed by using it. As a support tool for constructing logic in the FPGA from the HDL description, for example, "MAX + plusII" provided by Altera is available, which can be automatically performed by a computer using this.

Next, a wafer test technique using the probe card 2 in the test system 1 of FIG. 1 will be described.
In this embodiment, the wafer test is performed at the time of wafer burn-in. First, the needle 6 of the probe card 2 is brought into contact with the electrode pad formed on each semiconductor chip CH on the semiconductor wafer W mounted on the wafer stage WS having the temperature control function, and pressure is applied from above the probe card 2. In addition, the probe card 2 is pressed against the wafer W to electrically connect each test IC 5 to each semiconductor chip CH.

  When the semiconductor chip CH and the test IC 5 are electrically connected to each other, the control device 3 starts supplying the power supply voltage. The test IC 5 supplied with the power supply voltage operates according to the microprogram written by the control device 3 based on the tester construction data described in HDL, and generates a test pattern for the corresponding semiconductor wafer W in a predetermined order. To apply. At this time, all the semiconductor chips CH are simultaneously tested by the plurality of test ICs 5 provided in the probe card 2, and the results are sent to the control device 3 and stored in the memory in the control device.

  The control device 3 creates a pass / fail map of the semiconductor wafer based on the input test results, and provides data for removing defective products and classifying in a subsequent process (wafer dicing process).

  As described above, in the test system of the present embodiment, all the semiconductor chips CH formed on the semiconductor wafer W at the time of wafer burn-in are collectively collected by the plurality of test ICs 5 provided on the probe card 2. Since testing can be performed, testing time can be greatly reduced, and product development time can be shortened. This is true even when the test IC 5 is replaced with a microcomputer device.

  Further, since the FPGA is programmable, a necessary tester function can be rewritten at any time by using the FPGA as the test IC 5, so that a test method can be easily changed or added. The same can be achieved by replacing the control program stored in the internal RAM or EEPROM even when the test IC 5 is replaced with a microcomputer device.

  Furthermore, even when the test of the entire semiconductor chip CH is complicated, it is possible to divide the semiconductor chip CH into a plurality of blocks, rebuild the optimal ALPG for each block in the FPGA, and perform the test sequentially. It is. As a result, a test can be performed even if the logic scale of the FPGA used is small, and the feasibility of the test IC 5 corresponding to each semiconductor chip CH on the wafer is increased.

  In addition, by performing the test using the virtual tester together, the test program evaluation and the logic function can be verified by simulation using a hardware emulator or the like before the sample of the semiconductor integrated circuit device to be tested is prototyped. Simultaneous testing is possible, and the data used in the virtual tester can be used when constructing a test circuit (ALPG) in an FPGA, thereby enabling the test system in FIG. 1 to be configured efficiently. It becomes.

  Further, as the test IC 5, a self-verifying FPGA having a self-test function and a self-healing function as disclosed in a patent application (Japanese Patent Application No. 11-122229) separately proposed by the present inventors is used. It may be used. As a result, the test IC 5 has a structure capable of self-test and self-repair, and can have a structure resistant to defective exposure.

  FIG. 4 is an explanatory view showing a second embodiment of the test system to which the present invention is applied, and FIG. 5 is a diagram showing a relationship between a needle formed on a probe card and a test IC in the test system of the second embodiment. FIG. 6 is a diagram showing an example of forming a wafer piece constituting a probe card in the test system according to the second embodiment.

  As shown in FIG. 4, the test system 1 according to the second embodiment includes a probe card 2a and a control device 3, as in the first embodiment. The probe card 2a includes a fixed frame 18 and a plurality of wafer pieces 17 on which a test (test circuit) IC is formed.

  Also in this embodiment, as shown in FIG. 5, test ICs 5a each composed of an FPGA or a microcomputer device are formed directly on the wafer piece 17 corresponding to each semiconductor chip CH to be tested. . On the surface of the wafer piece 17 in the vicinity of the test IC 5a, a needle 6a that is in contact with the electrode pad of the semiconductor chip CH is provided. The needle 6a is also formed directly on the wafer 17 by using the processing technology of the semiconductor manufacturing process. Have been.

  The needle 6a is formed, for example, by a technique called silicon contact. The silicon contact is a structure formed using a silicon process using a nanotechnology processing technology. The needle 6a formed by the silicon contact has a fine structure, and the contact property with the electrode pad of the semiconductor chip CH to be tested is improved, so that the contact load can be significantly reduced, and the wafer test can be performed more easily and It can be done reliably.

  As shown in FIG. 6, the wafer piece 17 is obtained by cutting the semiconductor wafer W1 on which the test IC 5a (including the needle 6a) is formed into a rectangular shape having a predetermined size. As shown in FIG. 4, a configuration is adopted in which the fixing frame 18 is bonded and fixed to a fixing frame 18 made of aluminum or the like.

  The probe card 2a is superimposed on the wafer W such that the needle 6a is brought into contact with the electrode pads of each semiconductor chip CH on the semiconductor wafer W mounted on the wafer stage WS, so that the semiconductor chip CH and the test IC 5a Are electrically connected to perform a wafer test.

  In addition, by mounting a rewritable function on the test IC 5a, flexible addition and deletion of test items becomes possible. Concerning the test pattern, a test circuit is formed so as to form a test pattern for each pin, and by using pattern compression, a control program to be written in the test IC 5a is shortened and rewriting is facilitated. By doing so, when testing using the probe card 2a of FIG. 4, it is possible to deal with a plurality of semiconductor chips by rewriting a part of the control program without creating a plurality of test ICs and control programs. And its application range is expanded.

  Further, according to the second embodiment, the probe card 2a is constituted by the plurality of wafer pieces 17, so that the wafer piece 17 of a high-performance portion is cut out from the plurality of semiconductor wafers W1 to constitute the probe card 2a. Therefore, the reliability can be greatly improved. Further, even when testing a large-diameter wafer, it is possible to flexibly cope with the problem by increasing the number of wafer pieces 17, and the wafer pieces 17 constituting the test IC are formed by the semiconductor integrated circuit device to be tested. It can be formed on a wafer having a smaller diameter than the wafer W to be formed.

  Furthermore, in the above description, the probe card 2a is configured by combining a plurality of wafer pieces 17, but for example, as shown in FIGS. 7, 8A and 8B, the probe card 2a A plurality of test ICs 5a corresponding to the individual semiconductor chips CH of the semiconductor wafer W to be tested may be formed on a separate semiconductor wafer W1, and the semiconductor wafer W1 itself may be used as the probe card 2a.

  In this case, the needle 6b is formed at a position corresponding to the electrode pad of each semiconductor chip CH to be tested on the semiconductor wafer W1 on which the test IC 5a is formed. The needle 6b can be constituted by, for example, a bump B as shown in FIG. At the time of the wafer test, as shown in FIG. 8A, the main surface of the semiconductor wafer W and the main surface of the semiconductor wafer W1 which is the probe card 4b are overlapped with each other, so that the needle 6b made of the bump B and the semiconductor chip CH Contact with the electrode pad. Thereby, use durability can be improved.

  Also in the second embodiment, if a self-verifying FPGA having a self-testing function, a self-healing function, and the like is used as the test IC 5a, a structure resistant to defective exposure can be obtained.

  If there is an unrepairable test IC 5a in the probe card 2a, the fact that the test IC 5a cannot be repaired is recorded in the test IC 5a, and the test IC is replaced with a test IC closest to the test IC 5a. Is automatically assigned, it is possible to realize a test system capable of performing an inspection without being affected by a yield or a failure of the test IC 5a.

  FIG. 9A is a diagram showing an example of the arrangement of test ICs formed on a semiconductor wafer by applying the third embodiment of the present invention, and FIG. 9B is used in the third embodiment. FIG. 10 is an explanatory diagram of a probing module, and FIG. 10 is an explanatory diagram of a test measurement range in a tester according to the third embodiment.

  In the present embodiment, the test system 1 includes a test IC 5b formed on a semiconductor wafer, a probing module 19, and a power supply device 3a. As shown in FIG. 9A, the test IC 5b has a chip on which the test IC (test circuit) 5b is formed on the same semiconductor wafer W as the semiconductor wafer on which the semiconductor chip CH serving as a product is formed. They are arranged at appropriate positions at predetermined intervals.

  The test IC 5b formed on the same wafer in this way tests the semiconductor chip CH around the test IC 5b. For example, as shown in FIG. 10, eight semiconductor chips around the test IC 5b, or twenty-four semiconductor chips CH including the eight semiconductor chips and the sixteen semiconductor chips surrounding them are combined at one time. Configured to test.

  In the present embodiment, the connection between the semiconductor chip CH to be tested and the test IC 5b is performed by the probing module 19 shown in FIG. 9B. The probing module 19 is provided with wiring, and a needle is provided on the surface. Then, the needle is brought into contact with the electrode pad of the semiconductor chip CH and the electrode pad of the test IC 5b formed on the semiconductor wafer, and the individual semiconductor chip CH and the test IC 5b are connected via the wiring of the probing module 19.

  In addition, a wafer test is started by supplying a power supply voltage from the power supply device 3a to the test IC 5b on the wafer W and the semiconductor chips to be tested in the vicinity thereof via the probing module 19. When a power supply voltage is applied from the power supply device 3a, a test signal is output to each of the semiconductor chips CH measured from the test IC 5b, and the number of the semiconductor chips CH to be tested is measured through a Kelvin circuit. A voltage drop or the like due to the arrangement of the analog circuit is stored as information of each semiconductor chip CH. Based on this, the test items are automatically and sequentially executed.

  As a result of execution of this test, the signal output from each semiconductor chip CH is supplied to the test IC 5b, and is compared with the data stored in the memory inside the test IC 5b or the expected value data generated by the test IC 5 to determine whether or not the signal is good. It is determined whether the product is defective. In the case of a defective product, the test IC 5b is processed so that the semiconductor chip CH of the defective product can be distinguished from the external appearance.

  Examples of the processing for discrimination on the external appearance include cutting by passing an overcurrent through a part of the aluminum wiring or polysilicon wiring in the defective semiconductor chip CH or flowing a current through a zener zap. It is effective to use the high heat generated by the heat treatment to change the color of the heat-modified color former applied beforehand to the surroundings. In this manner, the test is completed only by applying the power supply voltage to the chips on the wafer by the probing module, and as a result, the semiconductor chip CH determined to be defective can be recognized as a defective in appearance. Can be easily distinguished.

  As described above, in the third embodiment, by forming the test IC 5b on the semiconductor wafer W, the configuration on the probe card side can be simplified, and the cost and space of the test apparatus can be significantly reduced. . In addition, since the test IC 5b is manufactured by the same process as that of the semiconductor chip CH as a product, the circuit scale, that is, the area can be reduced, and the overhead of the semiconductor wafer W can be greatly reduced. That is, the conventional tester is configured using a semiconductor integrated circuit device manufactured by a process technology of one generation or two generations earlier, which has a lower integration degree than the semiconductor integrated circuit device to be tested, so that the circuit scale is large. Although this is inevitable, the application of the present embodiment allows the test IC 5b to be formed by the latest process technology, so that the circuit scale of the test apparatus can be significantly reduced.

  Further, in the conventional test apparatus, a long signal wiring (cable) for connecting the probe card and the tester main body was required. In the present embodiment, such a signal wiring is not required, and the test IC 5b and the test IC 5b are connected. Since the distance from the semiconductor chip to be used is short, wiring stray capacitance is minimized, and high-speed clock actual operation tests can be performed in a stable manner. Can be demonstrated even more.

  Further, when the present embodiment is applied, each chip can be tested while performing aging (also called burn-in) in the state of the semiconductor wafer W, so that the period from the start of development of the semiconductor integrated circuit device to shipment is greatly reduced. Can be shortened.

  Hereinafter, the usefulness of the present embodiment will be described in terms of the process from the start of development of a semiconductor integrated circuit device to shipment when the test method of the present embodiment is applied, and the development of a semiconductor integrated circuit device when a conventional tester is used. A description will be given in comparison with the process from to shipping. FIG. 18 shows a process from the start of development of a semiconductor integrated circuit device to shipment when a conventional tester is used. FIG. 19 shows a process from the start of development to shipment of a semiconductor integrated circuit device when the test method of the present embodiment is applied.

  As shown in FIG. 18, in developing a conventional semiconductor integrated circuit device, first, a logic function of a semiconductor integrated circuit to be developed is designed (step S11). This logic function design is generally performed using HDL. Note that since the EDA vendor provides a support tool (program) for automatically creating an HDL description from a state transition diagram or a flowchart, the HDL description can be efficiently performed. The design data described in the HDL is subjected to a virtual test for verifying whether the operation is appropriate by a verification program for generating a test pattern called a test vector. When a defect is found by the virtual test, the HDL description is corrected.

  Next, a circuit is designed at the logic gate level based on the data designed in step S11 (step S12). Specifically, cells such as logic gates and flip-flops that constitute a circuit having a desired function are designed. Then, based on the design data, logic synthesis is performed to create design data in which connection information between each logic gate and cell is described in the form of a netlist (step S13). When a desired logic function is configured on an LSI for which a logic gate circuit has already been designed, such as a gate array, the circuit design in step S12 can be omitted. Also in this case, a program called a logic synthesis tool for converting design data described in HDL into design data at a logic gate level and synthesizing the design data is provided by the EDA vendor. . The generated logic gate level design data is verified again by a test vector (virtual tester). If a defect is found by the virtual tester, the design data at the logic gate level is corrected.

  Next, based on the logic gate level design data described in the netlist format, element level layout data is generated by a program called an automatic layout tool (step S14). Such automatic layout tools are also provided by several EDA vendors. Then, the layout of the chips on the wafer is determined (step S15). Then, mask pattern data is generated by artwork based on the determined layout data, and a mask is created based on the data (step S16).

  After that, a semiconductor integrated circuit is formed by performing processing such as diffusion processing and wiring pattern formation on the semiconductor wafer in the previous process (step S17). Then, a probe test is performed in which the probe at the tip of the cable extended from the tester is brought into contact with the electrode pad of each chip on the wafer, and a test pattern is input and the output is observed (step S18). When the probe test is completed, dicing for dividing the wafer into chips is performed (step S19).

  The divided chips are sealed in a package with a sealing material such as a resin (Step S20). At this time, the chips determined to be defective in the probe test in step S18 are removed in advance. Then, the semiconductor integrated circuit device in a package state is subjected to a high temperature by an aging (or pan-in) device, and is again subjected to a test by a tester in the package state (steps S21 and S22). The test content at this time is almost the same as the content of the probe test performed in step S18. Then, those which are determined to be defective in this test are marked on the package surface (step S23), removed in the sorting step, and only non-defective products are packed and shipped (step S24).

  FIG. 19 shows a process from the start of development of a semiconductor integrated circuit device to shipment when the test method of the embodiment is applied, that is, a procedure of a method of manufacturing a semiconductor integrated circuit device according to the present invention. As is apparent from comparison with FIG. 18, steps S11 to S14 are the same as those in the related art.

  However, in the process of the present invention, step design is performed in parallel with the function design (step S11), circuit design (step S12), logic synthesis (step S13), and automatic layout (step S14) of the semiconductor integrated circuit device to be developed. Using the data (tester IP) used in the virtual test performed in S11 and step S12, the function necessary for testing the semiconductor integrated circuit device under development is determined, that is, the tester function is optimized (step S31). .

  Then, as described in the above embodiment, this tester function is described in HDL (step S32). Then, similarly to the semiconductor integrated circuit device to be developed, the logic synthesis of the test circuit (ALPG) is performed from the HDL description using a logic synthesis tool to convert the data into logic gate level design data (step S33). Then, based on the generated logic gate level design data, the automatic layout tool generates element level layout data (step S34).

  In this manner, when the layout data of the test circuit is generated, in the present invention, in order to form this test circuit as a module on a wafer, the semiconductor chip developed on the wafer and the test circuit module are arranged in a predetermined arrangement. Is determined (step S15 '). At this time, the test circuit modules are arranged not in one-to-one but in a ratio such as one-to-eight or one-to-four, as will be described later.

  Then, based on the determined layout data, mask pattern data is generated by the artwork including the test circuit module, and a mask is created based on the data (step S16 ').

  After that, a process such as a diffusion process or a wiring pattern formation is performed on the semiconductor wafer in the previous process to form a semiconductor integrated circuit and a test circuit module (Step S17). Then, in the process of the present invention, a probe card or a probing module for supplying power and connecting the test circuit module and the semiconductor chip is brought into contact with the test circuit module on the wafer and the electrode pads of the semiconductor chip, and the process is performed on the wafer. Then, the test of the semiconductor chip by the test circuit module is automatically performed (step S18 '). Moreover, in this embodiment, the wafer test is performed in an aging device.

  When the test is completed, dicing is performed to divide the wafer into chips (step S19). Thereafter, the divided chips are sealed in a package with a sealing material such as resin (Step S20). At this time, the chip determined to be defective in the probe test in step S18 is removed. Then, the test of the packaged semiconductor integrated circuit device is performed by the tester (step S22 '). The test at this time is only a simple test such as the DC test not performed in step S18 '. Then, those which are determined to be defective in this test are marked on the package surface (step S23), removed in the sorting step, and only non-defective products are packed and shipped (step S24). When the test circuit module on the wafer also has a DC test function, the test by the tester in step S22 'can be omitted.

  As described above, in the process of the present invention, since the tests conventionally performed in the wafer state and the package state can be completed only once, the development period from functional design to product shipment can be shortened. . In addition, when a defect is found in the package test and the design needs to be changed, the TAT becomes very long because the wafer test and the package test need to be performed again in the conventional process. In the above process, even if there is a design change, only a wafer test is required for the test, so that the TAT is greatly reduced.

  Further, in the third embodiment, the test circuit module 5b is formed on the semiconductor wafer W on which the semiconductor chip to be tested is formed, and the test circuit module 5b and the semiconductor chip CH are connected by the probing module 19. However, for example, a test wiring for connecting the test circuit module 5b and the semiconductor chip CH may be formed in the scribe area SA between the chips CH on the semiconductor wafer W as shown in FIG.

  By the way, when the test wiring is formed in the scribe area SA, when dicing the semiconductor chips CH by dicing along the scribe area SA, the semiconductor chips CH are extended far outside the center line of the scribe area SA. The remaining wiring may remain without being cut. If there is any remaining wiring that is not cut in this way, it plays the role of an antenna and picks up electromagnetic noise, and it is expected that noise will easily enter the internal circuit from the electrode pad of the chip.

  FIGS. 12 and 13 show a devised configuration for reducing the influence of the residual wiring in the scribe area SA. 12 shows an example of a layout that is effective when applied to a test wiring H formed by a single-layer wiring, and FIG. 13 is an effective layout that is applied to a test wiring H that is formed by a two-layer wiring. 2 shows a layout example.

  As shown in FIGS. 12 and 13, the test wiring H is arranged so as to meander over the scribe line SL, which is the center line of the scribe area SA, many times. As a result, the test wiring H is always cut when dicing the semiconductor chip CH, and the length lc of the residual wiring extending from the electrode pad PAD of the chip to the scribe area SA is equal to the distance from the center line of the scribe area SA. And the cut is made to remain in the shortest length.

  FIGS. 20 and 21 show a relatively efficient wiring connection method when eight semiconductor chips CH around the test circuit module are tested by one test circuit module. FIG. 20 shows a case where the test wiring H is formed by a single-layer wiring. In FIG. 20, reference numeral 5b denotes a test circuit module, and CH1, CH2, and CH3 indicate three out of eight surrounding semiconductor chips.

  FIG. 20 shows that each of the four sides of the test circuit module 5b is divided into two, and the half-sides X2 and Y1 at the upper right corner include all the electrode pads provided around the right half of the adjacent chip CH1 and the chip CH2. And terminals connected to all the electrode pads provided on the left half of the periphery of the chip CH3 are provided by using the scribe areas SA1, SA2, SA3, and SA4. Means to form test wirings for connecting these terminals to the selected electrode pads of the chips CH1, CH2, CH3. The terminals provided on the four sides of the test circuit module 5b other than the terminals receiving the power supply voltage need not be electrode pads, and one ends of test wirings formed in the scribe areas SA1, SA2, SA3, and SA4 are connected. Virtual terminals. Therefore, terminals can be arranged more densely on the four sides of the test circuit module 5b than the semiconductor chip to be tested.

  Similarly, five chips (not shown) other than the chips CH1, CH2, and CH3 are respectively adjacent to the half sides Y2, X3; X4, Y3; Y4, and X1 of the three corners of the test circuit module 5b. Terminals to be connected to the electrode pads of the same part of one chip as described above are provided, and the connection is made by the test wiring formed in the scribe area. This makes it possible to connect one test circuit module to eight semiconductor chips around it using a relatively short length of test wiring.

  By the way, if the connection method as shown in FIG. 20 is adopted, the test wiring becomes densest at the diagonal line DL connecting the opposing corners of the chips CH1 and CH3. Therefore, it is calculated whether or not all the wirings to pass therethrough are within the width of the diagonal line DL at an allowable pitch. Just choose.

  In FIG. 21, 5b is a test circuit module, CH1 to CH8 are eight surrounding semiconductor chips, H1 to H4 are test wirings for connecting the test circuit module 5b and the semiconductor chips CH1 to CH8, and A to D are This represents an electrode pad. It is to be noted that the electrode pads with the same reference numerals are connected to the same test wiring. In FIG. 21, for the sake of illustration, the test wirings H1 to H4 are shown to extend along the periphery of each chip, but are arranged in the scribe area SA in an actual layout.

  In FIG. 21, the test wirings arranged in the scribe area SA are each composed of four fork-shaped wiring bodies H1, H3 each having three tooth portions and a connecting portion orthogonal to them and connecting them at one end. H2, H3, and H4. These four fork-shaped wiring bodies H1, H2, H3, and H4 have their respective tooth portions entering the scribe area SA of the chip matrix from four directions different from each other by 90 °. Are arranged so as to mesh with each other, and each of the chips CH1 to CH8 is arranged such that four sides are surrounded by any tooth portion of these forked wiring bodies H1, H2, H3, H4. The chips CH1 to CH8 and the electrode pads A, B, C, D of the test circuit module 5b are connected to the fork-shaped wiring members H1, H2, H3, H4 arranged along the sides thereof. Connected to.

  In the four forked wiring bodies H1, H2, H3, and H4, those having respective tooth portions in parallel are formed by wiring of the same layer, and those having orthogonal portions are formed by wiring of different layers. Specifically, the forked wiring bodies H1 and H3 are formed by first-layer wirings, and H2 and H4 are formed by second-layer wirings. As a result, the portions that cross each other are electrically insulated.

  As described above, by connecting the test circuit module 5b and the eight semiconductor chips CH1 to CH8 around the test circuit module 5b by the fork-shaped wiring bodies H1, H2, H3, H4, the number of wirings can be reduced, and the number of wirings can be relatively reduced. Connection using a narrow scribe line becomes possible. However, since the connection method in FIG. 21 is a bus method and a plurality of chips are connected to one wiring, a chip selection signal is sent from the test circuit module 5b to each of the semiconductor chips CH1 to CH8. In a certain time zone, it is necessary to perform control such that one of the chips is connected to the test circuit module 5b and the tests are sequentially performed in a time division manner.

  FIG. 22 shows an embodiment in which one test circuit module 5b tests 24 semiconductor chips CH1 to CH24 around it, and connects the test circuit module 5b and the surrounding semiconductor chips CH1 to CH24. In this case, a wiring connection method considered to be the most efficient will be described. This method is merely an increase in the scale of the method in FIG. 21, and the basic configuration is the same. That is, similarly to the method of FIG. 21, the connection between the test circuit module 5b and the 24 semiconductor chips CH1 to CH24 around the test circuit module 5b is performed by four forked wiring bodies H1, H2, H3, and H4. The difference from the method of FIG. 21 is that each fork-shaped wiring body H1, H2, H3, H4 is provided with five teeth instead of three. Also in this embodiment, the chips CH1 to CH24 and the electrode pads A, B, C, D of the test circuit module 5b are connected to the fork-like wiring bodies H1, H2, H3, H4 arranged along the sides. It is connected to the wiring of the tooth part.

  The layout of the test circuit module and the semiconductor chips to be tested on the wafer is not limited to the examples shown in FIGS. 10 and 11. For example, as shown in FIG. Test circuit modules 5c to 5e are collectively arranged, a test wiring is extended from each chip CH therefrom, or the test circuit modules 5c to 5e on the semiconductor wafer W and the semiconductor chips CH May be connected and tested.

  The test circuit modules 5c to 5e may have the same functions, but may have dedicated functions, for example, analog test modules or digital test modules. is there. By providing a plurality of test ICs 5c to 5e having a dedicated test function on a wafer in this manner, a more accurate test can be performed. Further, since a test function dedicated to high frequency can be taken in, a test with a large degree of freedom can be performed.

  In addition, the test circuit module 5f may be divided into four parts, each of which may be arranged at four peripheral parts of the semiconductor chip CH as shown in FIG. For example, a test circuit module 5f (area shaded) for testing the semiconductor chip CH1 is provided at a peripheral portion of the central semiconductor chip CH1 shown in FIG. 15 and another test circuit module located near the peripheral portion of the semiconductor chip CH1. A test circuit module 5f (white area) for testing the semiconductor chip CH is arranged. In this case, it is difficult to provide the electrode pads in the scribe area having a relatively small width. Therefore, the electrode pads are formed in the empty area of the peripheral portion of the semiconductor wafer W, and the wiring or the wiring formed in the scribe area from the electrode pads is formed. An insulating synthetic resin film such as a PIQ (polyimide insulating film) is formed on the surface of the final protective film above the semiconductor chip, and power is supplied to each test circuit module 5f via wiring formed thereon. It is good to configure.

  In such a configuration, the test circuit modules 5f can be evenly arranged on each semiconductor chip CH, and the optimum position for each test function, that is, the side closest to the electrode pad to which the test signal is input is provided. It is possible to arrange a test function unit for generating a test signal. In addition, since the test circuit module 5f is cut by dicing after the test is completed, the test circuit module 5f has no electrical influence on the semiconductor chip CH.

  Further, as shown in FIG. 16, test circuit modules 5g are arranged at predetermined intervals on the probe card 2b side formed on a semiconductor wafer W1 separate from the semiconductor wafer W to be tested, and one test circuit module A plurality of semiconductor chips CH on the semiconductor wafer W corresponding thereto may be tested by 5 g. In the probe card 2b, the hatched portions are the test circuit modules, and the other portions are the regions where the bumps and the wirings are formed. In FIG. 16, a circle indicates a range covered by one test circuit module 5g as a test target.

  FIG. 16 shows an example in which a single test circuit module 5g covers the test of a total of nine semiconductor chips CH of an opposing chip and surrounding chips. In this case, as shown in FIG. 17B, needles 6b made of bumps B are provided on the semiconductor wafer W1. Then, at the time of the wafer test, as shown in FIG. 17A, the test circuit module 5g of the semiconductor wafer W1 as the probe card 2b is formed on the main surface of the semiconductor wafer W on which the semiconductor chips are formed. By overlapping the surfaces, the needle 6b made of the bump B is brought into contact with the electrode pad of the semiconductor chip CH. Thereby, use durability can be improved. FIG. 17B is a partially enlarged view showing a portion denoted by reference numeral A in FIG. 17A in an enlarged manner.

  FIG. 23 shows an example of a mounting structure of a semiconductor chip cut out from a wafer after the test by the test circuit is completed. Among them, (a) is a general one-chip one-package type, (b) to (d) are ones in which a plurality of chips are sealed in one package, and (e) and (f) are ceramics and the like. This is a structure in which a chip mounted in a face-down manner on a substrate is molded with a resin RS. In FIG. 23, CH is a semiconductor chip, PG is a package made of resin or the like, BP is a bump provided on an electrode pad of the semiconductor chip CH, and LD is electrically connected to an electrode pad of the semiconductor chip CH via the bump BP. Lead terminals.

  Of the above structures, the one shown in FIG. 23A can be tested by a conventional tester, but the one shown in FIGS. 23B to 23D is tested by a tester because there are two or more chips in the package. In this case, the test pattern becomes very complicated unless each chip exists as an independent chip from the viewpoint of the tester, that is, if it is not configured to be able to be tested separately, the test program development and test execution time are considerably long. It will be long. In particular, in the structures of (b) and (f), since the test of the upper chip CH2 must be performed via the lower chip CH1, separate tests are impossible. Also, the test after mounting is difficult because the electrode pad of the chip is not exposed in the structure of (e).

  Therefore, with respect to a semiconductor chip having a mounting structure as shown in FIGS. 23 (b) to 23 (f), the test method performed at the wafer stage as in the above-described embodiment is adopted as compared with a test using a conventional tester. Much easier test programs and shorter test execution times.

  Next, when the semiconductor chip to be tested is a logic integrated circuit (logic IC), a specific example of an ALPG as a test circuit constructed in an FPGA to generate a test pattern will be described with reference to FIGS. explain. Among them, FIG. 24 shows a schematic configuration of an entire ALPG for generating test signals for a plurality of input terminals of a semiconductor chip under the control of a common control circuit in a shared resource system according to a predetermined algorithm, and a specific example of a sequence control circuit. Is shown.

  The ALPG shown in FIG. 24 includes a sequence control circuit 400 for sequentially controlling the entire ALPG, a test signal in response to a control signal from the sequence control circuit 400, and an output signal from a logic circuit (semiconductor chip) to be tested. It is composed of a driver / comparator block 300 which receives and outputs a pass / fail judgment signal in comparison with an expected value, and an interface circuit 210 which performs an interface between the ALPG and an external control device. A specific example of the driver / comparator block 300 is shown in FIG. 25, and a specific example of the interface circuit 210 is shown in FIG.

  As shown in FIG. 24, the sequence control circuit 400 among the above circuits includes an instruction memory 411 in which a microprogram composed of a plurality of microinstructions described according to a predetermined test pattern generation algorithm is stored. A program counter 412 that specifies a microinstruction to be read from the instruction memory 411, and decodes an instruction code in the microinstruction read from the instruction memory 411 to form a control signal for a circuit in the sequence control circuit 400 such as the program counter 412. Instruction decoding control circuit 430, a timing generator 420 for forming a timing control signal based on the reference clock φ0, and data for outputting control data to the timing generator 420 based on a timing setting bit MFd (TS bit) in the microinstruction. Register set 417, and a like decoder 418 for reading control data from the timing setting bits MFd (TS bit) data register set 417 decodes in the micro instruction. The instruction memory 411 and the data register set 417 are composed of data rewritable RAM or EEPROM.

  Also, among the logic circuits to be tested, in the case of a circuit whose function is specified (for example, ALU: Arithmetic Logic Unit), an appropriate test pattern formation method is already established in many cases. By using the assets of the test pattern, it is possible to efficiently generate the test pattern. As for the combinational logic circuit, there is known a fault assumption method and an efficient test pattern generation method called a D algorithm based on the idea of a single fault in which one circuit has one fault. By using this method, a microprogram for generating a test pattern can be shortened, and an increase in the capacity of the instruction memory 411 can be suppressed to an achievable level.

  In the ALPG of this embodiment, although not particularly limited, the timing setting bit TS decoded by the decoder 418 is composed of two bits, and the data register set 417 stores seven control data. One of these control data is data "RATE" which defines a test cycle, and the remaining six control data give output timing of a high level or low level signal for each signal line of the test bus. Two types of control data "ACLK1" and "ACLK2", two types of control data "BCLK1" and "BCLK2" for giving rise timings of pulse signals, and fall timings of pulse signals and comparison output timings with expected values are given. There are two types of control data "CCLK1" and "CCLK2".

  When each of these control data is supplied to the timing generation section 420, a signal RATE at a predetermined timing is supplied to the program counter 412 with respect to the control data RATE, and the micro instruction code is taken in from the instruction memory 411. It is. When “ACLK1” to “CCLK2” are supplied to the timing generator 420 as control data, a clock corresponding to the control code is output from the timing clocks ACLK1 to CCLK2 to the driver / comparator circuit 300. Connection and selection for use of each clock are appropriately performed as needed.

  Further, the ALPG sequence control circuit 400 selects an incrementer 421 for incrementing the value of the program counter 412 to “+1”, or any one of the incrementer 421 or a jump address in the address field MFa. A multiplexer 422 that supplies the number of repetitions in the operand field MFc to the program counter 412, a decrementer 424 for decrementing the value of the index register 423 by “−1”, A working register 425 for holding a value, a flag 427 indicating whether or not an operand used in a predetermined instruction is transferred to the program counter 412, and a value for selectively supplying the values of the registers 423 and 425 to the decrementer 424. Plexer 428, a demultiplexer 429 for distributing the provided value of the decrementer 424 to one of the plane of the working register 425.

  In the ALPG of FIG. 24, an operand field MFc for storing the number of instruction repetitions is provided in the micro-instruction code and an index register 423 for holding the number of repetitions is provided, so that the same test signal may be repeatedly generated. Thus, the number of required micro-instructions can be reduced and the micro-program can be shortened. In the ALPG of this embodiment, since the index register 423, the working register 425, and the flag 427 are provided in a plurality of planes (four in the figure), the sub-loop processing in a certain loop processing and the sub-loop processing in the sub-loop processing are further performed. Processing can be easily performed, and the microprogram can be shortened.

  FIG. 25 shows a specific example of the driver / comparator circuit 300. Although only the driver / comparator circuit corresponding to one of the signal lines constituting the test bus 220 is representatively shown in the circuit of FIG. 25, the circuit actually constitutes the test bus 220. The circuits shown in FIG. 25 are provided by the number of signal lines. Then, this test bus is formed in a scribe area on the wafer, and the ALPG is connected to a semiconductor chip as a logic circuit to be tested.

  As shown in FIG. 25, the driver / comparator circuit of this embodiment compares a driver circuit (signal forming circuit) 340 that forms a signal to be output to a test bus with a signal on the test bus and an expected value signal. A comparator circuit (comparison circuit) 350 for comparing the coincidence / non-coincidence, and a switching circuit 360 for switching between the driver circuit 340 and the comparator circuit 350. The switching circuit 360 includes a transmission gate TG1 provided between the driver circuit 340 and the input / output node Nio, and a transmission gate TG2 provided between the input / output node Nio and the comparator circuit 50. Either one is opened and the other is cut off according to the input / output control bit I / O supplied from the circuit 400.

  The driver circuit 340 includes an edge-triggered flip-flop 341 that fetches and holds the input / output control bit TP according to the timing clock ACLKi supplied from the timing generator 420, and the timing clocks BCLKi and CCLKi supplied from the timing generator 420. OR gate 342 that takes a logical sum, J / K flip-flop 343 that receives the output of OR gate 342 and the output of edge-triggered flip-flop 341 as input signals, and the output of J / K flip-flop 343 and sequence control An AND gate 344 which receives the input / output control bit CONT supplied from the circuit 400 as an input signal, inputs the output of the edge trigger flip-flop 341 and the input / output control bit CONT supplied from the sequence control circuit 400. An AND gate 345 to signal, and a driver 346 that drives the test bus by the output of these AND gates 344 and 345.

  On the other hand, the comparator circuit 350 includes an AND gate 351 that receives the timing clock CCLKi supplied from the timing generator 420 and the input / output control bit CONT supplied from the sequence control circuit 400 as input signals, and the D-type flip-flop 341. An exclusive OR gate 352 having an output (expected value) and a signal on a test bus supplied via a transmission gate TG2 as input signals, and outputs of the exclusive OR gate 352 and the AND gate 351 being input signals. And a flip-flop 354 that latches the output of the AND gate 353. A signal obtained by calculating the logical sum of the outputs of all the comparator circuits 350 is output as a total fail signal TFL. The input / output control bits I / O, TP, and CONT correspond to the control signal.

  As shown in FIG. 24, the microinstruction in the ALPG of the present embodiment stores an address field MFa storing a PC address indicating a jump address of an instruction used in a jump instruction, and a sequence control code. An operation code field MFb, an operand field MFc storing the number of instruction repetitions, and the like; a timing setting field MFd storing a timing setting bit TS for reading a control signal for the timing generator 420 from the data register set 14; An input / output control field MFe in which the input / output control bits of the driver / comparator circuit 300 are stored.

  Although the timing setting bits TS stored in the timing setting field MFd are two bits in this embodiment as described above, three or more bits may be provided. The input / output control bits stored in the input / output control field MFe correspond to three signal lines of the driver bus TP, the I / O bit, and the control bit CONT corresponding to the n signal lines of the test bus 220. Are set as one set, and only n sets are provided. Of these bits, the I / O bit is a control bit for designating input or output. When "1", the transmission gate TG1 is opened and TG2 is cut off to output the driver output signal to the corresponding test bus 220. The signal is output to the signal line, and when it is "0", the transmission gate TG1 is shut off and TG2 is opened to input the signal on the corresponding signal line of the test bus 220 to the comparison gate 352. The driver bit TP and the control bit CONT specify a high output or a low output, a positive pulse or a negative pulse output, an input invalid state, or an output high impedance state according to the combination.

  Table 1 shows the relationship between the input / output control bits TP, I / O, CONT and test signals (test patterns) output from the driver / comparator circuit 300.

  As shown in Table 1, when the input / output control bits TP, I / O, and CONT are “111”, the driver circuit 340 outputs a high-level signal. Control is performed such that a low-level signal is output, and when "110", driver circuit 340 outputs a positive pulse signal, and when "110", driver circuit 340 outputs a negative pulse signal. When the input / output control bits TP, I / O, and CONT are “101”, the comparator circuit 350 expects a high-level input signal, and when the input / output control bits TP, I / O, and CONT are “001”, the comparator circuit 350 expects a low-level input signal. , "100", control is performed such that the input signal is invalidated.

  In the driver / comparator circuit 300 of this embodiment, the state in which the control bits TP, I / O, and CONT are "000" has no meaning. However, when the control bits TP, I / O, CONT are "000", for example, the transmission gate TG1 is closed and TG2 is opened, and the exclusive OR gate 352 operates at two levels between the high level and the low level. The driver / comparator circuit 300 may be configured as a Schmitt circuit to compare the state where the potential of the input / output node Nio connected to the test bus 220 exists between the two levels (high impedance state). It is possible.

  FIG. 26 shows an example of the timing clocks ACLK1 to CCLK2 supplied from the timing generator 420 and signals output from the driver / comparator circuit 300 to the test bus 220 in the above embodiment. 26, (a) shows the reference clock φ0 supplied from the outside, (b) to (g) show the waveforms of the timing clocks ACLK1 to CCLK2, and (h) shows “1” as the output test signal in Table 9. 13 shows a waveform of an output signal of a terminal designated and ACLK1 selected as a clock. (I) shows the waveform of the output signal of the terminal in which “0” is designated as the output test signal in Table 1 and ACLK2 is selected as the clock. (J) shows the waveform of the output signal of the terminal in which "P" is designated as the output test signal in Table 1 and BCLK1 and CCLK1 are selected as the clock. Further, (k) shows the waveform of the output signal of the terminal where "N" is designated as the output test signal in Table 1 and BCLK2 and CCLK2 are selected as the clock.

  As can be seen from FIG. 26, the input / output control bits TP, I / O, and CONT are set to “111” and a high-level signal as shown in FIG. A low-level signal as shown in FIG. 26 (i) is output according to the clock ACLK2 from the terminal to which TP, I / O, and CONT are set to “011” and the clock ACLK2 is specified. From the terminal where CONT is set to "110" and the clocks ACLK1, BCLK1 and CCLK1 are specified, a positive pulse as shown in FIG. 26 (j) is output with BCLK1 and CCLK1 as edges according to the data set by the clock ACLK1. TP, I / O, CONT are set to “010” and clocks ACLK2, BCLK2, CCLK2 Negative pulse as shown in FIG. 26, the edge of BCLK2, CCLK2 accordance with the data which is set by the clock ACLK2 from the designated terminal (k) is output.

  Although not shown, the input / output control bits TP, I / O, and CONT are set to “101” and the terminal to which the clock CCLK1 is specified sets the expected value to the high level and uses the clock CCLK1 in FIG. 26F as a strobe signal. The comparison is performed. At the terminal to which TP, I / O, and CONT are set to "001" and the clock CCLK2 is specified, the expected value is set to the low level, and the comparison is performed using the clock CCLK2 of FIG. Note that the selection of the clock is not limited to the above, and may be any combination.

  The ALPG having the above configuration can arbitrarily change the generated test pattern and its output timing by rewriting the program stored in the instruction memory 411 and the control data stored in the data register set 417. Therefore, even when the semiconductor chips to be tested are different, it is possible to form an ALPG having the same architecture on the same wafer and perform the test. Also, even when an ALPG having the same architecture cannot be used, if the test target is in the same category as a logic IC or a memory, the architecture of the ALPG for testing it is similar, and therefore, for each semiconductor chip, Designing the optimal ALPG does not place a great burden on the designer.

  By the way, in order to rewrite data using the ALPG as a programmable device as described above, it is necessary to be able to connect to an external device. Therefore, the interface circuit 210 is provided in the ALPG of the embodiment of FIG. FIG. 27 shows a specific example of the interface circuit 210. When the test circuit is formed on the same wafer as the semiconductor chip to be tested as in the third embodiment, the number of electrode pads for connecting to an external device for rewriting data in the test circuit is large. Is undesirable. Thus, in the ALPG of this embodiment, a TAP (Test Access Port) 210 defined by the IEEE1149.1 standard is used as an interface circuit with an external device. By using the TAP as an interface, only a few electrode pads are required to connect to an external device for rewriting data.

  The TAP is an interface and a control circuit for a scan test and a BIST circuit specified by the IEEE1149.1 standard. The TAP is a bypass register 211 used when shifting test data from an input port to an output port. A data register 212 used for transmitting a signal, a device ID register 213 for setting a manufacturing identification number unique to a chip, an instruction register 214 used for selecting a data register and controlling an internal test method, and the entire TAP circuit Is configured by a controller 215 and the like for controlling

  The data register 212 is a register treated as an option. The instructions set in the instruction register 214 include four essential instructions and three optional instructions. A test mode select signal TMS for designating a test mode, a test clock TCK, and a reset signal TRST are input to the controller 215 from three dedicated external terminals, and the registers 211 to 214 are determined based on these signals. And control signals for the selector circuits 216 to 218.

  The TAP is provided with an input terminal for test data TDI and an output terminal for test result data TDO. The input test data TDI is supplied to each of the registers 211 to 214 or the internal scan path Iscan via the selector circuit 216. , Supplied to Bscan. The contents of the registers 211 to 214 and the scan-out data from the internal circuit are output to the outside of the chip via the selector circuits 217 and 218. Further, a signal to the internal BIST circuit is formed and supplied to the TAP in accordance with the contents of the data register 212 and the instruction register 214, and a signal indicating a test result output from the BIST circuit is transmitted through the selector circuits 217 and 218. So that it can be output to the outside of the chip.

  In the test system of the present invention, the test circuit (ALPG) formed on the wafer on which the logic circuit (semiconductor chip) to be tested is formed is regarded as a BIST circuit, and the signal input / output function for the BIST circuit of the TAP is provided. , The setting data for the data register set 417 of the ALPG, the microprogram stored in the instruction memory 411, and the test result by the ALPG are output. A clock φ0 for the ALPG timing generator 420 is also supplied via the TAP 210. In FIG. 27, the clock φ0 for the timing generator 420 is a separate clock from the clock TCK of the TAP 210, but TCK may be supplied to the timing generator 420 instead of φ0.

  In FIG. 27, "Iscan" means a test path for diagnosing the internal logic circuit using a shift register in which flip-flops constituting the internal logic circuit are connected in a chain as a scan path for test data. I do. “Bscan” uses a shift register in which flip-flops provided in a signal input / output unit are connected in a chain as a scan path to diagnose a connection state with another semiconductor integrated circuit (boundary scan test). Means a test pass to be performed. The function of the TAP for the scan test and the function of the boundary scan test are not used in the test system according to the present embodiment, and thus the description thereof is omitted.

  As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in the embodiments of FIGS. 9 and 10, it has been described that a test circuit is arranged on a wafer on which a semiconductor chip to be tested is formed and an ALPG as shown in FIG. 24 is used as the test circuit. Instead of forming the ALPG directly on the wafer, it is also possible to form an FPGA on the wafer on which the semiconductor chip to be tested is formed, and build and test the ALPG in this FPGA as shown in FIG. .

  In the embodiment of FIG. 24, when a test circuit is arranged on a wafer on which a semiconductor chip to be tested is formed, a TAP is used for an interface with an external device. However, the probe card and the probing module described above are used. When a test circuit is configured as described above, a TAP can be used as the interface.

  INDUSTRIAL APPLICABILITY The present invention can be widely used for testing semiconductor integrated circuit devices and manufacturing semiconductor integrated circuit devices.

FIG. 1 is an explanatory diagram of a test system according to a first embodiment of the present invention. FIG. 2 is an explanatory view of mounting a test IC mounted on the probe card according to the first embodiment of the present invention. FIG. 2 is an explanatory diagram of a virtual tester according to the first embodiment of the present invention. It is an explanatory view of a test system according to a second embodiment of the present invention. FIG. 7 is an explanatory diagram of a needle and a test IC formed on a probe card according to a second embodiment of the present invention. It is a figure showing an example of formation of a piece of a wafer which constitutes a probe card by a 2nd embodiment of the present invention. FIG. 11 is an explanatory diagram of a layout of a semiconductor chip to be tested and a test circuit module according to another embodiment of the present invention. (A) is a diagram showing an example of contact between a semiconductor wafer to be tested and a probe card according to another embodiment of the present invention, and (b) is an explanatory diagram in which a part thereof is enlarged. (A) is a figure which shows the example of arrangement | positioning of the test circuit module formed in the semiconductor wafer by 3rd Embodiment of this invention, (b) is explanatory drawing of a probing module. FIG. 11 is an explanatory diagram of a test measurement range in a tester according to a third embodiment of the present invention. FIG. 11 is a diagram illustrating an example of forming a test circuit module on a semiconductor wafer to be tested according to another embodiment of the present invention. FIG. 11 is an explanatory diagram showing an example in which a wiring connecting a test circuit module and a semiconductor chip according to another embodiment of the present invention is formed on a scribe area of a semiconductor wafer. FIG. 11 is an explanatory diagram showing another example in which wiring for connecting a test circuit module and a semiconductor chip according to another embodiment of the present invention is formed on a scribe area of a semiconductor wafer. FIG. 11 is a diagram illustrating an example of forming a test circuit module on a semiconductor wafer to be tested according to another embodiment of the present invention. FIG. 11 is a diagram illustrating another example of forming a test circuit module on a semiconductor wafer to be tested according to another embodiment of the present invention. FIG. 9 is a view showing still another example of forming a test circuit module on a semiconductor wafer to be tested according to another embodiment of the present invention. (A) is a diagram showing another example of a contact between a semiconductor wafer to be tested and a probe card according to another embodiment of the present invention, and (b) is an explanatory diagram in which a part thereof is enlarged. 9 is a flowchart showing a process from the start of development of a semiconductor integrated circuit device to shipment when a conventional tester is used. 6 is a flowchart showing a process from the start of development of a semiconductor integrated circuit device to shipment when the test method according to the embodiment of the present invention is applied. FIG. 11 is a layout explanatory diagram showing a relatively efficient wiring connection method in a case where one test circuit module tests eight surrounding semiconductor chips. FIG. 10 is a layout explanatory diagram showing another example of a relatively efficient wiring connection method in a case where one test circuit module tests eight semiconductor chips around it. FIG. 11 is a layout explanatory diagram showing another example of a relatively efficient wiring connection method in a case where one test circuit module tests 24 surrounding semiconductor chips. FIG. 3 is an explanatory sectional view showing an example of a mounting structure of a semiconductor chip cut out from a wafer. FIG. 2 is a block diagram illustrating a configuration example of an ALPG as a test circuit used in the present invention. FIG. 3 is a logical configuration diagram illustrating a specific example of a driver / comparator circuit configuring the ALPG. FIG. 25 is a waveform chart showing an example of a test signal waveform formed by the ALPG of FIG. 24. FIG. 3 is a block diagram illustrating a configuration example of an interface circuit configuring the ALPG.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Test system 2, 2a, 2b probe card 3 Control device 3a Power supply device 4, 4a, 4b Probe card board 5-5f Test IC, test circuit module (test circuit)
6,6a, 6b Needle 7-9 FPGA
DESCRIPTION OF SYMBOLS 10 Pattern generation part 11 Timing generation part 12 Power supply part 13 DC test circuit 14 Driver 15 Comparator 16 Microcomputer 17 Wafer piece 18 Fixed frame 19 Probe module 210 Interface circuit 300 Driver / comparator block 340 Driver circuit 340
350 Comparator circuit (comparison circuit)
360 switching circuit 400 sequence control circuit 411 instruction memory 412 program counter 420 timing generator 430 instruction decoding control circuit W, W1 semiconductor wafer CH semiconductor chip TCI semiconductor integrated circuit device B bump SA scribe area D1, D2 electrode pad H test wiring

Claims (15)

  A plurality of semiconductor chips having a desired function are formed on a semiconductor wafer, and the size of the semiconductor chip is set on a probe substrate having a size corresponding to the wafer and a conductive needle formed in accordance with the arrangement of the electrode pads of the semiconductor chip. A test circuit connected to the needle and operating according to a program to test the semiconductor chip, and the probe substrate is superimposed on the wafer so that the needle is brought into contact with a corresponding electrode pad of the semiconductor chip. A method for testing a semiconductor chip by the test circuit, and selecting a semiconductor chip determined as a non-defective product as a product.   A programmable logic IC capable of configuring any logic on the probe substrate is provided for each semiconductor chip on the wafer, and the programmable logic IC is configured based on the design data of the semiconductor chip described in a hardware description language. 2. The method according to claim 1, wherein the test circuit is configured in an IC, and the test circuit tests the semiconductor chip.   3. The semiconductor integrated circuit according to claim 1, wherein the test circuit is a test signal generation circuit configured to generate a test signal supplied to a semiconductor chip to be tested according to a predetermined algorithm. Device manufacturing method.   The test signal generation circuit includes an instruction memory that holds a program, a control unit that decodes an instruction of the program to generate a control signal, and a signal generation unit that generates a signal to be output. The method for manufacturing a semiconductor integrated circuit device according to claim 3.   5. The method according to claim 4, wherein a program stored in the instruction memory is rewritable from outside.   The test signal generation circuit further includes timing generation means for generating a desired timing signal by receiving a reference clock signal and control data from a storage means for holding control data relating to timing. The method for manufacturing a semiconductor integrated circuit device according to claim 4.   7. The method according to claim 6, wherein the control data stored in the storage unit is rewritable from outside.   A test circuit module that operates according to a program and tests the semiconductor chip is formed on a semiconductor wafer on which a plurality of semiconductor chips having desired functions are formed, and a power supply voltage is supplied from an external source to at least the test circuit module. A method of manufacturing a semiconductor integrated circuit device, wherein the semiconductor chip on the wafer is tested by a test circuit module, and a semiconductor chip determined as a non-defective product is selected as a product.   A conductive needle having a size corresponding to a wafer on which the semiconductor chip is formed and having a size corresponding to the arrangement of the test circuit module and the electrode pads of the semiconductor chip, for connection between the test circuit module and the semiconductor chip to be tested. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein said method is performed by a probe means in which wiring connecting predetermined needles is formed.   9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the connection between the test circuit module and the semiconductor chip to be tested is performed by a wiring formed in a scribe area of a wafer or a wiring layer dedicated to the test. .   11. The method according to claim 10, wherein the test wiring connecting the test circuit module and the semiconductor chip to be tested is formed so as to meander in a scribe area of the wafer.   12. The method according to claim 8, wherein the test of the semiconductor chip on the wafer by the test circuit module is performed during a burn-in or aging process. The function of the semiconductor chip to be tested is described in a hardware description language, the hardware description and the test program are input to a hardware emulator, and the hardware emulator performs a simulation to verify the function. While converting into design data, and further generating element-level layout design data of the semiconductor chip to be tested based on the design data,
A test function is extracted based on the data used in the simulation, the test function is described in a hardware description language, the description is converted to logic gate level design data, and the test is performed based on the design data. Generate element-level layout design data for circuit modules,
A mask for a wafer is manufactured using the element-level layout design data of the semiconductor chip to be tested and the element-level layout design data of the test circuit module, and the semiconductor chip to be tested and the test are manufactured using the mask. 13. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein the circuit module is formed on one wafer.   14. The method according to claim 8, wherein the test circuit module generates a test signal to be supplied to a plurality of semiconductor chips disposed around the test circuit module.   9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein said test circuit module tests a plurality of semiconductor chips formed on said semiconductor wafer.

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