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WO2001099167A2 - Dispositif memoire comportant des nano-amas et procede de fabrication dudit dispositif - Google Patents

Dispositif memoire comportant des nano-amas et procede de fabrication dudit dispositif Download PDF

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Publication number
WO2001099167A2
WO2001099167A2 PCT/US2001/016585 US0116585W WO0199167A2 WO 2001099167 A2 WO2001099167 A2 WO 2001099167A2 US 0116585 W US0116585 W US 0116585W WO 0199167 A2 WO0199167 A2 WO 0199167A2
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Prior art keywords
nanoclusters
tunnel dielectric
forming
layer
substrate
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WO2001099167A3 (fr
Inventor
Sucharita Madhukar
Ramachandran Muralidhar
David L. O'meara
Hsing H. Tseng
Bruce E. White
Michael A. Sadd
Sufi Zafar
Bich-Yen Nguyen
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Motorola Solutions Inc
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Motorola Inc
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Priority to AU2001263370A priority Critical patent/AU2001263370A1/en
Publication of WO2001099167A2 publication Critical patent/WO2001099167A2/fr
Publication of WO2001099167A3 publication Critical patent/WO2001099167A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

Definitions

  • the invention relates generally to semiconductor devices and more particularly to a semiconductor memory device and a process for forming such a semiconductor memory device.
  • EEPROM Electrically erasable programmable read only memory
  • EEPROM device structures commonly include a floating gate that has charge storage capabilities. Charge can be forced into the floating gate structure or removed from the floating gate structure using control voltages. The conductivity of the channel underlying the floating gate is significantly altered by the presence of charges stored in the floating gate. The difference in conductivity due to a charged or uncharged floating gate can be current sensed, thus allowing binary memory states to be determined. The conductivity difference is also represented by shift in the threshold voltage (V ⁇ ) associated with the device in the two different states.
  • V ⁇ threshold voltage
  • the operating voltages of such semiconductor devices are often reduced in order to suit low power applications. It is desirable for such operating voltage reductions to be accomplished while ensuring that the speed and functionality of the devices is maintained or improved.
  • a controlling factor in the operating voltages required to program and erase devices that include floating gates is the thickness of the tunnel oxide through which carriers are exchanged between the floating gate and the underlying channel region.
  • the floating gate is formed from a uniform layer of material such as polysilicon.
  • a thin tunnel dielectric layer beneath the floating gate presents the problem of charge leakage from the floating gate to the underlying channel through defects in the thin tunnel dielectric layer. Such charge leakage can lead to degradation of the memory state stored within the device and is therefore undesirable.
  • the thickness of tunnel dielectric is often increased.
  • thicker tunnel dielectric requires higher (programming and erasing) voltages for storing and removing charge from the floating gate as the charge carriers must pass through the thicker tunnel dielectric.
  • higher programming voltages require the implementation of charge pumps on integrated circuits in order to increase the supply voltage to meet programming voltage requirements. Such charge pumps consume a significant amount of die area for the integrated circuit and therefore reduce the memory array area efficiency and increase overall costs.
  • the uniform layer of material used for the floating gate may be replaced with a plurality of nanoclusters, which operate as isolated charge storage elements.
  • Such nanoclusters are also often referred to as nanocrystals, as they may be formed of silicon crystals.
  • the plurality of nanoclusters provide adequate charge storage capacity while remaining physically isolated from each other such that any leakage occurring with respect to a single nanoclusters via a local underlying defect does not cause charge to be drained from other nanoclusters (by controlling average spacing between nanoclusters, it can be ensured that there is no lateral charge flow between nanoclusters in the floating gate).
  • thinner tunnel dielectrics can be used in these device structures. The effects of leakage occurring in such thin tunnel dielectric devices does not cause the loss of state information that occurs in devices that include a uniform-layer floating gate.
  • a limiting factor in fabrication of devices that include floating gates made up of a plurality of nanoclusters relates to controlling of the size, density, and uniformity of the nanoclusters within the floating gate structure.
  • the density of the nanoclusters is important in the determination of the change in the threshold voltage for the device between the states where the floating gate is charged or discharged. Higher densities are desirable as they lead to an increased change in threshold voltage when the density of charges per storage element is fixed.
  • Prior art techniques for forming nanoclusters on the oxide tunnel dielectric were limited to a density of approximately 5 x 10 11 nanoclusters per cm 2 . With such a limited density of isolated storage elements, the charge density per nanocluster, or number of carriers that each nanocluster must retain, is forced to an elevated level.
  • the higher storage density per nanocluster typically leads to charge loss from individual nanoclusters, thus degrading the overall charge retention characteristics of the floating gate.
  • lower nanocluster densities require longer programming times as a longer time period is required for forcing subsequent charge carriers into each nanocluster after an initial carrier has been stored.
  • the time required for adding subsequent carriers continues to increase as the charge density per nanocluster is elevated.
  • ion implantation is used to implant silicon atoms into a dielectric material. Following implantation, an annealing step causes these implanted silicon atoms to group together through phase separation to form the nanoclusters. Problems arise using such a technique due to the difficulty in controlling the depth at which the silicon nanoclusters are formed due to the phase segregation in the dielectric material. Because the depth at which the isolation storage elements are formed dramatically affects the electrical characteristics of the resulting device, ion implantation does not provide the level of control desired in a manufacturing situation.
  • a thin layer of amorphous silicon is deposited on the tunnel dielectric material.
  • a subsequent annealing step is used to recrystalize the amorphous silicon into the nanoclusters.
  • the layer of amorphous silicon should be deposited such that it is on the order of 7-10 angstroms in thickness. Deposition of such thin layers of amorphous silicon is hard to control and therefore impractical in a manufacturing process. In addition to such control issues, additional problems may arise due to preexisting crystalline zones within the amorphous silicon layer. Such preexisting crystallites serve as nucleation sites for crystal growth, which deleteriously interferes with the spontaneous crystal growth desired for formation of the nanoclusters.
  • CVD chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • Such prior art LPCVD techniques typically involve a very short deposition time period, on the order of approximately 10-30 seconds. Part of this deposition time period includes an incubation period where an adequate number of silicon atoms are generated on the surface of the dielectric prior to the commencement of the clustering activity that forms the crystalline structures of the nanoclusters. The remaining portion of the time is used to nucleate and grow the nanoclusters to the desired size.
  • FIG. 1 includes a graph that illustrates curves associated with nanocluster formation, where such curves plot nanocluster density versus time during CVD processing
  • FIG. 2 illustrates a cross-sectional view of a portion of a semiconductor substrate that includes a formed layer of tunnel dielectric
  • FIG. 3 illustrates a cross-sectional view of the portion of the semiconductor substrate of FIG. 2 following formation of an overlying nitrogen-containing layer in accordance with a particular embodiment of the present invention
  • FIG. 4 illustrates a cross-sectional view of the portion of the semiconductor substrate of FIG. 2, including a representation of the initial molecular bonding structure at the surface of the tunnel dielectric layer;
  • FIG. 5 illustrates a cross-sectional view of the portion of the semiconductor substrate of FIG. 4 following alteration of the molecular bonding structure at the surface of the tunnel dielectric layer in accordance with a particular embodiment of the present invention
  • FIG. 6 illustrates a cross-sectional view of the portion of the semiconductor substrate of Figure 2 where nanocluster nucleation has been initiated in accordance with a particular embodiment of the present invention
  • FIGs. 7-9 illustrate cross-sectional views of the portion of the semiconductor substrate of FIG. 6 at subsequent time intervals corresponding to the formation of the nanoclusters in accordance with a particular embodiment of the present invention
  • FIG. 10 illustrates a cross-sectional view of the semiconductor substrate portion of FIG. 9 where the nanoclusters have been partially or fully relaxed to equilibrium with the surface of the tunnel dielectric layer in accordance with a particular embodiment of the present invention
  • FIG. 11 illustrates a cross-sectional view of the semiconductor substrate portion of FIG. 10 upon which a control dielectric layer has been formed in accordance with a particular embodiment of the present invention
  • FIG. 12 illustrates a cross-sectional view of the semiconductor substrate portion of FIG. 11 upon which a gate material layer has been formed in accordance with a particular embodiment of the present invention
  • FIG. 13 illustrates a cross-sectional view of the semiconductor substrate portion of FIG. 12 where the gate material layer has been patterned to form a gate electrode in accordance with a particular embodiment of the present invention
  • FIG. 14 illustrates a cross-sectional view of the semiconductor substrate portion of FIG. 13 where a portion of the control dielectric layer has been selectively removed in accordance with a particular embodiment of the present invention
  • FIG. 15 illustrates a cross-sectional view of the semiconductor substrate portion of FIG. 14 after selective removal of portions of the tunnel dielectric layer, the plurality of nanoclusters, and the control dielectric layer in accordance with the particular embodiment of the present invention
  • FIG. 16 illustrates a cross-sectional view of the semiconductor substrate portion of FIG. 15 where spacers, a source region, and a drain region have been formed for a semiconductor device in accordance with a particular embodiment of the present invention
  • FIGs. 17-19 illustrate cross-sectional views of the semiconductor substrate portion of FIG. 3 after sequential steps used to form a nitrogen-containing layer section overlying the tunnel dielectric layer in accordance with a particular embodiment of the present invention
  • FIG. 20 illustrates a cross-sectional view of the semiconductor substrate portion of FIG. 19 following selective growth of nanoclusters in accordance with a particular embodiment of the present invention
  • FIG. 21 illustrates an expanded cross-sectional view of a plurality of nanoclusters formed on a tunnel dielectric layer in accordance with a particular embodiment of the present invention
  • FIG. 22 illustrates an expanded cross-sectional view of the plurality of nanoclusters of FIG. 21 following partial or complete relaxation with the surface of the underlying tunnel dielectric layer in accordance with a particular embodiment of the present invention
  • FIG. 23 illustrates an expanded cross-sectional view of the nanoclusters of FIG. 22 where the nanoclusters have been encapsulated in an encapsulation layer in accordance with a 1 particular embodiment of the present invention
  • FIG. 24 illustrates an expanded cross-sectional view of the structure of FIG. 23 where a control dielectric layer has been formed overlying the tunnel dielectric layer and the encapsulated nanoclusters in accordance with a particular embodiment of the present invention
  • FIG. 25 illustrates an expanded cross-sectional view of the nanoclusters of FIG 22 following formation of a thin dielectric layer overlying the plurality of nanoclusters in accordance with a particular embodiment of the present invention
  • FIG. 26 illustrates an expanded cross-sectional view of the structure of FIG.
  • FIG. 27 illustrates an expanded cross-sectional view of the structure of FIG. 22 following formation of a multi-layered control dielectric overlying the plurality of nanoclusters;
  • FIG. 28 illustrates a schematic diagram of a processing apparatus for forming a tunnel dielectric layer, a plurality of nanoclusters overlying the tunnel dielectric layer, and a portion or the entirety of an overlying control dielectric in accordance with a particular embodiment of the present invention.
  • the present invention pertains to a semiconductor memory device with a floating gate that includes a plurality of nanoclusters and techniques useful in the manufacturing of such a device.
  • the device is formed by first providing a semiconductor substrate upon which a tunnel dielectric layer is formed. A plurality of nanoclusters is then grown on the tunnel dielectric layer. Such growth is facilitated by formation of a nitrogen-containing layer, which may be nitride, overlying the tunnel dielectric layer. Selected portions of the nitrogen-containing layer may be removed to aid in controlling where nanoclusters are formed.
  • the growth of the nanoclusters may also be facilitated by treating the surface of the tunnel dielectric to alter the bonding structure of the tunnel dielectric layer.
  • a control dielectric layer is formed over the nanoclusters.
  • a gate electrode is then formed over the control dielectric, and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed.
  • source and drain regions are formed by implantation in the semiconductor layer such that a channel region is formed between the source and drain regions underlying the gate electrode.
  • the density of nanoclusters included in the floating gate structure can be closely controlled.
  • references to LPCVD processing describe processing that may be performed using LPCVD or RTCVD processing techniques.
  • a multistep process may be utilized to ensure proper nucleation and growth selectivity for different phases of the nanocluster formation. As such, desired nanocluster densities can be achieved while ensuring uniformity in size and density in a manufacturable process.
  • UHVCVD is utilized to grow the nanocluster structures
  • additional advantages are achieved due to the reduction in background contamination in the environment within which the nanocluster formation occurs. Similar optimizations to the formation of the nanoclusters that were utilized in LPCVD techniques can be employed in UHVCVD techniques to produce the desired resulting nanocluster structures.
  • UHVCVD techniques even lower pressures than those present in LPCVD techniques can provide a further reduction in growth kinetics such that a higher level of control is obtained over the nanocluster formation.
  • potential gradients in nanocluster growth rates due to precursor gas depletion effects are further minimized.
  • FIG. 1 illustrates a graph that shows the general evolution of the nanoclusters during the nucleation and growth phases as a function of time.
  • Two curves 302 and 312 are illustrated in FIG. 1.
  • the curve 302 corresponds to nanocluster development consistent with prior art techniques in which higher temperatures and shorter growth time periods produced through a single step deposition process resulted in a limited level of control over nanocluster growth.
  • the parameters associated with such prior art techniques provide a lack of control of the selectivity of nucleation to growth with regard to nanocluster formation during all phases of the one step process to which the curve 302 corresponds.
  • the curve 302 corresponding to the prior art deposition technique begins with a brief incubation phase where silicon atoms begin to be deposited on the tunnel dielectric layer. Once enough silicon atoms have been deposited on the dielectric material, nucleation begins to occur. Due to the fact that higher temperatures are used in conjunction with the prior art technique, the surface diffusion rate of silicon atoms present on the dielectric layer will be higher than that in a lower temperature environment. The size of the stable critical nucleus is also higher at the higher deposition temperature. The growth of the already formed nuclei is also higher at the higher temperature.
  • the silicon atoms arriving on the surface of the dielectric must move through a longer diffusion distance before they are either captured by an already existing nucleus or they combine with other diffusing silicon atoms to form a stable nucleus.
  • the probability of capture of a silicon atom by an existing nucleus is higher at higher temperature due to longer diffusion distances, hence the growth rate of nuclei dominates the nucleation rate. This type of limited nucleation and rapid growth is undesirable as it results in smaller numbers of large nanoclusters.
  • the curve 312 corresponds to nanocluster development in accordance with a portion of the teachings provided herein. Such teachings provide a lower temperature process that results in a much greater level of control over nanocluster nucleation and growth. As such, the nanocluster development can be performed as a multi-step process rather than a single, hard to control step.
  • a highly selective nucleation phase 318 occurs. The nucleation phase 318 allows for a high nucleation-to-growth ratio with respect to nanocluster formation on the tunnel dielectric surface.
  • silicon atoms (or atoms of other materials used to form the nanoclusters) present on the tunnel dielectric surface are much more likely to form nuclei than they are to attach to pre-existing nuclei, which would result in growth.
  • the conditions that favor such a selective nucleation phase include low temperatures and higher partial pressures of the reactant gas. Note that the temperature should not be so low as to become reaction limited.
  • a plurality of critical nuclei is formed.
  • a saturation region 314 that is much longer than that associated with prior art nanocluster formation techniques allows for controlled growth of the nucleated nanocluster structures.
  • the critical nuclei are grown into nanoclusters.
  • the control present during the saturation region 314 enables nanoclusters of the desired size to be formed uniformly across the surface of the tunnel dielectric layer covering the substrate. Due to the fact that the saturated region 314 is relatively lengthy in time, the optimal saturation density 316 may be achieved in a manufacturing environment. Thus, deviations with respect to the time period over which the nanocluster growth occurs will have less of an effect on the resulting density of nanoclusters on the tunnel dielectric.
  • factors that are important for prolonging the saturation region 314 include lower partial pressures of the precursor gas and a temperature greater than or equal to the temperature of nucleation.
  • the factors that elevate the growth rate during the saturation region 314 also decrease the nucleation rate normally associated with the nucleation phase 318.
  • the deposition of the nanoclusters on the dielectric layer is divided into a two-step process, where each step can be individually controlled to achieve the desired result.
  • the times associated with the curves illustrated in FIG. 1 are merely provided as examples, and are not to be construed as limiting.
  • the time period associated with the nucleation and growth phases of the curve 312 may be modified based on alterations to the conditions present during the different deposition phases. As is apparent to one of ordinary skill in the art, higher temperatures will reduce the time periods associated with each of the phases when the partial pressures are maintained at a constant level. Similarly, higher pressures will reduce the time periods associated with the various phases when the temperature is held constant.
  • FIG. 2 illustrates a cross-sectional view of a portion of a semiconductor substrate 10 that includes a semiconductor layer 12.
  • the semiconductor layer 12 may be silicon.
  • a tunnel dielectric layer 14, which may also be referred to as tunnel oxide, has been formed overlying the semiconductor layer 12.
  • the tunnel dielectric layer 14 may be silicon dioxide, silicon oxynitride, or other high dielectric constant (high-K) materials.
  • the tunnel dielectric layer 14 may be thermally grown or deposited.
  • the thickness of the tunnel dielectric layer 14 may be on the order of less than 50 angstroms. In the case where the device formed is used in more volatile memory structures, thinner tunnel dielectric layers, such as those on the order of 15-20 Angstroms may be used.
  • the surface of the tunnel dielectric layer 14 can be modified to promote nucleation of nanocluster structures.
  • the surface structure can be modified such that critical nucleus size, surface diffusion of silicon atoms is reduced, and the reactant byproducts desorption is increased.
  • FIG. 3 illustrates one technique for altering the surface of the tunnel dielectric layer 14 in order to promote nucleation.
  • FIG. 3 illustrates a cross sectional view of the portion of the semiconductor substrate 10 where a nitrogen-containing layer 502 has been formed over the tunnel dielectric layer 14.
  • the nitrogen-containing layer 502 may include nitride (Si 3 N 4 ) or silicon oxynitride (SiO x N y ).
  • Both nitride and silicon oxynitride change the surface structure of the tunnel dielectric such that nucleation is promoted.
  • nucleation promotion includes a reduction in the size of a critical nucleus in terms of number of atoms, a decrease in the surface diffusion rate that promotes nucleation of nanoclusters, an increase in the surface reaction such that undesired byproducts resulting from nanocluster formation are desorbed more rapidly from the surface, and an improved adhesion of the atoms comprising the nanoclusters to the substrate surface.
  • the nitrogen-container layer 502 may be formed by CVD processes such as LPCVD or UHVCVD, and the nitrogen-containing layer 502 may be in direct contact with the tunnel dielectric layer 14.
  • UHVCVD of the nitrogen-containing layer may be more controllable than LPCVD as the UHVCVD generally occurs more slowly and therefore the growth rate may be more closely regulated.
  • the nitrogen-containing layer may be a result of deposition from the reaction of such gases as silane (or other silicon source precursor such as dic lorosilane, or disilane) and ammonia (or other nitrogen species such as plasma-ionized nitrogen, N 2 0 or NO) or a surface reaction to a reacting gas such as ammonia (or other nitrogen species such as plasma-ionized nitrogen, N 2 0 or NO).
  • a reacting gas such as ammonia (or other nitrogen species such as plasma-ionized nitrogen, N 2 0 or NO).
  • Dichlorosilane and ammonia gas in combination with a co-flow of some inert gas and oxygen-containing gas may be used for growth of the nitrogen- containing layer 502.
  • the thickness of the nitrogen-containing layer 502 is preferably limited to ensure that carrier traps included in nitride structures do not dominate the charge storage aspects of the semiconductor device being formed.
  • a desired thickness for the nitrogen-containing layer is less than 10 angstroms. In other embodiments, the desired thickness may be 5 angstroms or less. Utilizing thin nitrogen-containing layers ensures that the long term charge retention characteristics of memory devices formed using floating gate structures that include nanoclusters will meet desired specifications. Thicker nitrogen-containing layers, such as those on the order of 20 or more angstroms, may be undesirable as the charge retention characteristics of the resulting device may be compromised through the limited charge retention characteristics of the nitrogen- containing layer.
  • the nitrogen-containing layer will trap some of the carriers intended to be stored within the nanocluster structures. Such trapped carriers in the nitride level can dominate the overall charge retention characteristics of the resulting device. Furthermore, the inclusion of thicker nitrogen-containing layers, such as those greater than or equal to 20 angstroms, may increase the time associated with forcing carriers into the nanocluster structures as the traps capture some of the carriers en route.
  • the nitride layer may be less than or equal to 7 angstroms.
  • the thickness of the nitrogen-containing layer should be at least that required to ensure generally uniform coverage of the tunnel dielectric layer 14 by the nitrogen-containing layer 502 such that uniform nanocluster deposition occurs. Therefore, in some embodiments, the thickness of the nitride layer is greater than or equal to 3 angstroms such that an acceptable nitride thickness range may be between 3 and 7 angstroms.
  • the concentration of nitrogen within the silicon oxynitride may be greater than 5%.
  • the percentage concentration of nitrogen included in the silicon oxynitride can be controlled such that the trade-off between the saturation density of nanoclusters that can be formed on the surface and the inclusion of traps due to nitride concentration is regulated.
  • the nucleation of nanoclusters on the surface of the tunnel dielectric layer 14 can be improved by altering the surface bonding structure of the tunnel dielectric layer 14.
  • FIG. 4 illustrates a cross-sectional view of the portion of the semiconductor substrate 10 following formation of the tunnel dielectric layer 14. The tunnel dielectric layer 14 in FIG.
  • each of the two silicon atoms within the silicon dioxide bonding structure 504 is bonded to a single oxygen atom. This bonding structure is generally less reactive to the silane precursor gas commonly used for silicon nanocluster formation.
  • a reactant gas species can be applied to the surface.
  • HF hydrofluoric acid
  • reagents can be applied to the surface of the tunnel dielectric layer 14 to alter the bonding structure such that the resulting surface bonding structure facilitates adsorption of silane, reduces the critical nucleus size, improves reaction byproduct desorption and therefore improves the nucleation of nanocrystals on the tunnel dielectric layer 14.
  • FIG. 5 illustrates a cross-sectional view of the portion of the semiconductor substrate 10 where the bonding structure for the top portion or surface of tunnel dielectric layer 14 has been altered by exposure to a reagent.
  • the bonding structure 506 illustrates individual silicon atoms bonded to an oxygen reactant pair where in the case of exposure to HF, the reactant (R) will be hydrogen (H) or fluorine (F).
  • the reactant (R) will be hydrogen (H) or fluorine (F).
  • different reagents, or reactant gases may be used in place of HF.
  • Example reagents include gases such as germane, phosphine, diborane, ammonia, and water vapor.
  • the reactant portion of the bonding structure 506 may be different materials, where the bonding structure 506 is more reactive to silane gas and therefore improves nucleation on the surface of the tunnel dielectric layer 14. Therefore, other similar reactant gases may be utilized to achieve the same alteration in bond structures as described with respect to FIG. 5. Reacting the surface portion of the tunnel dielectric 14 to alter the bonding structure can be achieved through wet etching operations or by performing an annealing process using a reactant gas at a temperature known to facilitate such bond
  • FIG. 6 illustrates a cross-sectional view of the portion of the semiconductor substrate 10 as formed in FIG. 2 where nuclei 15, which eventually grow into nanoclusters, have begun to form.
  • the time interval associated with FIG. 6 preferably corresponds to the nucleation phase 318 of the curve 312 illustrated in FIG. 1.
  • the surface of the tunnel dielectric layer 14 of FIG. 6 may have been treated using one or more of the methods described with respect to FIGs. 3-5 in order to facilitate nucleation.
  • the nucleation shown to be occurring in FIG. 6 typically follows the incubation period described with respect to FIG. 1.
  • CVD process which may be an LPCVD process or a UHVCVD process.
  • Such CVD processes typically occur within a controlled environment of a CVD chamber.
  • CVD processes involve flowing a precursor gas into the chamber under controlled conditions such that molecules in the precursor gas adsorb on the surface of the substrate wafer and react to form the desired species. Typically undesired byproducts resulting from the CVD operation will desorb from the surface and exit the chamber.
  • the nanoclusters are typically formed of semiconductor materials such as silicon, germanium, or silicon germanium alloy.
  • the precursor gas utilized to form the silicon nanoclusters may be silane, disilane, or other silicon- containing gas.
  • silicon-containing gases can be used to promote both initial nucleation and further growth of the nanoclusters until the desired density and size is obtained.
  • the conditions within the CVD chamber are closely controlled. A number of factors influence whether nucleation or growth occurs with respect to the nanoclusters being formed.
  • the nature of the surface of the tunnel dielectric layer 14, the partial pressure the semiconductor-containing gas, the temperature within the chamber, and the presence and identity of any co-flow gases can be controlled.
  • Parameters suitable for initial nucleation of silicon nanoclusters include a chamber temperature not exceeding 600°C, a silicon- containing gas flow rate that is greater than or equal to approximately 50 standard cubic centimeters per minute (SCCM), a partial pressure for the silicon-containing gas that is less than or equal to about 200 mTorr.
  • the substrate with the overlying tunnel dielectric layer 14 may be placed in a CVD chamber and heated to a temperature not exceeding 600 degrees Celsius at which point silicon nanoclusters may be formed by flowing gas as stated above.
  • a temperature of 580 degrees Celsius using 100 per cent silane at 1000SCCM for one minute has been found to be effective
  • the temperature within the chamber during nanocluster formation may be between 500° and 600°C. Further reduction in temperature below 500°C may result in reduction in the desorption rate of hydrogen from the surface of the semiconductor wafer during nanocluster formation. Such a reduction in the desorption rate of hydrogen can impede the nucleation process by blocking reactant sites which could be available for silicon- containing precursor adsorption.
  • FIG. 7 illustrates a cross-sectional view of the portion of the semiconductor substrate 10 as formed in FIG. 6 following additional nucleation and some growth of established nuclei.
  • the established nuclei 16 have been shown to increase in size through the addition of subsequent atoms, whereas additional nuclei 17 may be forming during this intermediate stage between a first phase, where primarily nucleation is occurring, and a second phase, where primarily growth of established nuclei occurs.
  • FIG. 8 illustrates a cross-sectional view of the portion of the semiconductor substrate 10 as formed in FIG. 7 where nucleation has generally ceased as the size and density of the established nuclei 18 has reached a point where atoms tend to join the established nuclei rather than generating new nuclei.
  • the point at which such a changeover from nucleation to growth occurs can be controlled by variation of the process parameters such that the desired density of nanoclusters can be achieved.
  • the conditions within the CVD chamber may be adapted to promote growth of the established nanoclusters 18.
  • the conditions that promote nanocluster growth may include lower partial pressure of the precursor gas, which may be a silicon- containing gas as described earlier.
  • the partial pressure of the silicon-containing gas may be reduced to a point where the partial pressure is less than or equal to 10 mTorr.
  • An additional factor that may promote growth over nucleation is an increased temperature, as faster moving atoms are more likely attach to established nucleation sites rather than forming new nuclei. Decreased partial pressures of the silicon-containing gas causes fewer silicon atoms to form on the surface such that the growth rate of the nanoclusters can be closely controlled.
  • co-flow gases are often employed in order to ensure process stability.
  • co-flow gases can inhibit the deposition of silicon and the growth of nanoclusters.
  • hydrogen is a common co-flow gas utilized in conjunction with silane.
  • the breakdown of the silane gas into silicon and hydrogen can be inhibited by a hydrogen co-flow gas, as the hydrogen by-product of the silane breakdown operation is prevented from desorbing from the surface of the wafer.
  • a gas mixture that includes inert co-flow gases, such as nitrogen or argon, along with a semiconductor-containing gas, such as silane or disilane, may be used to enhance silicon deposition on the wafer.
  • inert co-flow gases such as nitrogen or argon
  • semiconductor-containing gas such as silane or disilane
  • co-flow gases may not be required to promote the distribution of the silane or other semiconductor-containing gas within the chamber.
  • the semiconductor-containing gas may be present without any co-flow gases in the CVD chamber during UHVCVD nanocluster formation.
  • the semiconductor wafer is preferably kept in a non-oxidizing ambient to inhibit oxidation of the nanoclusters. Further steps can be taken to inhibit oxidation, such as encapsulation of the nanoclusters, which is described in additional detail with respect to FIGs 21-27 below.
  • a further step that can reduce the harmful effects of such oxidation is to allow the silicon nanoclusters to obtain their equilibrium shape, which may be a generally lens-like or hemispherical configuration as shown with respect to the nanoclusters 21 in FIG. 10.
  • the contact angle of molten silicon on a silicon dioxide tunnel dielectric layer is approximately 90°.
  • general shape of the nanoclusters may evolve to form the shape similar to that of the nanoclusters 21.
  • the exact profile of the nanoclusters may be dependent on the wetting characteristics of the underlying tunnel dielectric layer 14. As such, pre-treating of the tunnel dielectric layer 14 may be performed to promote such wetting.
  • the general shape of the resulting nanocluster structures is more likely to be in a non-equilibrium configuration such as the configuration of the nanoclusters 19 in FIG. 9.
  • an annealing process may be utilized.
  • the extended time period associated with the formation of the nanoclusters may be sufficient to allow the nanoclusters to obtain the equilibrium shape illustrated in FIG. 10. If the time period is not sufficient, a similar annealing step may be utilized to promote the transition to the equilibrium configuration.
  • a desirable size of nanoclusters for use in semiconductor memory structures may be between 30 and 70 angstroms, and in some embodiments a target diameter of 50 angstroms may be appropriate.
  • a density of greater than 5x10 11 nanoclusters per centimeter 2 can be achieved using the formation techniques described herein.
  • the coverage, or area density of the nanoclusters on the underlying tunnel dielectric layer may be approximately 20%.
  • the 20% area density is reasonable for semiconductor device manufacturing, as it provides a level of tolerance in the spacing between the nanoclusters included in the floating gate structures.
  • higher area densities may be achieved, the proximity of the isolated storage elements in such higher area density embodiments may increase the probability of lateral charge transfer between nanoclusters, thus degrading the beneficial effects of their isolation.
  • FIG. 11 illustrates a cross-sectional view of the semiconductor substrate portion 10 of FIG. 10 upon which a control dielectric layer 20 has been formed.
  • the control dielectric layer 20 overlies the nanoclusters 21 and the tunnel dielectric layer 14.
  • the control dielectric layer 20 may be deposited using CVD, sputtering, or other deposition steps commonly used in semiconductor processing operations.
  • the material included in the control dielectric layer 20 may be oxide-nitride-oxide (ONO), silicon oxide, or metal oxide.
  • ONO oxide-nitride-oxide
  • each of the nanoclusters 21 may be encapsulated in order to prevent oxidation as described with respect to FIGs. 21-27 below.
  • FIG. 12 illustrates a cross-sectional view of the portion of the semiconductor substrate 10 of FIG. 11 where a conductive layer 22 has been deposited over the control dielectric layer 20.
  • the conductive layer 22 is preferably a gate material such as doped polysilicon or metal. Deposition of the conductive layer 22 may be accomplished using CVD or other techniques commonly used to deposit such gate materials.
  • FIG. 13 illustrates a cross-sectional view of the semiconductor substrate portion 10 of FIG. 9 where a portion of the conductive layer 22 has been removed to form a gate, or gate electrode 24. Formation of the gate electrode 24 defines a channel region in the semiconductor layer 12 that underlies the gate electrode 24. Etching of the conductive layer 22 to form the gate electrode 24 may be accomplished using a reactive ion etch.
  • FIG. 14 illustrates a cross-sectional view of the semiconductor substrate portion 10 of FIG. 10 where a portion of the control dielectric layer 20 has been etched to form an etched control dielectric layer 26.
  • the portion of the control dielectric layer 20 that is removed to form the etched control dielectric layer 26 is the portion that lies adjacent to (not below) the gate electrode 24.
  • the portion of the control dielectric layer 20 that underlies the gate electrode 24 is not etched.
  • Such etching may be performed using reactive ion etching (RIE).
  • FIG. 15 illustrates a cross-sectional view of the substrate portion 10 of FIG. 14 where a portion of the plurality of nanoclusters 21 have been reacted to form a compound that has subsequently been removed through etching operations.
  • the portion that is reacted is the portion that underlies the portion of the control dielectric layer 20 that was etched away to produce the etched control dielectric layer 26 illustrated in FIG. 14.
  • the portion of the plurality of nanoclusters 21 that underlies the gate electrode 24 is generally unaffected by the reacting operation.
  • Reacting may include reacting with oxygen, which creates silicon oxide in the case of silicon nanoclusters.
  • the reacted portion may be removed along with a corresponding portion of the tunnel and control dielectric layers 14 and 26 using an etching operation.
  • the etching operation may be a non-selective wet etch operation.
  • reacting a portion of the plurality of nanoclusters may include reacting those nanoclusters with oxygen to form silicon oxide.
  • the tunnel and control dielectric layers 14 and 26 are silicon oxide, a wet etch operation utilizing dilute hydrofluoric acid will achieve the desired results. What is shown to remain in the cross-sectional view of FIG. 15 is the gate electrode 24, a selected portion of the control dielectric layer 28, a portion of the nanoclusters 21 , and a selected portion of the tunnel dielectric layer 30, all of which underlie the gate electrode 24.
  • FIG. 16 illustrates a cross-sectional view of the semiconductor substrate 10 of FIG. 15 where spacers 35 and source and drain regions 32 and 34 have been formed to form a transistor structure (or at least a major portion thereof).
  • the source and drain regions 32 and 34 may be formed through implantation of dopant materials in the semiconductor layer 12. Formation of the source and drain regions 32 and 34 results in the formation of the channel region that lies beneath the gate electrode 24 between the source and drain regions 32 and 34.
  • Such a transistor structure may be produced to include field isolation regions (not shown) to isolate the transistor for neighboring devices.
  • Transistors such as that shown in FIG. 16 may be utilized in semiconductor memory structures such as flash memories, EEPROM memories, DRAM memories, or other memory structures of varying volatility.
  • semiconductor memory structures such as flash memories, EEPROM memories, DRAM memories, or other memory structures of varying volatility.
  • such a transistor structure may be useful in the production of flash memory structures that require charge retention characteristics such that the state of the transistor can be maintained for a time period on the order of years.
  • the initial growth or deposition of nanoclusters can be controlled such that few or none of the nanoclusters need to be reacted and etched away.
  • manufacturing efficiency can be improved.
  • preferable growth regions can be formed on the tunnel dielectric layer 14. Such preferable growth regions correspond to areas on the tunnel dielectric layer 14 where surface modifications have been performed to facilitate nucleation of nanoclusters.
  • nitrogen-containing sections can be formed over different portions of the tunnel dielectric layer 14 where the nitrogen-containing sections promote higher nanocluster nucleation and growth. Due to the difference in incubation time associated with nanocluster development on nitrogen- containing material and the incubation time associated with the tunnel dielectric materials such as silicon dioxide, nanocluster nucleation and growth will preferentially occur on those nitrogen-containing sections overlying the tunnel dielectric layer 14.
  • FIGs. 17-20 illustrate cross-sectional views of the portion of the semiconductor substrate 10 corresponding to different steps in the selective formation of nanoclusters overlying the tunnel dielectric layer 14.
  • FIG. 17 illustrates the portion of the semiconductor substrate 10 as illustrated in FIG. 3 following growth of a masking layer 520, which may be photoresist.
  • FIG. 18 illustrates a cross-sectional view of the portion of the semiconductor substrate 10 of FIG. 17 following a subsequent step during which the masking layer 520 is patterned to form a patterned masking layer 522.
  • the patterning can be achieved by lithographic exposure of the photoresist followed by a lift-off operation. As such, a remaining portion 522 of the masking layer remains overlying the portion of the tunnel dielectric layer 14 corresponding to the area in which nanocluster growth is desired. Thus, masked and unmasked portions of the nitrogen-containing layer 502 remain after removal of the portion of the masking layer 520.
  • FIG. 19 illustrates a cross-sectional view of the semiconductor substrate portion 10 of FIG. 18 following subsequent processing steps where the remaining portion 522 of the masking layer has been removed along with those unmasked portions of the nitrogen containing layer 502 (those portions not underlying the remaining portion 522 of the masking layer, which are considered the masked portions).
  • the portion of the semiconductor substrate as illustrated in FIG. 18 may be anisotropically etched to first remove the unmasked portion of the nitrogen-containing layer that does not underlie the portion of the masking layer 522, and then the remaining portion 522 of the masking layer can also be removed to produce the resulting structure illustrated in FIG. 19.
  • a nitrogen-containing layer section 524 (masked portion of the nitrogen-containing layer) that corresponds to a location on the tunnel dielectric 14 where nanocluster growth is desired. Those portions of the tunnel dielectric 14 that do not have overlying nitrogen- containing layer sections correspond to areas where nanocluster growth is not desired.
  • FIG. 20 illustrates the selective growth of nanoclusters on the structure illustrated in FIG. 19.
  • nanoclusters will preferentially grow on the nitrogen-containing layer section 524 such that a number of nanoclusters 521 will be formed thereon.
  • the tunnel dielectric layer 14 due to the difference in incubation periods and less reactive nature of the tunnel dielectric layer 14, only a fractional set of corresponding nanoclusters 532 will be formed directly on the tunnel dielectric 514.
  • the operations are performed to remove the nanoclusters not underlying the gate region of the device, the number of nanoclusters that must be reacted and removed through etching operations is greatly reduced.
  • FIG. 21 illustrates an expanded cross-sectional view of a plurality of nanoclusters 103 as formed on a tunnel dielectric layer 102.
  • the substrate 100 may be exposed to ambient conditions. Such exposure to ambient conditions may result in oxidation of the nanoclusters 103 which in turn may result in a number of undesirable effects.
  • One undesirable effect concerns the reduction in the effective size of the nanoclusters through the consumption of silicon or other composition materials during such oxidation. As a result, if too much oxidation occurs, the resulting size of the nanoclusters may be such that they are incapable of storing charge in the manner required to allow them to effectively function as charge storage elements.
  • Smaller nanoclusters are less receptive to charge carriers due to reduced cross-sectional area as well as other factors. As such, higher programming voltages, longer programming times, and less effective programming may result from smaller nanoclusters that are less than 25 angstroms in diameter.
  • oxidation involves the increase in thickness of the tunnel dielectric layer 102, which can occur due to oxidation of either the nanoclusters 103 or the underlying substrate 100. Specifically, oxidation may occur at the interface between the nanoclusters 103 and the tunnel dielectric layer
  • tunnel dielectric layer 102 is often formed of silicon oxide, and oxidation of silicon nanoclusters will result in additional silicon oxide, this effectively increases the thickness of the tunnel dielectric layer 102. Such an increase in thickness is undesirable as it can affect the overall electrical characteristics of the semiconductor device that includes the nanoclusters 103.
  • FIG. 22 illustrates the nanoclusters as shown in FIG. 21 following a subsequent processing step that reconfigures the general shape of the nanoclusters 103 to form generally hemispherical nanoclusters 104.
  • This alteration in nanocluster shape can be produced by an annealing step or other operations that allow the atoms in the nanoclusters to move to equilibrium with the underlying tunnel dielectric layer 102. Such a step was also described above with respect to FIG. 10.
  • the resulting generally hemispherical nanoclusters 104 have a reduced amount of surface area that may be exposed to ambient conditions during subsequent processing steps. Furthermore, the diffusion of oxygen to portions of the nanoclusters 104 are in contact with the underlying tunnel dielectric 102 is reduced so that problems associated with increased tunnel dielectric thickness are generally avoided.
  • a further benefit of the generally-hemispherical nanoclusters 104 shown in FIG. 22 may be realized based on the increased surface area of the generally-hemispherical nanoclusters 104 in contact with the tunnel dielectric layer 102.
  • the generally- hemispherical nanoclusters 104 provide an increased cross-sectional area for capturing charge carriers received from the underlying channel region of the device during programming operations'.
  • FIG. 23 illustrates the nanocluster structures of FIG. 22 following an encapsulation step.
  • the encapsulation step forms an encapsulation layer 106 on each of the nanoclusters 104.
  • Such an encapsulation layer 106 may be formed of silicon nitride.
  • Silicon nitride may be formed on the surface of the nanoclusters 104 by exposing the nanoclusters 104 to a nitriding ambient at high temperature.
  • Such an ambient may include ammonia, nitrous oxide, or other nitrogen-containing compounds that are reactive to silicon in a manner that can be controlled.
  • a thin layer of nitride is formed on the nanoclusters by flowing ammonia, without other reactants, over the nanoclusters.
  • the conditions under which the ammonia may be flowed may include a temperature within a typical range of 700-1000 degrees Celsius and a pressure within a typical range of 1 -760 Torr.
  • the formation of the encapsulation layer 106 can be controlled such that the thickness of the encapsulation layer 106 is on the order of 5 angstroms, or no greater than 10% of the diameter of the nanoclusters 104.
  • the nitriding process used to create the encapsulating layer 106 is typically self-limiting.
  • the maximum growth of silicon nitride on the silicon nanoclusters 104 may be self-limited with respect to the temperature of nitridation.
  • the nitriding ambient used for forming the encapsulation layer 106 does not affect the underlying tunnel dielectric layer 102 in a significant manner. As such, the nitriding step utilized to form the encapsulation layer 106 will not result in nitridation of the underlying tunnel dielectric layer 102. As such, traps that may be generated within the encapsulation layer 106 are isolated from the underlying substrate 100 as well as from the encapsulation layers of neighboring nanoclusters. As such, trap assisted leakage between the nanoclusters is less likely to occur. This lack of degradation of charges stored in the traps may actually enhance the charge storage characteristics of the nanoclusters 104.
  • FIG. 24 illustrates the portion of the semiconductor substrate of FIG. 23 following deposition of the control dielectric layer 108.
  • the formation of the control dielectric layer 108 could result in oxidizing ambient exposure of the nanoclusters 104 such that oxidation occurs.
  • oxidation or other degradation due to oxidizing ambient exposure of the nanoclusters 104 can be reduced or eliminated. As such, the diameter of the nanoclusters 104 is maintained, and no uncontrolled increase in the underlying tunnel dielectric occurs.
  • a protecting nitride layer may be deposited rather than grown on individual nanoclusters.
  • FIG. 25 illustrates the nanocluster structures as shown in FIG. 22 following a step where a thin nitride layer 107 is deposited.
  • the nitride layer 107 may be deposited using CVD operations that utilize ammonia and dichlorosilane. Such CVD operations may be performed using LPCVD or UHVCVD techniques.
  • the deposition of the thin nitride layer 107 is preferably controlled such that the thickness of the thin nitride layer 107 is limited.
  • a desirable thickness for the thin nitride layer 107 may be on the order of 5 angstroms. Such a limited thickness of nitride may limit or eliminate the potential for traps that may degrade the charge storage characteristics of semiconductor device being manufactured.
  • the thin nitride layer 107 illustrated in FIG. 25 forms a barrier to oxygen such that both the nanoclusters 104 and the underlying semiconductor substrate 100 below the tunnel dielectric layer 102 are protected from oxidation. As such, the potential for an increase in the thickness of the tunnel dielectric layer 102 is reduced.
  • FIG. 26 illustrates the portion of the semiconductor substrate of
  • FIG. 25 following the formation of the control dielectric layer 108.
  • the thin dielectric layer 107 prevents oxidation of the nanoclusters 104 and may also serve to eliminate the potential for uncontrolled increase of the thickness of the tunnel dielectric 102.
  • control dielectric layer 108 may be formed of a high dielectric (high K) material that does not require high concentrations of oxygen for formation. As such, oxidation of the nanoclusters is less likely to occur. Control dielectrics that include metal oxide do not require the high concentrations of oxygen for growth that silicon oxide control dielectrics require. As such, there is less likelihood of degradation of the nanocluster structures.
  • the high dielectric constants associated with metal oxide also serve to reduce the required programming voltages in comparison with silicon oxide control dielectrics. Metal oxides such as zirconium oxide, hafnium oxide, zirconium silicate, hafnium silicate, lanthanum aluminate, alumina, and strontium titanate may be used as the control dielectric.
  • FIG. 27 illustrates the semiconductor substrate portion of FIG. 22 following such processing steps.
  • a thin layer of high-quality silicon oxide 112 is formed over the nanoclusters 104 and underlying tunnel dielectric 102.
  • Deposition of the thin high quality silicon oxide layer 112 may result in a small amount of oxidation of the nanoclusters 104.
  • the thickness of the thin layer of high-quality silicon oxide layer 112 is preferably limited such that the time required for such deposition is limited. Because the time period for the deposition is limited, the degradation of the nanoclusters 104 is also limited to a tolerable amount.
  • the thin layer of high-quality silicon oxide 112 is formed to be approximately 13 angstroms thick.
  • a silicon-rich silicon oxide layer 114 is formed overlying the thin layer of high-quality silicon oxide 112.
  • the silicon-rich silicon oxide layer 114 includes silicon atoms that may readily bond with oxygen atoms introduced through exposure to oxidizing conditions. As such, oxygen atoms attempting to migrate through the silicon-rich silicon oxide layer 114 and combine with silicon atoms in the nanoclusters 104 are captured by the silicon atoms, thus preventing degradation of the nanoclusters 104 as well as the underlying semiconductor substrate material 100.
  • the silicon-rich silicon oxide layer 114 includes approximately 1% to 2% non-stoichiometric silicon (excess silicon).
  • the thickness of the silicon-rich silicon oxide layer 114 may be on the order of 20-25 angstroms. It should be noted that this thickness can be altered in order to provide adequate protection for the underlying nanoclusters 104 based on the ambient to which the substrate may be exposed.
  • the thickness of the silicon-rich silicon oxide layer 114 may be determined based on the potential oxidation that may occur during subsequent processing steps as well as the amount of excess silicon included within the material used to form the silicon-rich silicon oxide layer 114. Thus, a trade off exists between the concentration of excess silicon within this layer and the degree of oxidation expected to occur during subsequent processing steps. It is desirable to ensure that the majority of the excess silicon within the silicon rich silicon oxide layer 114 combines with oxygen atoms to ensure that the conductive qualities of the silicon rich silicon oxide layer 114 are eliminated. Following deposition of the silicon-rich silicon oxide layer 114, the remainder of the control dielectric layer can be formed through the growth of an additional high-quality silicon oxide layer 116 overlying the previously formed layers.
  • overlying high-quality silicon oxide layer 116 typically exposes the remaining portions of the structure to ambient conditions. However, as stated above, the silicon-rich silicon oxide layer 114 helps to prevent the oxidation of the nanoclusters 104 during such ambient exposure.
  • the overlying high-quality silicon oxide layer 116 may be formed through CVD operations such as those described for other deposition steps above.
  • the thickness of the overlying high-quality silicon oxide layer 116 may be on the order of 65 angstroms, or may be determined in order to provide a total control dielectric layer thickness of approximately 100 angstroms.
  • the encapsulation technique described with respect to FIGs. 23 and 24, the protective layer technique described with respect to FIGs 25 and 26, the technique for inclusion of a silicon-rich oxide layer as described with respect to FIG. 27, and the use of alternate control gate dielectrics such as metal oxides may be used in conjunction with nanoclusters that are both spherical or hemispherical.
  • FIGs. illustrate encapsulation, layering, etc. with respect to generally-hemispherical nanoclusters, it is apparent to one of ordinary skill in the art that such techniques would also benefit spherical nanoclusters or nanoclusters of other shapes.
  • various combinations of the techniques described above may be useful in protecting the nanoclusters and underlying substrate from degradation resulting from exposure to oxidizing or other ambient conditions.
  • the formation of the tunnel dielectric layer, the nanoclusters, and the control dielectric layer may all be accomplished within a controlled environment that does not expose the substrate wafer to ambient conditions during and between these processing steps.
  • a controlled environment is schematically illustrated in FIG. 28, which may represent a cluster tool.
  • a dielectric module 208 may be used for growth or deposition of the tunnel dielectric layer and also for formation of the control dielectric layer following formation of the nanoclusters on the surface of the tunnel dielectric layer.
  • the dielectric module 208 is included in an isolated area 210 along with the module 206 that controls the CVD of the nanoclusters.
  • the isolated area 210 provides a controlled environment, such as a near vacuum environment, and the transfer of the semiconductor substrate wafers between the dielectric module 208 and the CVD module 206 occurs without exposure to ambient conditions.
  • the substrate upon which the nanoclusters are formed is continuously within the controlled environment of the cluster tool from the step of forming the tunnel dielectric until after the step of forming the nanoclusters.
  • preventing the tunnel dielectric layer from exposure to ambient conditions reduces the chance of contaminants forming on the tunnel dielectric layer. Such contaminants can adversely affect the nucleation and growth of nanoclusters, and therefore any reduction in such contaminants is highly desirable.
  • a control module 204 controls the dielectric growth within the dielectric module 208 and the nanocluster growth within the nanocluster growth module 206.
  • Such control may include regulation of source gases 202 and 212 such that desired flow rates and pressures are achieved.
  • Other control may include regulation of temperature within the isolated area 210.
  • the present invention provides techniques useful in forming nanocluster structures using LPCVD and UHCVCD deposition techniques. Utilization of the techniques described herein allows for high densities of nanoclusters to be achieved while maintaining process controllability. Such controllability allows the size, distribution, and general uniformity of the nanoclusters to be closely regulated such that the desired electrical characteristics for devices that include nanocluster floating gate structures can be achieved. As such, devices can be produced that include very thin tunnel dielectric layers such that low-power and high-speed operation can be achieved.

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Abstract

La présente invention concerne un dispositif mémoire à semi-conducteur doté d'une grille flottante qui comporte une pluralité de nano-amas (21), ainsi que des techniques utiles pour la fabrication dudit dispositif. Selon ledit procédé, une couche diélectrique à effet tunnel (14) est formée sur un substrat semi-conducteur (12). Une pluralité de nano-amas (19) est ensuite amenée à croître sur la couche diélectrique à effet tunnel (14). Cette croissance est facilité par la formation d'une couche contenant de l'azote (502), qui peut être du nitrure, destinée à couvrir la couche diélectrique à effet tunnel (14). Des parties sélectionnées de la couche contenant de l'azote (502) peuvent être éliminées pour permettre un meilleur contrôle des sites où les nano-amas sont formés. La croissance des nano-amas peut également être facilitée par traitement de la surface de la couche diélectrique à effet tunnel (14) pour modifier la structure de liaison de ladite couche (14). Après formation des nano-amas (21), un couche diélectrique de commande (20) est formée sur lesdits nano-amas (21). Une électrode (24) de grille est ensuite formée sur le diélectrique de commande. Puis des parties de la couche diélectrique de commande (20), de la pluralité de nano-amas et du diélectrique de grille qui ne se trouvent pas sous l'électrode de grille sont sélectivement éliminées. Après formation des éléments d'écartement (35), des régions de source et de drain (32, 34) sont formées par implantation dans la couche de semi-conducteur (12) de manière qu'une région de canal soit formée entre les régions de source et de drain (32, 34) se trouvant sous l'électrode (24) de grille.
PCT/US2001/016585 2000-06-16 2001-05-23 Dispositif memoire comportant des nano-amas et procede de fabrication dudit dispositif Ceased WO2001099167A2 (fr)

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CN100343979C (zh) * 2004-03-04 2007-10-17 三星电子株式会社 包括有均匀分布的硅纳米点的栅的存储器的制造方法
EP1844492A4 (fr) * 2005-01-26 2009-10-21 Freescale Semiconductor Inc Memoire non volatile a nanocristaux et procede associe
WO2010023575A1 (fr) * 2008-08-26 2010-03-04 Nxp B.V. Condensateur et procédé de fabrication

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US6060743A (en) * 1997-05-21 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same
JP3495889B2 (ja) * 1997-10-03 2004-02-09 シャープ株式会社 半導体記憶素子
US6232643B1 (en) * 1997-11-13 2001-05-15 Micron Technology, Inc. Memory using insulator traps
JP4538693B2 (ja) * 1998-01-26 2010-09-08 ソニー株式会社 メモリ素子およびその製造方法
JP3769120B2 (ja) * 1998-05-08 2006-04-19 株式会社東芝 半導体素子

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100343979C (zh) * 2004-03-04 2007-10-17 三星电子株式会社 包括有均匀分布的硅纳米点的栅的存储器的制造方法
EP1844492A4 (fr) * 2005-01-26 2009-10-21 Freescale Semiconductor Inc Memoire non volatile a nanocristaux et procede associe
WO2010023575A1 (fr) * 2008-08-26 2010-03-04 Nxp B.V. Condensateur et procédé de fabrication
CN102132367B (zh) * 2008-08-26 2012-07-25 Nxp股份有限公司 电容器及其制造方法
US8697516B2 (en) 2008-08-26 2014-04-15 Nxp, B.V. Capacitor and a method of manufacturing the same

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