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WO2000063958A1 - Depot in situ avec environnement controle d'ono destine a l'application a la memoire flash eprom - Google Patents

Depot in situ avec environnement controle d'ono destine a l'application a la memoire flash eprom Download PDF

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Publication number
WO2000063958A1
WO2000063958A1 PCT/US2000/009724 US0009724W WO0063958A1 WO 2000063958 A1 WO2000063958 A1 WO 2000063958A1 US 0009724 W US0009724 W US 0009724W WO 0063958 A1 WO0063958 A1 WO 0063958A1
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WO
WIPO (PCT)
Prior art keywords
layer
silicon
oxide
silicon dioxide
angstroms
Prior art date
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Ceased
Application number
PCT/US2000/009724
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English (en)
Inventor
Robert Bertram Ogle, Jr.
Arvind Halliyal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of WO2000063958A1 publication Critical patent/WO2000063958A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Definitions

  • This invention pertains to integrated circuit manufacturing technology, and in particular to an improved process and product produced therefrom for forming an interpoly dielectric for Flash EPROM.
  • Flash EPROM' s Erasable Programmable Read-Only Memory
  • Flash EPROM's are a type of programmable memory cell, wherein channel conductivity of a transistor therein may be maintained at one of two levels, corresponding to two binary states.
  • the contents of all of the memory's array cells can be simultaneously and rapidly erased through the use of an electrical erase signal.
  • Flash EPROM 's utilize a floating gate which retains charge until discharged through an erase process wherein the erasing mechanism is Fowler-Nordheim tunneling from the floating gate to the drain region. Flash EPROM 's offer high density, low cost, and easy erasability.
  • the basic structure of a Flash EPROM is shown in Figure la and Figure lb.
  • the floating gate 2 (generally polysilicon) is separated from substrate 4 by gate oxide 6.
  • Composite interpoly dielectric layer 8 which may be composed of an Oxide-Nitride-Oxide (ONO) sandwich, separates floating gate 2 from control gate 10, also generally polysilicon.
  • the interpoly layer must have a sufficiently high breakdown voltage to provide for effective charge retention, i.e., to prevent charge loss from the floating gate at all times other than during an erase cycle.
  • the interpoly dielectric breakdown voltage must be high enough so that Fowler-Nordheim tunneling from floating gate to control gate is blocked when the control gate has 12 - 20 volts applied thereto.
  • the effective thickness of the ONO composite layer i.e., the thickness of an oxide layer having equivalent capacitance
  • the interpoly dielectric layer Capacitative coupling between the control electrode and the floating gate electrode is improved with thinner interpoly dielectric thickness, thereby improving transistor speed and performance.
  • the scaling of the interpoly dielectric thickness has in the past been limited by an increase of leakage current and the resultant lowering of the dielectric breakdown voltage, both of which reduce the Flash EPROM device yield for thinner dielectric layers.
  • a method for providing interpoly dielectric layers with effective thickness below 130 Angstroms without lowering device yield would be desirable for scaling down of Flash EPROMs.
  • the same method would also be useful for other EPROM-related technologies such as EEPROM's, and any other technologies which utilize the ONO interpoly dielectric layer.
  • Fig. la shows the gate region of a prior art Flash EPROM cell.
  • Fig. lb shows an expanded view of the gate and dielectric region of the cell of Fig. la.
  • Fig. 2 is a schematic drawing of the cluster deposition system used in the experiments described herein.
  • Fig. 3 shows the gate and dielectric region of a Flash EPROM cell having the inventive structure and made by the inventive process.
  • Figure la shows the configuration of the gate region of an embodiment of a Flash EPROM cell, which is known in the art.
  • the floating polysilicon gate 2 is separated from substrate 4 by gate oxide 6.
  • Figure lb is an expanded view of the gate and dielectric region of the cell of Figure la.
  • ONO composite layer is comprised of a bottom silicon dioxide layer 14 atop floating gate 2, silicon nitride layer 16 atop oxide layer 14, and top silicon dioxide layer 18 atop nitride layer 16.
  • Control gate 10 is shown atop oxide layer 18.
  • bottom oxide layer 14 is generally formed by Low Pressure Chemical Vapor Deposition (LPCVD) in a high throughput batch oxide deposition chamber, and has a thickness of approximately 50 - 60 Angstroms.
  • Silicon nitride layer 16 is also generally LPCVD, is deposited in a separate nitride deposition chamber, and has a thickness of approximately 100 Angstroms (with an equivalent oxide thickness of approximately 50 Angstroms).
  • Top oxide layer 18 is generally LPCVD or thermally formed by partial oxidation of nitride, and has a thickness of approximately 40 - 50 Angstroms.
  • the problem of organic residue on the surface of the bottom oxide layer in the ONO structure is recognized as being a limiting factor in the ability to successfully scale down interpoly dielectric thickness in Flash EPROM 's while maintaining device yield, and the problem is solved by utilizing a cluster deposition system to deposit the bottom two, or alternately all three, layers of the ONO film without return to the atmospheric environment, so as to essentially eliminate this organic residue.
  • Figure 2 shows a schematic drawing of a cluster deposition system, which was used in the experiments described herein. A single wafer enters evacuated region 20 through load lock 22 and is transferred through transfer chamber 23 into oxide deposition chamber 24 or nitride deposition chamber 26.
  • the top oxide is either deposited in the same cluster tool, or thermally grown in a separate batch furnace. Better results have been obtained with thermally grown top oxide, by partial oxidation of the nitride layer.
  • Figure 3 shows the gate and dielectric region of a Flash EPROM cell formed using the inventive method. There is no measurable organic residue 19 atop bottom oxide layer 14.
  • Table 1 shows experimental results from Flash EPROM devices fabricated using the standard batch process for the ONO layer, wherein separate nitride and oxide deposition chambers are utilized, compared with Flash EPROM devices fabricated using the inventive process for the ONO layer, wherein the nitride and bottom oxide layers are deposited in the vacuum environment of the cluster chamber.
  • the wafers fabricated using the standard process will be hereinafter referred to as the control wafers. Wafer # Process Equiv. Oxide thickness (A)
  • the standard ONO deposition process for the control wafers comprises: 1) 50-60 Angstroms LPCVD oxide deposited atop the floating poly gate, using a conventional batch oxide deposition system;
  • the equivalent oxide thickness for the conventionally prepared ONO layer on the control wafers, as measured by capacitance-voltage (CV) tests is approximately 140 - 150 Angstroms.
  • the inventive ONO deposition process for the experimental wafers comprises:
  • RTCVD Rapid Thermal CVD oxide
  • the process chamber is brought to a pressure of 50 Torr and a mixture of dichlorosilane (DCS) and nitrous oxide (N20) is flowed into the process chamber with nitrogen carrier gas while the temperature is ramped to 750C.
  • the target oxide thickness is achieved by controlling the duration of deposition, ranging between 20 and 60 seconds. The pressure and temperature remain constant during the deposition process.
  • the process chamber is brought to a pressure of 100 Torr and a mixture of dicholorosilane and ammonia (NH3) is flowed into the process chamber with nitrogen carrier gas while the temperature is ramped to 750C.
  • NH3 dicholorosilane and ammonia
  • the target nitride thickness is achieved by controlling the duration of deposition, ranging between 50 and 100 seconds. The pressure and temperature remain constant during the deposition process.
  • the equivalent oxide thickness for the ONO layer on the experimental wafers as measured by CV tests ranges between 115 and 132 Angstroms.
  • Flash EPROM yield data for the control vs the experimental wafers shows comparable results for the two. There is no indication of lower yield for the experimental wafers with equivalent thickness at the thinner end of this range. It is believed that the improvement in results for the Flash EPROM devices fabricated using the inventive method are due to the large decrease in organic residue on the bottom oxide layer of the ONO. It is expected that a minimum of a monolayer of organic materials are adsorbed onto the bottom oxide surface in the conventionally prepared ONO structure, whereas the residual layer is less than a monolayer for the ONO structure prepared in the cluster chamber according to the inventive process.
  • an improved device is produced having essentially no measurable organic residue between the ONO layers.
  • the resultant lowering of leakage current through the interpoly dielectric improves charge retention and allows the device yield to be maintained for thinner interpoly dielectric layers.
  • Scaling of the ONO to smaller thickness improves capacitative coupling between the control gate and the floating gate, thereby improving the speed and performance of the Flash EPROM device.
  • the invention be restricted to the exact embodiments described herein.
  • the exact parameters of the oxide and nitride layer depositions may differ, or the type of cluster deposition chamber may vary, without altering the inventive concept.
  • the oxide and nitride depositions could also be performed in a nitrogen ambient introduced following evacuation of the cluster system deposition chamber.
  • the scope of the invention should be construed in view of the claims.

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé de fabrication de circuit intégré et le produit formé au moyen de ce procédé destiné à un diélectrique interpoly utilisé dans des dispositifs mémoire à grille flottante tels que Flash EPROM, le procédé permettant de réduire l'épaisseur du diélectrique sans diminuer le rendement. L'utilisation d'un système de dépôt en grappes pour les couches ONO du diélectrique interpoly réduit la quantité de résidu à base de carbone sur les couches diélectriques et abaisse le courant de fuite.
PCT/US2000/009724 1999-04-16 2000-04-11 Depot in situ avec environnement controle d'ono destine a l'application a la memoire flash eprom Ceased WO2000063958A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US29335499A 1999-04-16 1999-04-16
US09/293,354 1999-04-16

Publications (1)

Publication Number Publication Date
WO2000063958A1 true WO2000063958A1 (fr) 2000-10-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/009724 Ceased WO2000063958A1 (fr) 1999-04-16 2000-04-11 Depot in situ avec environnement controle d'ono destine a l'application a la memoire flash eprom

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2061243A (en) * 1979-09-12 1981-05-13 Philips Electronic Associated Method of making semiconductor devices
US4438157A (en) * 1980-12-05 1984-03-20 Ncr Corporation Process for forming MNOS dual dielectric structure
US5104819A (en) * 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
US5619052A (en) * 1994-09-29 1997-04-08 Macronix International Co., Ltd. Interpoly dielectric structure in EEPROM device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2061243A (en) * 1979-09-12 1981-05-13 Philips Electronic Associated Method of making semiconductor devices
US4438157A (en) * 1980-12-05 1984-03-20 Ncr Corporation Process for forming MNOS dual dielectric structure
US5104819A (en) * 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
US5619052A (en) * 1994-09-29 1997-04-08 Macronix International Co., Ltd. Interpoly dielectric structure in EEPROM device

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