[go: up one dir, main page]

WO2000065440A3 - Exception handling method and apparatus for use in program code conversion - Google Patents

Exception handling method and apparatus for use in program code conversion Download PDF

Info

Publication number
WO2000065440A3
WO2000065440A3 PCT/GB2000/001439 GB0001439W WO0065440A3 WO 2000065440 A3 WO2000065440 A3 WO 2000065440A3 GB 0001439 W GB0001439 W GB 0001439W WO 0065440 A3 WO0065440 A3 WO 0065440A3
Authority
WO
WIPO (PCT)
Prior art keywords
registers
section
subject
code
reg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB2000/001439
Other languages
French (fr)
Other versions
WO2000065440A2 (en
Inventor
Alasdair Rawsthorne
John Harold Sandham
Jason Souloglou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Manchester
Original Assignee
Victoria University of Manchester
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB9909615A external-priority patent/GB2349486B/en
Application filed by Victoria University of Manchester filed Critical Victoria University of Manchester
Priority to AU45803/00A priority Critical patent/AU4580300A/en
Priority to JP2000614118A priority patent/JP4709394B2/en
Priority to EP00927395A priority patent/EP1183601A2/en
Publication of WO2000065440A2 publication Critical patent/WO2000065440A2/en
Publication of WO2000065440A3 publication Critical patent/WO2000065440A3/en
Priority to US09/827,970 priority patent/US7353163B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

A method of handling exceptions for use in an emulator (20) performing program code conversion. Registers (X) of a subject machine (11) being emulated (20) are represented by a pair of abstract registers (XA, XB) on the target machine (31), suitably using memory locations of the target machine and/or any available target registers. One of the pair (e.g., Reg XA) holds a definitive value at entry into a section (100) of subject code (10) whilst the other (e.g., Reg XB) holds a speculative value which is updated during translation and execution of that section of code. Exceptions are handled by recovering the conditions of the virtual subject machine (11) upon entry into the section of subject code (100) using the definitive version of each abstract register (i.e., Reg XA). Advantageously, the function of the pair of registers (XA, XB) is alternated upon successful completion of each section of subject code (100) such that a definitive version of each register is always available for exception handling whilst avoiding time consuming copy and storing operations.
PCT/GB2000/001439 1999-04-27 2000-04-26 Exception handling method and apparatus for use in program code conversion Ceased WO2000065440A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU45803/00A AU4580300A (en) 1999-04-27 2000-04-26 Exception handling method and apparatus for use in program code conversion
JP2000614118A JP4709394B2 (en) 1999-04-27 2000-04-26 Method and apparatus for exception handling used in program code conversion
EP00927395A EP1183601A2 (en) 1999-04-27 2000-04-26 Exception handling method and apparatus for use in program code conversion
US09/827,970 US7353163B2 (en) 1999-04-27 2001-04-06 Exception handling method and apparatus for use in program code conversion

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US29975199A 1999-04-27 1999-04-27
GB9909615.8 1999-04-27
GB9909615A GB2349486B (en) 1999-04-27 1999-04-27 Exception handling in program code conversion.
US09/299,751 1999-04-27

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US09/827,970 Continuation US7353163B2 (en) 1999-04-27 2001-04-06 Exception handling method and apparatus for use in program code conversion
US09/827,970 Continuation-In-Part US7353163B2 (en) 1999-04-27 2001-04-06 Exception handling method and apparatus for use in program code conversion

Publications (2)

Publication Number Publication Date
WO2000065440A2 WO2000065440A2 (en) 2000-11-02
WO2000065440A3 true WO2000065440A3 (en) 2001-01-25

Family

ID=26315473

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2000/001439 Ceased WO2000065440A2 (en) 1999-04-27 2000-04-26 Exception handling method and apparatus for use in program code conversion

Country Status (4)

Country Link
EP (1) EP1183601A2 (en)
JP (1) JP4709394B2 (en)
AU (1) AU4580300A (en)
WO (1) WO2000065440A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002042898A2 (en) * 2000-11-20 2002-05-30 Zucotto Wireless, Inc. Interpretation loop for object oriented processor
GB2411990B (en) * 2003-05-02 2005-11-09 Transitive Ltd Improved architecture for generating intermediate representations for program code conversion
GB0315844D0 (en) * 2003-07-04 2003-08-13 Transitive Ltd Method and apparatus for performing adjustable precision exception handling
US7480902B2 (en) * 2004-07-08 2009-01-20 Intel Corporation Unwind information for optimized programs
JP5448165B2 (en) * 2006-10-02 2014-03-19 インターナショナル・ビジネス・マシーンズ・コーポレーション Computer system adapted to support register window architecture, method of controlling the computer system, and computer program thereof
JP5115332B2 (en) 2008-05-22 2013-01-09 富士通株式会社 Emulation program, emulation device, and emulation method
CN102141929B (en) * 2010-10-21 2014-05-07 华为技术有限公司 Application program running method, simulator, host machine and system
WO2014043886A1 (en) * 2012-09-21 2014-03-27 Intel Corporation Methods and systems for performing a binary translation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0285310A2 (en) * 1987-03-31 1988-10-05 Kabushiki Kaisha Toshiba Device for saving and restoring register information
WO1998059292A1 (en) * 1997-06-25 1998-12-30 Transmeta Corporation Improved microprocessor
US5872950A (en) * 1997-03-31 1999-02-16 International Business Machines Corporation Method and apparatus for managing register renaming including a wraparound array and an indication of rename entry ages

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63156236A (en) * 1986-12-19 1988-06-29 Toshiba Corp Register device
JP2707867B2 (en) * 1991-04-25 1998-02-04 富士ゼロックス株式会社 Register file of digital computer and instruction execution method using it.
JP3302706B2 (en) * 1991-05-31 2002-07-15 日本電気株式会社 Storage device
JPH06180653A (en) * 1992-10-02 1994-06-28 Hudson Soft Co Ltd Interruption processing method and device therefor
US5694564A (en) * 1993-01-04 1997-12-02 Motorola, Inc. Data processing system a method for performing register renaming having back-up capability
JPH0756760A (en) * 1993-08-10 1995-03-03 Fujitsu Ltd Recovery equipment
JP2513142B2 (en) * 1993-09-07 1996-07-03 日本電気株式会社 Program simulator device
US5812823A (en) * 1996-01-02 1998-09-22 International Business Machines Corporation Method and system for performing an emulation context save and restore that is transparent to the operating system
US5925124A (en) * 1997-02-27 1999-07-20 International Business Machines Corporation Dynamic conversion between different instruction codes by recombination of instruction elements

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0285310A2 (en) * 1987-03-31 1988-10-05 Kabushiki Kaisha Toshiba Device for saving and restoring register information
US5872950A (en) * 1997-03-31 1999-02-16 International Business Machines Corporation Method and apparatus for managing register renaming including a wraparound array and an indication of rename entry ages
WO1998059292A1 (en) * 1997-06-25 1998-12-30 Transmeta Corporation Improved microprocessor

Also Published As

Publication number Publication date
JP2002543490A (en) 2002-12-17
AU4580300A (en) 2000-11-10
JP4709394B2 (en) 2011-06-22
EP1183601A2 (en) 2002-03-06
WO2000065440A2 (en) 2000-11-02

Similar Documents

Publication Publication Date Title
GB2337142B (en) Method and apparatus for forwarding of operands in a computer system
US20040168078A1 (en) Apparatus, system and method for protecting function return address
KR100385426B1 (en) Method and apparatus for aliasing memory data in an advanced microprocessor
JP3615770B2 (en) Memory controller that detects failure to think of addressed components
EP0651327A3 (en) Recompilation of computer programs for enhanced optimization
US8464033B2 (en) Setting a flag bit to defer event handling to one of multiple safe points in an instruction stream
JP3776132B2 (en) Microprocessor improvements
US6470493B1 (en) Computer method and apparatus for safe instrumentation of reverse executable program modules
EP0849671A3 (en) A method for utilizing a multi-word instruction register during debugging of a data processing system
JPH08263287A (en) Exception processing of expectation instruction
MY126879A (en) Storing stack operands in registers
WO2000065440A3 (en) Exception handling method and apparatus for use in program code conversion
JPH0314025A (en) Instruction execution control system
US6820190B1 (en) Method and computer system for decomposing macroinstructions into microinstructions and forcing the parallel issue of at least two microinstructions
WO2002091166A3 (en) Apparatus and method for uniformly performing comparison operations on long word operands
WO2004046915A3 (en) Pipelined processor method and circuit
JPH10133884A5 (en)
US7219335B1 (en) Method and apparatus for stack emulation during binary translation
US20030191622A1 (en) Exception handling method and apparatus for use in program code conversion
WO1996008948A3 (en) Method and apparatus for fast microcontroller context switching
US6636960B1 (en) Method and apparatus for resteering failing speculation check instructions
JPS5922142A (en) Data processor
JPS63163543A (en) Information processor
JP2856784B2 (en) Electronic computer
JPH02181236A (en) Debug device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 09827970

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2000927395

Country of ref document: EP

ENP Entry into the national phase

Ref country code: JP

Ref document number: 2000 614118

Kind code of ref document: A

Format of ref document f/p: F

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWP Wipo information: published in national office

Ref document number: 2000927395

Country of ref document: EP

DPE2 Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101)