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WO2000060661A1 - Procede de production d'un dispositif a semi-conducteur - Google Patents

Procede de production d'un dispositif a semi-conducteur Download PDF

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Publication number
WO2000060661A1
WO2000060661A1 PCT/JP1999/001731 JP9901731W WO0060661A1 WO 2000060661 A1 WO2000060661 A1 WO 2000060661A1 JP 9901731 W JP9901731 W JP 9901731W WO 0060661 A1 WO0060661 A1 WO 0060661A1
Authority
WO
WIPO (PCT)
Prior art keywords
forming
gate
insulating film
conductive layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP1999/001731
Other languages
English (en)
Japanese (ja)
Inventor
Fumio Naito
Hisaya Imai
Hidenori Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei Microsystems Co Ltd
Asahi Kasei Microdevices Corp
Original Assignee
Asahi Kasei Microsystems Co Ltd
Asahi Kasei Microdevices Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP26982597A priority Critical patent/JP3556079B2/ja
Application filed by Asahi Kasei Microsystems Co Ltd, Asahi Kasei Microdevices Corp filed Critical Asahi Kasei Microsystems Co Ltd
Priority to PCT/JP1999/001731 priority patent/WO2000060661A1/fr
Priority to US09/701,633 priority patent/US6472259B1/en
Priority to DE1999183274 priority patent/DE19983274B4/de
Priority to KR10-2000-7013616A priority patent/KR100383703B1/ko
Publication of WO2000060661A1 publication Critical patent/WO2000060661A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Definitions

  • the present invention relates to a nonvolatile semiconductor memory device, and more particularly to a method of manufacturing a semiconductor device in which a nonvolatile memory transistor having a stacked gate structure including a floating gate and a control gate and a MOS transistor having a single gate structure are mixed.
  • a method of manufacturing an EPROM with a high voltage transistor is described, for example, in US Pat. No. 4,851,3,61.
  • a high voltage transistor eg, a MOS transistor can be used
  • an active region is formed in a semiconductor substrate, a thin tunnel region of a nonvolatile memory cell is formed, and then a first polysilicon layer is deposited on the entire surface of the semiconductor substrate.
  • the first polysilicon layer is processed to form a floating gate electrode of the nonvolatile memory cell.
  • a first passivation film is formed on the entire surface of the oxide film.
  • a second polysilicon layer is deposited, and the second polysilicon layer is processed to form a control gate of a memory cell, a gate electrode of a high-voltage transistor, and a gate electrode of a logic circuit. Disclosure of the invention
  • the second polysilicon layer thus formed has a step due to the first polysilicon layer, and the second polysilicon deposited on the step sidewall of the first polysilicon layer during the etching of the second polysilicon layer.
  • the polysilicon must be removed, and conditions must be set to cause excessive etching and side etch.
  • the dimensional accuracy of the gate formed of the second polysilicon layer is reduced, and it is difficult to form a fine gate.
  • the gate oxide film of the high-voltage transistor and the gate oxide film of the logic circuit portion are formed at the same time, the gate oxide film must be formed relatively thick, and it is difficult to make the logic circuit portion finer. For this reason, a method of forming a relatively thick oxide film on the gate oxide film of the high-voltage MOS transistor and forming a thin gate oxide film on the open circuit portion may be considered. However, this method is not preferable because the number of steps is increased. .
  • the present invention provides a method of manufacturing a semiconductor device in which a nonvolatile memory cell such as an EEPROM and a logic circuit are mixedly mounted, and a method of forming a finer gate electrode in a logic circuit portion without increasing the number of manufacturing steps.
  • the purpose is to provide.
  • a first embodiment of the present invention relates to a method of manufacturing a semiconductor device including a nonvolatile memory transistor having a stack gate structure composed of a floating gate and a control gate, and a MOS transistor having a single gate structure.
  • Forming a region for separating the floating gate from the first conductive layer by removing a region extending in a direction perpendicular to a direction in which the control gate is formed by extension from the first conductive layer.
  • a method of manufacturing a semiconductor device comprising a step of forming the stack gate structure and the single gate structure.
  • a second embodiment of the present invention is directed to the first embodiment, wherein the MOS transistor having the single gate structure is a MOS transistor forming a high-voltage transistor and a peripheral circuit. It is a method for manufacturing the described semiconductor device.
  • the step of forming the first insulating film includes the step of forming a gate insulating film of the high-voltage transistor, and the step of forming a gate insulating film between the floating gate and the substrate. Forming a tunnel oxide film and, at the same time, forming a gate insulating film of the MOS transistor.
  • the second conductive layer constituting the control gate is used as a mask, and is self-aligned.
  • a fifth embodiment of the present invention is the method of manufacturing a semiconductor device according to the first embodiment, wherein the first conductive layer and the second conductive layer are made of polysilicon. It is.
  • the sixth embodiment of the present invention is the first embodiment, further comprising a step of forming a side wall on the side surface of the control gate after patterning the second conductive layer. It is a manufacturing method of the semiconductor device described.
  • a first metal silicide is provided on the second conductive layer.
  • the method of manufacturing a semiconductor device according to the fifth embodiment further comprising a step of forming a 4-layer.
  • An eighth embodiment of the present invention is directed to an eighth aspect of the present invention, wherein a step of forming a third insulating film on the first metal silicide layer, the third insulating film other than the control gate portion of the stack gate structure, Removing the first metal silicide layer, the second conductive layer, and the second insulating film to form a control gate portion; and forming a side wall in the control gate portion Forming a second metal silicide layer on the exposed first conductive layer and the third insulating film; and forming a fourth insulating film on the second metal silicide layer. Forming the fourth insulating film, the second metal silicide layer, and the first conductive layer to form an MS transistor having a single gate structure, and to form the control gate.
  • the first conductive layer is Forming the stack gate structure in a self-aligned manner by etching.
  • a ninth embodiment of the present invention relates to a method of manufacturing a semiconductor device having a nonvolatile memory cell, a capacitor and / or a resistor, and a logic circuit, wherein the tunnel oxide film of the memory cell and the logic circuit Forming a gate oxide film of the MOS transistor at the same time; forming a first polysilicon layer on the entire surface of the oxide film; and forming a floating gate of the memory cell on the first polysilicon layer. Removing a region for isolating the gate, forming a first insulating film on the first polysilicon layer, and forming a second polysilicon layer on the entire surface of the first insulating film.
  • FIGS. 1 to 13 are diagrams illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
  • FIG. 1 is a top view in which a field oxide film 2, a relatively thick gate oxide film 3, and a tunnel oxide film 4 are formed on a surface of a semiconductor substrate 1.
  • FIG. 2 is a cross-sectional view taken along the site II shown in FIG.
  • FIG. 3 is a diagram in which a polysilicon layer 6 is deposited as a first conductive layer on the entire surface of the substrate.
  • FIG. 4 is a top view showing a structure in which the polysilicon layer 6 at a predetermined position is removed by etching.
  • FIG. 5 is a cross-sectional view taken along the site V shown in FIG.
  • FIG. 6 is a cross-sectional view showing that a first insulating film is formed on the polysilicon layer 6.
  • FIG. 7 is a cross-sectional view showing that a second conductive layer is formed on first insulating film 7.
  • FIG. 8 is a cross-sectional view at the stage shown in FIG. 7, cut along a portion corresponding to the portion V in FIG.
  • Figure 9 shows that the control gate 11 is provided at the part corresponding to the stack gate.
  • FIG. 10 is a cross-sectional view taken along the site X shown in FIG.
  • FIG. 11 is a cross-sectional view of a semiconductor device manufactured according to the first embodiment of the present invention.
  • FIG. 12 is a top view of a semiconductor device manufactured according to the first embodiment of the present invention using the control gate portion as a mask.
  • FIG. 13 is a cross-sectional view taken along the site XII I shown in FIG. 14 to 23 illustrate a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
  • FIG. 14 is a cross-sectional view showing that a field oxide film and a gate oxide film are formed on the semiconductor substrate 21.
  • FIG. 15 shows that the photo-resist is used to remove the gate oxide film 23 corresponding to the gate of the non-volatile memory cell and the gate of the MOS transistor of the open-circuit circuit. It is sectional drawing.
  • FIG. 16 is a cross-sectional view showing the formation of a stack oxide film 25a of a stack gate of a nonvolatile memory cell and a gate oxide film 25b of a portion corresponding to a gate of a MOS transistor of an open circuit.
  • FIG. 17 is a cross-sectional view showing a stage in which a polysilicon layer 26 doped with phosphorus is formed on the entire surface of the substrate to form a first conductive layer.
  • the entire surface of the substrate is a sectional view showing a step of forming the S i 0 2 / S i 3 N 4 ONO film 2 7 comprising three layers of ZS i 0 2.
  • FIG. 7 is a cross-sectional view showing a stage in which a stack gate and a capacitor of a volatile memory cell are formed.
  • 2 0 is a sectional view showing a step of forming a C VD S i 0 2 film 3 2 on the entire surface of the substrate.
  • FIG. 4 is a cross-sectional view showing a stage where a door 34 is formed.
  • Figure 22 shows the metal silicide layer over the entire surface of the substrate
  • FIG. 23 is a cross-sectional view showing a stage in which a floating gate is formed in a self-aligned manner using the upper structure of the ONO film 27 or more and the side wall 34 formed on the side as a mask.
  • FIG. 24 is a cross-sectional view of a semiconductor device manufactured according to the second embodiment of the present invention.
  • 25 to 26 are diagrams illustrating a method for manufacturing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing a stage in which a laminated structure made of zero is formed.
  • FIG. 5 is a cross-sectional view showing a stage in which a is formed.
  • This method is a method for manufacturing a semiconductor device in which a nonvolatile memory cell such as an EEPROM and a MOS transistor are mixedly mounted.
  • the non-volatile memory cell has a stack gate in which a floating gate and a control gate are stacked on a tunnel oxide film via an insulating film, and a select gate formed of a high-voltage transistor for selecting a desired stack gate.
  • FIG. 1 is a top view in which a field oxide film 2, a relatively thick gate oxide film 3, and a tunnel oxide film 4 are formed on a surface of a semiconductor substrate 1.
  • FIG. 2 is a cross-sectional view taken along the site II shown in FIG. At this stage, the source, drain and stack gate of the transistor to be the memory, the select gate and the channel region of the MOS transistor have already been formed on the semiconductor substrate 1, but in order to maintain the clarity of the drawing, Not shown.
  • a field oxide film 2 and a relatively thick gate oxide film 3 are formed by thermal oxidation.
  • the thickness of the field oxide film is 450 nm, and the thickness of the gate oxide film is, for example, 41.5 nm.
  • the gate oxide film 3 at the position corresponding to the tunnel oxide film 4 of the nonvolatile memory cell and the position corresponding to the gate oxide film 5 of the logic circuit is removed by etching. 4 and the gate oxide film 5 of the MOS transistor, respectively. Formed to a thickness of 1 O nm.
  • a region i is a region of a nonvolatile memory cell
  • a region ii is a region of an MS transistor.
  • FIG. 3 is a diagram in which a polysilicon layer 6 is deposited as a first conductive layer on the entire surface of the substrate.
  • the polysilicon layer 6 constituting the floating gate of the nonvolatile memory cell is separated.
  • FIG. 4 is a top view showing a structure in which the polysilicon layer 6 at a predetermined position is removed by etching.
  • FIG. 5 is a cross-sectional view taken along a portion V shown in FIG. 4, and this cutting line is orthogonal to the cutting line in FIG. This shows a state where a groove is formed by etching a predetermined position of the polysilicon layer 6 and the field oxide film 2 is exposed at the bottom of the groove.
  • a groove is formed only in the X direction perpendicular to the y direction, where the control gate is extended later. If this groove is not formed, the floating gate cannot be separated in a later step if the control gate is extended and formed without breaks.
  • FIG. 6 is a cross-sectional view showing that a first insulating film is formed on the polysilicon layer 6.
  • FIG. 7 is a cross-sectional view showing that a second conductive layer is formed on first insulating film 7.
  • a polysilicon layer 8 was deposited as a second conductive layer.
  • FIG. 8 is a cross-sectional view in a state where the polysilicon layer 8 is formed, which is cut at a portion corresponding to the portion V in FIG.
  • FIG. 9 is a top view showing that a control gate is provided in a portion corresponding to the stack gate
  • FIG. 10 is a cross-sectional view taken along a portion X shown in FIG.
  • An insulating film 10 is formed on the entire surface of the polysilicon layer 8, and a mask is provided on a portion corresponding to the stack gate of the nonvolatile memory cell, and a portion other than the portion corresponding to the stack gate is formed by reactive ion etching.
  • the second of A state in which the insulating layer 10, the polysilicon layer 8 and the first insulating film 7 are removed by etching to form a polysilicon layer (control gate) 11 is shown.
  • an insulating film 12 is deposited, and the entire surface is subjected to reactive ion etching to form a side wall 13 on the side of the control gate 11.
  • a floating gate 14 forming a part of the stack gate 9 of the nonvolatile memory cell is formed in a self-aligned manner.
  • the selection gate 16 of the nonvolatile memory cell and the gate electrode 17 of the MOS transistor can be formed simultaneously.
  • an insulating film 15 is deposited, and then a mask is provided on a portion corresponding to the selection gate of the nonvolatile memory cell and the gate electrode of the MOS transistor.
  • FIG. 11 is a cross-sectional view of the semiconductor device manufactured as described above. i indicates a nonvolatile memory cell area, and i i is an M ⁇ S transistor area.
  • FIG. 9 the control gate portion shown in FIG. 9 (that is, the first insulating film 7, the control gate 11 and the second insulating film 10) is used. ) Can be used as a mask to etch the polysilicon layer 6 to form the floating gate 14.
  • the selection gate electrode 16 and the like of the nonvolatile memory cell are formed in the same manner as described above.
  • the gate electrode 17 of the MOS transistor can be formed simultaneously.
  • FIG. 12 shows a top view of the semiconductor device thus manufactured.
  • FIG. 13 is a cross-sectional view taken along the site XIII shown in FIG.
  • the gate oxide film 5 of the MOS transistor can be formed thinner together with the tunnel oxide film 4 of the stack gate 9 of the nonvolatile memory cell. Since the floating gate 14 is formed in a self-aligned manner, the gate can be miniaturized without increasing the number of steps.
  • FIGS. A second embodiment of the present invention will be described with reference to FIGS.
  • This embodiment corresponds to the seventh and eighth embodiments of the present invention, and is a manufacturing example of a semiconductor device having a nonvolatile memory cell having a stack gate structure, a MOS transistor of an open circuit, and a resistor and a capacitor. It is.
  • the formation of the active region below both the gate of the non-volatile memory cell and the gate of the MOS transistor, and the formation of the channel, source, and drain are well known and will not be described.
  • FIG. 14 is a cross-sectional view showing that a field oxide film and a gate oxide film have been formed on the semiconductor substrate 21.
  • a field oxide film 22 having a thickness of 45 O nm and a thick gate oxide film 23 having a thickness of 41.5 nm were formed on the surface of the semiconductor substrate 21 by thermal oxidation.
  • the semiconductor substrate 21 has the stack gate source, drain and stack gate of the non-volatile memory cell, the selection gate and the channel region of the MOS transistor already formed. Omitted.
  • FIG. 15 shows the gate oxidation of the gate corresponding to the gate of the non-volatile memory cell and the gate of the M ⁇ S transistor of the logic circuit using the photo-resist.
  • FIG. 4 is a cross-sectional view showing that a film 23 has been removed.
  • Huotre Using the gate 24, a thick gate oxide corresponding to the tunnel oxide film 25a of the stack gate of the nonvolatile memory cell and the gate oxide film 25b of the M0S transistor of the logic circuit is used.
  • the film 23 was removed by a wet etch.
  • FIG. 16 is a cross-sectional view in which a tunnel oxide film 25a of a stack gate of a nonvolatile memory cell and a gate oxide film 25b of a portion corresponding to a gate of a MOS transistor of a logic circuit are formed. is there.
  • a 1-nm-thick tunnel oxide film 25a and a MOS transistor gate oxide film 25b were formed by thermal oxidation.
  • a polysilicon layer 26 having a thickness of 25 Onm is formed on the entire surface of the oxide film (with a thickness of 0, and is doped with phosphorus to form a predetermined polysilicon layer 26).
  • the first conductive layer was removed, and the resulting phosphorus glass was removed using a hydrofluoric acid solution, and then, as described above, a predetermined portion of the polysilicon layer 26 was formed. Was removed by dry etching to separate the floating gate.
  • the thickness 1 onm of S i 0 2 a thickness of 1 Onm S i 3 N 4, 3 layers of S i 0 2 thickness 5 nm ONO
  • the film 27 is formed by thermal oxidation of S i 0 2 and C 3 V 4 by C VD, and a polysilicon layer 28 of 250 nm thickness is formed thereon.
  • the second conductive layer was given a predetermined conductivity. At that time, the phosphorus glass generated on the surface was removed using a hydrofluoric acid solution.
  • a metal silicide layer in this example, a tungsten (W) silicide layer 29, was formed on the polysilicon layer 28 to a thickness of 15 Onm by sputtering.
  • the S i 0 2 film 3 0 thick 2 3 0 nm was due connection formed by CVD CV D thereon (hereinafter, referred to as C VD S i 0 2 film).
  • a follower Torejisu bets 3 1 provided at a predetermined position, CVDS i 0 2 film 3 0 by dry etching Then, the W silicide layer 29, the polysilicon layer 28 and the 0N0 film 27 were removed. At this stage, a stacked structure for a stack gate superstructure and a capacitor is formed.
  • a metal silicide layer in this example, a W silicide layer 35 is formed on the entire surface by sputtering to a thickness of 15 Onm. Formed on it, thickness 2 3 om
  • the opening gate (polysilicon layer) 26 of the stack gate 37 is formed by the upper structure above the ONO film 27 and the side wall 34 formed on the side. By using it as a mask, it was formed in a self-aligned manner. Further, the select gate and the source and drain of the MOS transistor were formed by a known method.
  • FIG. 24 shows a cross-sectional view of the semiconductor device manufactured as described above. In FIG. 24, ch indicates a channel, d indicates a drain, and s indicates a source. Although not shown, the structure of the channel, source, and drain below each gate of the semiconductor device shown in FIG. 13 is the same as that in FIG.
  • a third embodiment in which the metal silicide layer is omitted can be adopted.
  • the third embodiment corresponds to a ninth embodiment of the present invention.
  • the polysilicon layer in the manufacture of a semiconductor device having a nonvolatile memory cell, a MOS transistor of a logic circuit, and a resistor and a capacitor, the polysilicon layer is not used without using the metal silicide layers 29 and 35. 26 and the polysilicon layer 28 can be used as electrodes. That is, without forming the W silicide layers 29 and 35, the polysilicon layer as shown in FIG. 25 is placed at the position corresponding to the nonvolatile memory cell, the MOS transistor, the capacitor and the resistor. 2 6, ⁇ N ⁇ film 2 7, O 0 066
  • FIG. 15 Create a laminated structure consisting of the silicon layer 28 and the CVD Si 2 film 30.
  • FIG. 25 corresponds to the stage of FIG. 19 of the second embodiment. Then, the whole forming a CVDS i 0 2 film 3 2 on the structure, as shown in FIG. 2 6, all while leaving the CVDS i 0 2 film 3 and second region of the resistor and the lower electrode region of the Capacity evening
  • a side wall 34 may be formed on the side surface of the upper structure of the stack gate by anisotropically etching the surface.
  • FIG. 26 corresponds to the stage of FIG. 21 of the second embodiment. Even with this method, the floating gate can be formed in a self-aligned manner. The subsequent steps are the same as in the second embodiment. Industrial applicability
  • the first conductive layer (polysilicon layer 6) except for the region where the floating gate is separated is provided. , The flatness of the surface is maintained. Therefore, processing in subsequent steps such as the etching step of the second conductive layer and the like can be facilitated, dimensional accuracy can be increased, and miniaturization can be achieved. Since excessive etching is not required when etching the gate electrode of the logic circuit, a finer gate electrode can be formed. Furthermore, the stack oxide tunnel film of the nonvolatile memory cell and the gate oxide film of the MOS transistor of the logic circuit can be formed thin, and the floating gate of the stack gate can be self-aligned.
  • the dimensional accuracy of a semiconductor device in which a nonvolatile memory cell such as an EEPROM and a MOS transistor are mixedly mounted can be improved, and the miniaturization can be improved.
  • the number of steps can be reduced because the stacked gate and single-gate MOS transistors, resistors, and capacitors can be formed with two conductive layers. It is easy to mix with analog circuits.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé de production d'un dispositif à semi-conducteur doté d'un transistor de mémoire rémanente présentant une structure de grille empilée constituée d'une grille flottante et d'une grille de commande ainsi que d'un transistor MOS présentant une structure de grille unique, caractérisé en ce qu'il consiste à former une première couche mince isolante destinée à servir de couche mince d'oxyde de grille d'un transistor sur un substrat à semi-conducteur, à former une première couche conductive sur la première couche isolante, à retirer une région destinée à l'isolation de la grille flottante par rapport à la première couche conductive perpendiculairement au sens dans lequel la grille de commande doit être étendue et formée, à former une seconde couche mince isolante sur la première couche conductive, à former une seconde couche conductive sur la seconde couche mince isolante, à tracer le motif de la seconde couche conductive de manière à former la grille de commande et à tracer le motif de la première couche conductive afin de former la structure de grille empilée ainsi que la structure de grille unique.
PCT/JP1999/001731 1997-10-02 1999-04-01 Procede de production d'un dispositif a semi-conducteur Ceased WO2000060661A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP26982597A JP3556079B2 (ja) 1997-10-02 1997-10-02 半導体装置の製造方法
PCT/JP1999/001731 WO2000060661A1 (fr) 1997-10-02 1999-04-01 Procede de production d'un dispositif a semi-conducteur
US09/701,633 US6472259B1 (en) 1999-04-01 1999-04-01 Method of manufacturing semiconductor device
DE1999183274 DE19983274B4 (de) 1999-04-01 1999-04-01 Verfahren zum Herstellen eines nichtflüchtigen Halbleiterspeicherbauteils
KR10-2000-7013616A KR100383703B1 (ko) 1999-04-01 1999-04-01 반도체 장치의 제조 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP26982597A JP3556079B2 (ja) 1997-10-02 1997-10-02 半導体装置の製造方法
PCT/JP1999/001731 WO2000060661A1 (fr) 1997-10-02 1999-04-01 Procede de production d'un dispositif a semi-conducteur

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Cited By (2)

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KR100399415B1 (ko) * 2001-02-08 2003-09-26 삼성전자주식회사 비휘발성 메모리소자 및 그의 제조방법
CN102254952A (zh) * 2010-05-17 2011-11-23 常忆科技股份有限公司 双多晶硅闪存的堆叠式电容器及其制造方法

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JP3556079B2 (ja) * 1997-10-02 2004-08-18 旭化成マイクロシステム株式会社 半導体装置の製造方法
JPH11330430A (ja) 1998-05-18 1999-11-30 Nec Corp 不揮発性半導体記憶装置の製造方法
KR100383703B1 (ko) 1999-04-01 2003-05-14 아사히 가세이 마이크로시스템 가부시끼가이샤 반도체 장치의 제조 방법
JP4390412B2 (ja) * 2001-10-11 2009-12-24 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
KR100585097B1 (ko) * 2003-07-01 2006-05-30 삼성전자주식회사 이이피롬 소자 및 그 제조방법
JP5073934B2 (ja) 2005-10-06 2012-11-14 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
JP2016162904A (ja) * 2015-03-03 2016-09-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

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JPS6276668A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 半導体記憶装置
JPS63144577A (ja) * 1986-12-09 1988-06-16 Toshiba Corp 不揮発性半導体記憶装置
JPH04119666A (ja) * 1989-12-14 1992-04-21 Sgs Thomson Microelettronica Spa 集積回路の製造方法
JPH10189783A (ja) * 1996-12-26 1998-07-21 Lg Semicon Co Ltd 半導体メモリ素子及びその製造方法
JPH11111936A (ja) * 1997-10-02 1999-04-23 Asahi Kasei Micro Syst Co Ltd 半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100399415B1 (ko) * 2001-02-08 2003-09-26 삼성전자주식회사 비휘발성 메모리소자 및 그의 제조방법
CN102254952A (zh) * 2010-05-17 2011-11-23 常忆科技股份有限公司 双多晶硅闪存的堆叠式电容器及其制造方法
CN102254952B (zh) * 2010-05-17 2014-01-22 常忆科技股份有限公司 双多晶硅闪存的堆叠式电容器及其制造方法

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