WO2000060661A1 - Method of manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device provided with a nonvolatile memory transistor having a stacked gate structure made up of a floating gate and a control gate and a MOS transistor having a single gate structure, characterized by comprising forming a first insulating film to serve as a gate oxide film of a transistor on a semiconductor substrate, forming a first conductive layer on the first insulating layer, removing a region for isolation of the floating gate from the first conductive layer perpendicularly to the direction in which the control gate is to be extended and formed, forming a second insulating film on the first conductive layer, forming a second conductive layer on the second insulating film, patterning the second conductive layer so as to form the control gate, and patterning the first conductive layer so as to form the stacked gate structure and the single gate structure.

Description

 Specification

 Manufacturing method of semiconductor device

 The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a method of manufacturing a semiconductor device in which a nonvolatile memory transistor having a stacked gate structure including a floating gate and a control gate and a MOS transistor having a single gate structure are mixed. Background art

 A method of manufacturing an EPROM with a high voltage transistor (eg, a MOS transistor can be used) is described, for example, in US Pat. No. 4,851,3,61. According to this conventional method, an active region is formed in a semiconductor substrate, a thin tunnel region of a nonvolatile memory cell is formed, and then a first polysilicon layer is deposited on the entire surface of the semiconductor substrate. Next, the first polysilicon layer is processed to form a floating gate electrode of the nonvolatile memory cell. Furthermore, after forming a capacitor insulating film, a gate oxide film of a high-voltage transistor, and a gate oxide film of a logic circuit portion, a first passivation film is formed on the entire surface of the oxide film.

A second polysilicon layer is deposited, and the second polysilicon layer is processed to form a control gate of a memory cell, a gate electrode of a high-voltage transistor, and a gate electrode of a logic circuit. Disclosure of the invention

However, as described above, in a conventional method of manufacturing a semiconductor device in which a nonvolatile memory cell such as an EEPROM and a logic circuit are mixed, The second polysilicon layer thus formed has a step due to the first polysilicon layer, and the second polysilicon deposited on the step sidewall of the first polysilicon layer during the etching of the second polysilicon layer. The polysilicon must be removed, and conditions must be set to cause excessive etching and side etch. However, in this case, the dimensional accuracy of the gate formed of the second polysilicon layer is reduced, and it is difficult to form a fine gate.

 In addition, since the gate oxide film of the high-voltage transistor and the gate oxide film of the logic circuit portion are formed at the same time, the gate oxide film must be formed relatively thick, and it is difficult to make the logic circuit portion finer. For this reason, a method of forming a relatively thick oxide film on the gate oxide film of the high-voltage MOS transistor and forming a thin gate oxide film on the open circuit portion may be considered. However, this method is not preferable because the number of steps is increased. .

 Therefore, the present invention provides a method of manufacturing a semiconductor device in which a nonvolatile memory cell such as an EEPROM and a logic circuit are mixedly mounted, and a method of forming a finer gate electrode in a logic circuit portion without increasing the number of manufacturing steps. The purpose is to provide.

A first embodiment of the present invention relates to a method of manufacturing a semiconductor device including a nonvolatile memory transistor having a stack gate structure composed of a floating gate and a control gate, and a MOS transistor having a single gate structure. Forming a first insulating film to be a gate oxide film of both the nonvolatile memory transistor and the MOS transistor on a semiconductor substrate; and forming a first conductive layer on the first insulating film. Forming a region for separating the floating gate from the first conductive layer by removing a region extending in a direction perpendicular to a direction in which the control gate is formed by extension from the first conductive layer. Forming a second insulating film on the first conductive layer; and forming the second insulating film on the first conductive layer. Forming a second conductive layer on the insulating film, patterning the second conductive layer so as to form the control gate, and patterning the first conductive layer. A method of manufacturing a semiconductor device, comprising a step of forming the stack gate structure and the single gate structure.

 A second embodiment of the present invention is directed to the first embodiment, wherein the MOS transistor having the single gate structure is a MOS transistor forming a high-voltage transistor and a peripheral circuit. It is a method for manufacturing the described semiconductor device.

 In a third embodiment of the present invention, the step of forming the first insulating film includes the step of forming a gate insulating film of the high-voltage transistor, and the step of forming a gate insulating film between the floating gate and the substrate. Forming a tunnel oxide film and, at the same time, forming a gate insulating film of the MOS transistor. The method of manufacturing a semiconductor device according to the second embodiment,

 According to a fourth embodiment of the present invention, in the step of patterning the first conductive layer to form a stack gate structure, the second conductive layer constituting the control gate is used as a mask, and is self-aligned. The method of manufacturing a semiconductor device according to the first embodiment, characterized in that the floating gate is patterned.

 A fifth embodiment of the present invention is the method of manufacturing a semiconductor device according to the first embodiment, wherein the first conductive layer and the second conductive layer are made of polysilicon. It is.

 The sixth embodiment of the present invention is the first embodiment, further comprising a step of forming a side wall on the side surface of the control gate after patterning the second conductive layer. It is a manufacturing method of the semiconductor device described.

According to a seventh embodiment of the present invention, a first metal silicide is provided on the second conductive layer. 00/60661

 The method of manufacturing a semiconductor device according to the fifth embodiment, further comprising a step of forming a 4-layer.

 An eighth embodiment of the present invention is directed to an eighth aspect of the present invention, wherein a step of forming a third insulating film on the first metal silicide layer, the third insulating film other than the control gate portion of the stack gate structure, Removing the first metal silicide layer, the second conductive layer, and the second insulating film to form a control gate portion; and forming a side wall in the control gate portion Forming a second metal silicide layer on the exposed first conductive layer and the third insulating film; and forming a fourth insulating film on the second metal silicide layer. Forming the fourth insulating film, the second metal silicide layer, and the first conductive layer to form an MS transistor having a single gate structure, and to form the control gate. The first conductive layer is Forming the stack gate structure in a self-aligned manner by etching. The method of manufacturing a semiconductor device according to the seventh embodiment, further comprising the step of:

A ninth embodiment of the present invention relates to a method of manufacturing a semiconductor device having a nonvolatile memory cell, a capacitor and / or a resistor, and a logic circuit, wherein the tunnel oxide film of the memory cell and the logic circuit Forming a gate oxide film of the MOS transistor at the same time; forming a first polysilicon layer on the entire surface of the oxide film; and forming a floating gate of the memory cell on the first polysilicon layer. Removing a region for isolating the gate, forming a first insulating film on the first polysilicon layer, and forming a second polysilicon layer on the entire surface of the first insulating film. Forming a second insulating film on the second polysilicon layer; leaving the desired region of the memory cell and the upper electrode region of the capacitor, the second insulating film; 2 Po Removing the polysilicon layer and the first insulating film; forming a third insulating film over the entire surface; leaving the lower electrode region and the resistor region of the capacitor in the third insulating film. A process of removing other parts, and a step of forming a stack gate side wall of the memory cell by anisotropically etching the entire surface. o Brief description of drawings

 1 to 13 are diagrams illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

 FIG. 1 is a top view in which a field oxide film 2, a relatively thick gate oxide film 3, and a tunnel oxide film 4 are formed on a surface of a semiconductor substrate 1.

 FIG. 2 is a cross-sectional view taken along the site II shown in FIG.

 FIG. 3 is a diagram in which a polysilicon layer 6 is deposited as a first conductive layer on the entire surface of the substrate.

 FIG. 4 is a top view showing a structure in which the polysilicon layer 6 at a predetermined position is removed by etching.

 FIG. 5 is a cross-sectional view taken along the site V shown in FIG.

 FIG. 6 is a cross-sectional view showing that a first insulating film is formed on the polysilicon layer 6.

 FIG. 7 is a cross-sectional view showing that a second conductive layer is formed on first insulating film 7.

 FIG. 8 is a cross-sectional view at the stage shown in FIG. 7, cut along a portion corresponding to the portion V in FIG.

Figure 9 shows that the control gate 11 is provided at the part corresponding to the stack gate. FIG.

 FIG. 10 is a cross-sectional view taken along the site X shown in FIG.

 FIG. 11 is a cross-sectional view of a semiconductor device manufactured according to the first embodiment of the present invention.

 FIG. 12 is a top view of a semiconductor device manufactured according to the first embodiment of the present invention using the control gate portion as a mask.

 FIG. 13 is a cross-sectional view taken along the site XII I shown in FIG. 14 to 23 illustrate a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

 FIG. 14 is a cross-sectional view showing that a field oxide film and a gate oxide film are formed on the semiconductor substrate 21.

 FIG. 15 shows that the photo-resist is used to remove the gate oxide film 23 corresponding to the gate of the non-volatile memory cell and the gate of the MOS transistor of the open-circuit circuit. It is sectional drawing.

 FIG. 16 is a cross-sectional view showing the formation of a stack oxide film 25a of a stack gate of a nonvolatile memory cell and a gate oxide film 25b of a portion corresponding to a gate of a MOS transistor of an open circuit.

 FIG. 17 is a cross-sectional view showing a stage in which a polysilicon layer 26 doped with phosphorus is formed on the entire surface of the substrate to form a first conductive layer.

1 8, the entire surface of the substrate is a sectional view showing a step of forming the _{S i 0 2 / S i 3} N 4 ONO film 2 7 comprising three layers of ZS i 0 _2.

Figure 1 9, the follower Torejisu bets 3 1 provided at a predetermined position, CVDS i 0 ₂ film 30, W Shirisai de layer 29 by dry etching, the poly-silicon layer 2 8, and ON 0 film 27 is removed, the non-volatile FIG. 7 is a cross-sectional view showing a stage in which a stack gate and a capacitor of a volatile memory cell are formed. 2 0 is a sectional view showing a step of forming a C VD S i 0 ₂ film 3 2 on the entire surface of the substrate.

Figure 2 1 is a the Photo registry 3 3 provided at a position corresponding to the capacitor and the resistor, better dividing the CVD S i 0 ₂ film 3 2 by dry etching, rhinoceros the sidewall of the superstructure of the stack gate Ichito unit FIG. 4 is a cross-sectional view showing a stage where a door 34 is formed.

 Figure 22 shows the metal silicide layer over the entire surface of the substrate, and

It is a sectional view showing a C VD S i 0 ₂ film 3 6 to form a step.

 FIG. 23 is a cross-sectional view showing a stage in which a floating gate is formed in a self-aligned manner using the upper structure of the ONO film 27 or more and the side wall 34 formed on the side as a mask.

 FIG. 24 is a cross-sectional view of a semiconductor device manufactured according to the second embodiment of the present invention.

 25 to 26 are diagrams illustrating a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

2 5, the nonvolatile memory cell, MO S transistor, at a position corresponding to the capacitor and resistor, polysilicon con layer 2 6, 0 NO film 2 7, polysilicon con layer 2 8 and CVD S i 0 ₂ film 3 FIG. 4 is a cross-sectional view showing a stage in which a laminated structure made of zero is formed.

2 6, Sai Douoru 3 to the side of the superstructure of the static Kkuge Ichito by anisotropically Etsuchingu the entire surface, leaving a CVD S i 0 ₂ film 3 and second lower electrode region and the resistor region of the capacitor FIG. 5 is a cross-sectional view showing a stage in which a is formed. BEST MODE FOR CARRYING OUT THE INVENTION 1

 8 A first embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. The first embodiment corresponds to first to sixth aspects of the present invention. This method is a method for manufacturing a semiconductor device in which a nonvolatile memory cell such as an EEPROM and a MOS transistor are mixedly mounted. The non-volatile memory cell has a stack gate in which a floating gate and a control gate are stacked on a tunnel oxide film via an insulating film, and a select gate formed of a high-voltage transistor for selecting a desired stack gate. By controlling the threshold voltage of the stacked gate transistor by forcibly injecting charges through the tunnel oxide film, data is stored. Separately, there is a case where a circuit for generating a high voltage composed of a high-voltage transistor and further controlling it is built-in. Since the method of the present invention has a special feature in a method of forming a gate, a description of formation of a known channel, source, drain, and the like in an active region will be omitted.

 FIG. 1 is a top view in which a field oxide film 2, a relatively thick gate oxide film 3, and a tunnel oxide film 4 are formed on a surface of a semiconductor substrate 1. FIG. 2 is a cross-sectional view taken along the site II shown in FIG. At this stage, the source, drain and stack gate of the transistor to be the memory, the select gate and the channel region of the MOS transistor have already been formed on the semiconductor substrate 1, but in order to maintain the clarity of the drawing, Not shown.

First, a field oxide film 2 and a relatively thick gate oxide film 3 are formed by thermal oxidation. The thickness of the field oxide film is 450 nm, and the thickness of the gate oxide film is, for example, 41.5 nm. Next, using a mask, the gate oxide film 3 at the position corresponding to the tunnel oxide film 4 of the nonvolatile memory cell and the position corresponding to the gate oxide film 5 of the logic circuit is removed by etching. 4 and the gate oxide film 5 of the MOS transistor, respectively. Formed to a thickness of 1 O nm. In FIG. 2, a region i is a region of a nonvolatile memory cell, and a region ii is a region of an MS transistor.

 Next, FIG. 3 is a diagram in which a polysilicon layer 6 is deposited as a first conductive layer on the entire surface of the substrate. Next, the polysilicon layer 6 constituting the floating gate of the nonvolatile memory cell is separated. FIG. 4 is a top view showing a structure in which the polysilicon layer 6 at a predetermined position is removed by etching. FIG. 5 is a cross-sectional view taken along a portion V shown in FIG. 4, and this cutting line is orthogonal to the cutting line in FIG. This shows a state where a groove is formed by etching a predetermined position of the polysilicon layer 6 and the field oxide film 2 is exposed at the bottom of the groove. A groove is formed only in the X direction perpendicular to the y direction, where the control gate is extended later. If this groove is not formed, the floating gate cannot be separated in a later step if the control gate is extended and formed without breaks.

Next, FIG. 6 is a cross-sectional view showing that a first insulating film is formed on the polysilicon layer 6. An insulating film 7 on the polysilicon layer _{6 S i 0 2, S i} 3 N 4, S i 0 2 three-layer structure (hereinafter, referred to as ONO film) you formed as o

 FIG. 7 is a cross-sectional view showing that a second conductive layer is formed on first insulating film 7. A polysilicon layer 8 was deposited as a second conductive layer. FIG. 8 is a cross-sectional view in a state where the polysilicon layer 8 is formed, which is cut at a portion corresponding to the portion V in FIG.

FIG. 9 is a top view showing that a control gate is provided in a portion corresponding to the stack gate, and FIG. 10 is a cross-sectional view taken along a portion X shown in FIG. An insulating film 10 is formed on the entire surface of the polysilicon layer 8, and a mask is provided on a portion corresponding to the stack gate of the nonvolatile memory cell, and a portion other than the portion corresponding to the stack gate is formed by reactive ion etching. The second of A state in which the insulating layer 10, the polysilicon layer 8 and the first insulating film 7 are removed by etching to form a polysilicon layer (control gate) 11 is shown.

 Next, an insulating film 12 is deposited, and the entire surface is subjected to reactive ion etching to form a side wall 13 on the side of the control gate 11. Next, by using this side wall to etch the polysilicon layer 6, a floating gate 14 forming a part of the stack gate 9 of the nonvolatile memory cell is formed in a self-aligned manner. During the etching for forming the floating gate 14, the selection gate 16 of the nonvolatile memory cell and the gate electrode 17 of the MOS transistor can be formed simultaneously. First, an insulating film 15 is deposited, and then a mask is provided on a portion corresponding to the selection gate of the nonvolatile memory cell and the gate electrode of the MOS transistor. By etching the insulating layer 15 and the polysilicon layer 6 using this mask, the insulating film 12 and the side wall 13 as an etching mask, the floating gate 14 and the selection gate electrode of the nonvolatile memory cell are etched. 16 and the gate electrode 17 of the MOS transistor are formed. Then, the mask at the position corresponding to the selection gate of the nonvolatile memory cell and the gate of the MOS transistor is removed. Subsequently, a select gate and a source and a drain of the MOS transistor are formed by a known method. FIG. 11 is a cross-sectional view of the semiconductor device manufactured as described above. i indicates a nonvolatile memory cell area, and i i is an M〇S transistor area.

To form the floating gate 14 of the non-volatile memory cell in a self-aligned manner, the control gate portion shown in FIG. 9 (that is, the first insulating film 7, the control gate 11 and the second insulating film 10) is used. ) Can be used as a mask to etch the polysilicon layer 6 to form the floating gate 14. At this time, the selection gate electrode 16 and the like of the nonvolatile memory cell are formed in the same manner as described above. And the gate electrode 17 of the MOS transistor can be formed simultaneously. FIG. 12 shows a top view of the semiconductor device thus manufactured. FIG. 13 is a cross-sectional view taken along the site XIII shown in FIG.

 As described above, according to the present invention, the gate oxide film 5 of the MOS transistor can be formed thinner together with the tunnel oxide film 4 of the stack gate 9 of the nonvolatile memory cell. Since the floating gate 14 is formed in a self-aligned manner, the gate can be miniaturized without increasing the number of steps.

 A second embodiment of the present invention will be described with reference to FIGS. This embodiment corresponds to the seventh and eighth embodiments of the present invention, and is a manufacturing example of a semiconductor device having a nonvolatile memory cell having a stack gate structure, a MOS transistor of an open circuit, and a resistor and a capacitor. It is. The formation of the active region below both the gate of the non-volatile memory cell and the gate of the MOS transistor, and the formation of the channel, source, and drain are well known and will not be described.

 FIG. 14 is a cross-sectional view showing that a field oxide film and a gate oxide film have been formed on the semiconductor substrate 21. A field oxide film 22 having a thickness of 45 O nm and a thick gate oxide film 23 having a thickness of 41.5 nm were formed on the surface of the semiconductor substrate 21 by thermal oxidation. At this stage, the semiconductor substrate 21 has the stack gate source, drain and stack gate of the non-volatile memory cell, the selection gate and the channel region of the MOS transistor already formed. Omitted.

Next, Fig. 15 shows the gate oxidation of the gate corresponding to the gate of the non-volatile memory cell and the gate of the M〇S transistor of the logic circuit using the photo-resist. FIG. 4 is a cross-sectional view showing that a film 23 has been removed. Huotre Using the gate 24, a thick gate oxide corresponding to the tunnel oxide film 25a of the stack gate of the nonvolatile memory cell and the gate oxide film 25b of the M0S transistor of the logic circuit is used. The film 23 was removed by a wet etch.

 Next, FIG. 16 is a cross-sectional view in which a tunnel oxide film 25a of a stack gate of a nonvolatile memory cell and a gate oxide film 25b of a portion corresponding to a gate of a MOS transistor of a logic circuit are formed. is there. After removing the resist 24 and performing necessary cleaning steps, a 1-nm-thick tunnel oxide film 25a and a MOS transistor gate oxide film 25b were formed by thermal oxidation. Then, as shown in FIG. 17, a polysilicon layer 26 having a thickness of 25 Onm is formed on the entire surface of the oxide film (with a thickness of 0, and is doped with phosphorus to form a predetermined polysilicon layer 26). By giving conductivity, the first conductive layer was removed, and the resulting phosphorus glass was removed using a hydrofluoric acid solution, and then, as described above, a predetermined portion of the polysilicon layer 26 was formed. Was removed by dry etching to separate the floating gate.

Next, as shown in FIG. 1 8, consisting of the entire surface, the thickness 1 onm of S i 0 _2, a thickness of _{1 Onm S i 3 N 4,} 3 layers of S i 0 ₂ thickness 5 nm ONO The film 27 is formed by thermal oxidation of S i 0 _{2 and} C ₃ V ₄ by C VD, and a polysilicon layer 28 of 250 nm thickness is formed thereon. The second conductive layer was given a predetermined conductivity. At that time, the phosphorus glass generated on the surface was removed using a hydrofluoric acid solution. After a necessary cleaning step, a metal silicide layer, in this example, a tungsten (W) silicide layer 29, was formed on the polysilicon layer 28 to a thickness of 15 Onm by sputtering. In addition, the S i 0 ₂ film 3 0 thick 2 3 0 nm was due connexion formed by CVD CV D thereon (hereinafter, referred to as C VD S i 0 ₂ film). Next, as shown in FIG. 1 9, in order to form a stacked gate and a capacitor of the non-volatile memory cells, a follower Torejisu bets 3 1 provided at a predetermined position, CVDS i 0 ₂ film 3 0 by dry etching Then, the W silicide layer 29, the polysilicon layer 28 and the 0N0 film 27 were removed. At this stage, a stacked structure for a stack gate superstructure and a capacitor is formed. Followed by, after removal of the Photo registry 3 1, as shown in FIG. 2 0, to form a thick 1 7 Onm C VD S i 0 2 film 3 and second on the entire surface.

Next, as shown in FIG. 2 1 a provided follower Torejisu preparative 3 3 at a position corresponding to the capacitor and the resistor, was removed by dividing the CVDS i 0 ₂ film 3 2 by dry etching. By dry etching, a force C VD S i 0 ₂ film 3 on the sidewalls of 2 superstructure stack gate portion which is exposed to cyclic Douoru 3 4 are ^formed?, Are covered in the Photo registry 3 3 No side wall is formed in the capacitor and resistor sections.

 Next, the resist is removed, and after a necessary cleaning step, as shown in FIG. 22, a metal silicide layer, in this example, a W silicide layer 35 is formed on the entire surface by sputtering to a thickness of 15 Onm. Formed on it, thickness 2 3 om

The CVD S i 0 ₂ film 3 6 have been conducted under the form to CVD. Finally,

Provide a photo resist on each of the C VD S i 02 film 36 corresponding to the gate of the select gate and the MOS transistor of the logic circuit, dry-etch, and excluding the bottom of the photo resist. of CVD S i 0 ₂ film 3 6, W Shirisai de layer 35, the polysilicon layer 2 6 removed; removing the host Torejisu bets. As a result, as shown in Fig. 23, 1) polysilicon layer (floating gate) 26, 0N0 film 27, polysilicon layer (control gate) 28, W silicon layer 29, and a stack gate 3 7 consisting of CVD S i 0 ₂ film 3 0, polysilicon con layer 2 6, W Shirisai de layer 35 and CVDS i 〇 ₂ Nonvolatile memory cell and a selection gate one bets 3 8 consisting film 3 6, and, 2) polysilicon consisting Con layer 2 6, W Shirisai de layer 35 and CVDS i 0 ₂ film 3 6 MO S transistor Gate 39 is formed. Furthermore, 3) made of a polycrystalline silicon layer 2 6, 0 N 0 film 2 7, the polysilicon layer 2 8, W Shirisai de layer 2 9, CVD S i 0 ₂ film 3 0, and CVD S i 0 ₂ film 3 2 Canon Pashita 4 0, and, 4) a poly silicon layer 2 6 and the second CVDS i 0 ₂ film 3 2 which resistor 4 1 are formed simultaneously.

 As can be seen from FIG. 23, the opening gate (polysilicon layer) 26 of the stack gate 37 is formed by the upper structure above the ONO film 27 and the side wall 34 formed on the side. By using it as a mask, it was formed in a self-aligned manner. Further, the select gate and the source and drain of the MOS transistor were formed by a known method. FIG. 24 shows a cross-sectional view of the semiconductor device manufactured as described above. In FIG. 24, ch indicates a channel, d indicates a drain, and s indicates a source. Although not shown, the structure of the channel, source, and drain below each gate of the semiconductor device shown in FIG. 13 is the same as that in FIG.

Instead of the second embodiment shown in FIGS. 14 to 23, a third embodiment in which the metal silicide layer is omitted can be adopted. The third embodiment corresponds to a ninth embodiment of the present invention. In the third embodiment, in the manufacture of a semiconductor device having a nonvolatile memory cell, a MOS transistor of a logic circuit, and a resistor and a capacitor, the polysilicon layer is not used without using the metal silicide layers 29 and 35. 26 and the polysilicon layer 28 can be used as electrodes. That is, without forming the W silicide layers 29 and 35, the polysilicon layer as shown in FIG. 25 is placed at the position corresponding to the nonvolatile memory cell, the MOS transistor, the capacitor and the resistor. 2 6, 〇N〇 film 2 7, O 0 066

15 Create a laminated structure consisting of the silicon layer 28 and the CVD Si 2 film 30. FIG. 25 corresponds to the stage of FIG. 19 of the second embodiment. Then, the whole forming a CVDS i 0 ₂ film 3 2 on the structure, as shown in FIG. 2 6, all while leaving the CVDS i 0 ₂ film 3 and second region of the resistor and the lower electrode region of the Capacity evening A side wall 34 may be formed on the side surface of the upper structure of the stack gate by anisotropically etching the surface. FIG. 26 corresponds to the stage of FIG. 21 of the second embodiment. Even with this method, the floating gate can be formed in a self-aligned manner. The subsequent steps are the same as in the second embodiment. Industrial applicability

As described above, according to the present invention, when manufacturing a semiconductor device having a nonvolatile memory cell and a logic circuit, the first conductive layer (polysilicon layer 6) except for the region where the floating gate is separated is provided. , The flatness of the surface is maintained. Therefore, processing in subsequent steps such as the etching step of the second conductive layer and the like can be facilitated, dimensional accuracy can be increased, and miniaturization can be achieved. Since excessive etching is not required when etching the gate electrode of the logic circuit, a finer gate electrode can be formed. Furthermore, the stack oxide tunnel film of the nonvolatile memory cell and the gate oxide film of the MOS transistor of the logic circuit can be formed thin, and the floating gate of the stack gate can be self-aligned. Since it can be formed, the dimensional accuracy of a semiconductor device in which a nonvolatile memory cell such as an EEPROM and a MOS transistor are mixedly mounted can be improved, and the miniaturization can be improved. In addition, the number of steps can be reduced because the stacked gate and single-gate MOS transistors, resistors, and capacitors can be formed with two conductive layers. It is easy to mix with analog circuits.

Claims

1. A method of manufacturing a semiconductor device including a nonvolatile memory transistor having a stacked gate structure composed of a floating gate and a control gate, and a MOS transistor having a single gate structure,  Forming a first insulating film to be a gate oxide film of both the nonvolatile memory transistor and the MOS transistor on the semiconductor substrate;  Forming a first conductive layer on the first insulating film;  Removing a region extending in a direction perpendicular to a direction in which the control gate is formed to extend from the first conductive layer to form a region for separating the floating gate;  Forming a second insulating film on the first conductive layer;  Forming a second conductive layer on the second insulating film;  Patterning the second conductive layer so as to form the control gate;  Patterning the first conductive layer to form the stack gate structure and the single gate structure;  A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the MOS transistor having the single gate structure is a MOS transistor forming a high voltage transistor and a peripheral circuit. 3. The step of forming the first insulating film includes: forming a gate insulating film of the high-voltage transistor; and forming a gate between the floating gate and a substrate. 3. The method for manufacturing a semiconductor device according to claim 2, comprising the steps of forming a channel oxide film and simultaneously forming a gate insulating film of said MOS transistor. 4. In the step of patterning the first conductive layer to form a stack gate structure, the floating gate is formed in a self-aligned manner using the second conductive layer constituting the control gate as a mask. The method for manufacturing a semiconductor device according to claim 1, wherein patterning is performed. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive layer and the second conductive layer are made of polysilicon. 6. The method according to claim 1, further comprising, after patterning the second conductive layer, forming a side wall on a side surface of the control gate. 7. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming a first metal silicide layer on the second conductive layer. 8. a step of forming a third insulating film on the first metal silicide layer, the third insulating film other than the control gate portion of the stack gate structure, the first metal silicide layer Removing the second conductive layer and the second insulating film to form a control gate portion;  Forming a side wall in the control gate portion; Forming a second metal layer on the exposed first conductive layer and the third insulating film; Forming a recycled layer;  Forming a fourth insulating film on the second metal silicide layer; patterning the fourth insulating film, the second metal silicide layer, and the first conductive layer; Forming a MOS transistor having a single-gate structure, and forming the stack gate structure in a self-aligned manner by etching the first conductive layer using the control gate portion as a mask. 8. The method for manufacturing a semiconductor device according to claim 7, wherein: 9. In a method for manufacturing a semiconductor device having a nonvolatile memory cell, a capacitor and a Z or a resistor, and a logic circuit,  Simultaneously forming a tunnel oxide film of the memory cell and a gate oxide film of an M 0 S transistor of the logic circuit;  Forming a first polysilicon layer over the entire surface of the oxide film; and removing a region of the first polysilicon layer separating the floating gate of the memory cell;  Forming a first insulating film on the first polysilicon layer; forming a second polysilicon layer on the entire surface of the first insulating film; and forming a second polysilicon layer on the second polysilicon layer. Forming a second insulating film; and removing the second insulating film, the second polysilicon layer, and the first insulating film while leaving a desired region of the memory cell and an upper electrode region of the capacitor. Process and  Forming a third insulating film on the entire surface;  Removing the remaining portion of the third insulating film except for the lower electrode region and the resistor region of the capacitor; Anisotropically etching the entire surface and stack gate size of the memory cell A method of manufacturing a semiconductor device, comprising: a step of forming an oar.