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WO2000057550A2 - Systeme, procede et produit de programmation informatique pour la conception automatisee de circuits au moyen d'algorithmes genetiques lineaires - Google Patents

Systeme, procede et produit de programmation informatique pour la conception automatisee de circuits au moyen d'algorithmes genetiques lineaires Download PDF

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WO2000057550A2
WO2000057550A2 PCT/US1999/006369 US9906369W WO0057550A2 WO 2000057550 A2 WO2000057550 A2 WO 2000057550A2 US 9906369 W US9906369 W US 9906369W WO 0057550 A2 WO0057550 A2 WO 0057550A2
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circuit
computer
component
graphs
cast
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WO2000057550A3 (fr
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Jason D. Lohn
Silvano P. Colombano
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level

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  • the field of the present invention relates generally to analog circuit design, and more particularly, to a system and method for automated circuit design using linear genetic algorithms.
  • Analog circuits are of great importance in electronic system design since the world is fundamentally analog in nature. While the amount of digital design activity far outpaces that of analog design, most digital systems require analog modules for interfacing to the external world. It was recently estimated that approximately 60% of CMOS-based application-specific integrated circuit (ASIC) designs incorporated analog circuits (Gielen, G., et al., Symbolic Analysis for Automated Design of Analog Integrated Circuits, Kluwer, Boston, MA (1991)). With challenging analog circuit design problems and fewer analog design engineers, there are economic reasons for automating the analog design process, especially time-to-market considerations.
  • ASIC application-specific integrated circuit
  • the present invention is directed to a linear representation and unfolding technique, coupled with modest computer resources, for evolving analog electronic circuitry, for example, analog filters and transistor-based amplifiers.
  • the system, method or computer program product use a defined, finite set of component-placing instructions capable of placing components in a circuit between an input node and an output node. Each instruction has an opcode specifying the connectivity of an associated component and a component value.
  • a plurality of circuit graphs is generated, and each graph comprises a plurality of the instructions selected by mapping opcode and component values to linear genome segments.
  • the graphs are converted to netlists that are tested in a circuit simulation computer program to isolate one or more evolved circuits that best approximates a fitness function.
  • the invention has the desirable property that all sets of circuit-constructing primitives result in a very high percentage of valid circuit graphs. Thus application of genetic operators will result in valid circuit graphs, while allowing circuit size (number of devices), circuit topology, and device values to be evolved.
  • the present invention is capable of generating a rich set of circuit topologies including many of the useful topologies seen in hand-designed circuits.
  • the present invention minimizes the amount of computer processing and hence run time of the system. Since virtually all of the graph structures generated are valid circuits, the system does not need to perform functions such as the pruning of unconnected circuit branches.
  • the present invention differs from the previously mentioned GA techniques in that the present inventions allow both topology and component sizes to be evolved.
  • the present invention is further distinguished from Zebulum et al. because it employs a linear genetic algorithm. Because the genome resembles a computer program, and because our GA acts upon dynamically-sized representations, it has some elements in common with genetic programming. The genomes in the present invention are fixed to hold a maximum of 150 circuit components, a limit arrived at by surveying the circuit design literature for the various design tasks of interested. Of course, this upper limit can be extended as computations resources are added. Using a cluster of six engineering workstations such as Sun Ultra workstations, manufactured by Sun Microsystems, Palo Alto, California, the inventors have evolved circuit solutions to several circuit designs.
  • Sun Ultra workstations manufactured by Sun Microsystems, Palo Alto, California
  • FIGs. 1A, IB and 1C illustrate the effect of the move-to-new, cast-to- previous and cast-to-ground instructions in accordance with the present invention.
  • FIG.2 illustrates a template circuit: the evolved circuit is located between fixed input and output terminals in accordance with the present invention (v v is an ideal voltage source, R. is the source resistance, R, is the load resistance in accordance with the present invention).
  • FIGs.3 A and 3B illustrate default bipolar junction transistor symbols: (a) npn; (b) pnp.
  • FIGs. 4A and 4B illustrate the labeling of transistor terminals: (a) devices with two terminals have incoming and outgoing terminals; (b) devices with three terminals are treated as two terminal devices by having a fixed connection at the third terminal in accordance with the present invention.
  • FIG.5 illustrates transistor configurations showing the outgoing and fixed connections when the incoming terminal is the transistor's base terminal in accordance with the present invention.
  • FIG. 6 illustrates an overview of the circuit evaluation process starting with circuit constructing instructions and ending with the calculation of fitness in accordance with the present invention.
  • FIG. 7 illustrates the parallelization of a circuit generation technique in accordance with the present invention.
  • FIG.8 illustrates common low-pass filter terminology and specification in accordance with the present invention.
  • FIG. 9 illustrates gain on a logarithmic amplitude scale for a third-order Butterworth filter in accordance with the present invention.
  • FIG. 10A illustrates an evolved low-pass filter for use in an electronic stethoscope in accordance with the present invention (units are ohms and farads).
  • FIG.1 OB illustrates nearly identical frequency response curves for evolved and actual electronic stethoscope circuit in accordance with the present invention (the frequency axis is scaled logarithmically).
  • FIG. 11 A illustrates an evolved 3rd-order Butterworth low-pass filter in accordance with the present invention (units are ohms, farads, and henries.)
  • FIG. 1 IB illustrates a frequency response curve for evolved 3rd-order
  • FIG. 12A illustrates an evolved circuit satisfying target specifications for filter number three in accordance with the present invention.
  • FIG. 12B illustrates a frequency response for filter number three of FIG. 12A in accordance with the present invention.
  • FIG. 13 illustrates an ideal inverting amplifier showing how gain is set by the ratio of the feedback to source resistor.
  • FIG. 14 illustrates a circuit schematic of an evolved 75 dB amplifier in accordance with the present invention.
  • FIGs. 15A, 15B and 15C illustrate a small signal behavior of 75 dB evolved amplifier in accordance with the present invention: 15 A is a time domain input waveform at 1 kHz; 15B is the waveform of 15 A inverted and amplified; and 15C is a frequency response showing 3 dB bandwidth of 7.59 kHz.
  • FIG. 16 illustrates the DC transfer characteristic of the 75 dB amplifier in accordance with FIGs. 15A-C.
  • FIG. 17 illustrates a circuit schematic of an evolved 85 dB amplifier in accordance with the present invention.
  • FIGs. 18A. 18B and 18C illustrate a small signal behavior of the 85 dB evolved amplifier of FIG. 17 in accordance with the present invention: 18A is the time domain input waveform at 1 kHz; 18B is the waveform of 18A inverted and amplified; and 18C is a frequency response showing a flatband gain of 85.46 dB.
  • FIG. 19 illustrates the DC Transfer characteristic of the 85 dB amplifier of FIG 17.
  • FIG. 20 is a block diagram of an exemplary computer system useful for implementing the present invention.
  • the present invention relates to a system, method, and computer program product for automated circuit design using linear genetic algorithms.
  • the present invention is described in terms of various examples. This is for convenience only and is not intended to limit the application of the present invention. In fact, after reading the following description, it will be apparent to one skilled in the relevant art how to implement the following invention in alternative embodiments.
  • the automated circuit design system, method, and computer program product can be implemented by Sun® SPARC® workstations.
  • Other such systems include, for example, Intel® processor-based, IBM compatible PCS, running the Windows 95/98TM or Windows NTTM operating systems, a Macintosh® computer running the Mac® OS operating system, or the like.
  • the present invention may be implemented within any processing device that executes software applications, including, but not limited to, a desktop computer, and the like.
  • Section II presents the evolutionary computation, and in Section III experimental results are presented and analyzed.
  • Section IV is a conclusion.
  • the representation should permit any circuit or at least a wide range of circuits to be represented. If it is known a priori that certain topologies are well-suited to a specific design task, topological restrictions inherent in the representation may be beneficial since the search space will be reduced. Conversely, not having this JO-
  • the genotype conversion algorithm (the circuit constructing process also called the genetic algorithm) should run as fast as possible. Clearly if numerous traversals of the circuit graph structure are required in order to guarantee a valid circuit graph, the performance hit will be commensurate. For an n-component circuit, a reasonable upper bound would be for the algorithm to scale proportionately to the number of circuit components.
  • the representation should be syntactically closed so that genetic operators do not create invalid circuit graphs.
  • a graph could be a valid circuit graph, yet not make sense as an electrical circuit (for example, dissimilar voltage sources connected in parallel) from those that are valid.
  • the circuit representations presented herein were designed to have these properties.
  • Circuit designs are constructed by an automaton that is programmed via a set of low-level instructions.
  • the automaton is called a circuit-constructing robot or cc-bot.
  • the language that programs the cc-bot is small and, in a preferred embodiment of the present invention, contains only component-placing instructions (e.g., control instructions are not included, but could be impletented in an alternative embodiment).
  • the cc-bot is an abstraction that provides a useful construct for visualizing how an evolved circuit is generated by a computers via execution of the cc-bot instructions.
  • the set of cc-bot instructions has the desirable property that virtually all possible sequences of instructions result in a valid electrical circuit. This property is important because it greatly limits the out-of-bounds regions of the search space containing invalid circuit graphs.
  • Each cc-bot instruction places a circuit component and directs the movement of the cc-bot.
  • the five basic cc-bot instruction types are: x-move-to- new, x-cast-to-previous, x-cast-to-ground, -cast-to-input, x-cast-to-output, where x can be replaced by an electronic device, such as a R (resistor), C (capacitor), L (inductor), or transistor configuration.
  • R resistor
  • C capacitor
  • L inductor
  • each cc-bot instruction is summarized in Table I.
  • the "move-to-new” instruction places one end of a component at the active node and the other at a newly created node (the "active" node is the current location being processed by the hypothetical cc-bot). The newly created node then becomes the active node.
  • the "cast-to” instructions place one end of the component at the active node and the other at either the ground, input, output, or previously-created node.
  • the cc-bot remains at the active node.
  • the input and output nodes are the overall input and output nodes of the circuit as opposed to the input and output of the placed component.
  • FIGs. 1 A, IB and 1 C Illustrations of three cc-bot instructions that place components are shown in FIGs. 1 A, IB and 1 C.
  • component xl is connected between active (i.e., current) node CNt and a new node CNt+1 via a move-to-new instruction.
  • component x2 is connected between two existing nodes and CN remains unchanged via a cast-to- previous instruction.
  • componentxJ is connected between existing node CNand ground via a cast-to-ground instruction.
  • the cast-to-input and cast- to-output instructions are very similar to the cast-to-ground instruction.
  • the circuit is constructed by the cc-bot inside of a template circuit.
  • the design tasks presented here use a template having one input and one output terminal as shown in FIG. 2.
  • An ideal voltage source v s is connected to ground and to a source resistor R .
  • the circuit's output voltage is taken across a load resistor R f .
  • the genetic algorithm (GA) used in accordance with the present invention is used to generate variable-length lists of cc-bot instructions (components and component values by mapping bytecodes discussed below) so that the size of the circuit can be evolved.
  • the cc-bot reaches the last component to place in the circuit, the inventors have chosen to have the last active node connected to the output terminal by a wire (accomplished by connection of a 1 micro ohms ( ⁇ ) resistor). By doing so. unconnected branches are eliminated.
  • cc-bot instructions are mapped to bytecodes of the GA.
  • the linear GA can be analogized to a list of pseudo-random numbers that are used to select component/opcode and component values. This is accomplished by mapping opcode and component values to a linear genome segment.
  • each cc-bot instruction is represented by up to four bytecodes of the GA.
  • the first byte is the component/opcode (e.g., a resister cast to ground), and the next three bytes represent the component value (e.g., the resistance value).
  • component/opcode e.g., a resister cast to ground
  • the next three bytes represent the component value (e.g., the resistance value).
  • component values are not needed, because a set of default transistor characteristics is assumed. Using three bytes allows the component values to take on one of 256 3 values, a sufficiently fine-grained resolution. The raw numerical value of these bytes is then scaled into a reasonable range, depending on the type of component.
  • Resistor values can be scaled sigmoidally between 1 and 100K ohms using l/(l+exp(- 1.4(1 Ox- 8))) so that roughly 75% of the resistor can be biased to be less than 10K ohms.
  • Capacitor values can be scaled between approximately 10 picofarads (pF) and 200 microfarads ( ⁇ F) and inductors between roughly 0.1 millihertz (mH) and 1.5 hertz (H.)
  • Transistors are current amplifying and switching devices that have three terminals.
  • the third terminal is hardwired (fixed) to one of the following pre-existing circuit nodes: ground, power supply (positive or negative), input, output, the previously placed node, or even to itself.
  • the terminals are labeled in a generic way: incoming, outgoing, and fixed. These configurations are illustrated in FIG.4A and FIG.4B.
  • the incoming terminal is the terminal that the cc-bot will connect to the active node.
  • the outgoing terminal will become the new active node (for move-to instructions) or it will be cast to a pre-existing circuit node.
  • the fixed terminal is hardwired as its name implies.
  • FIG. 5 illustrates 52 configurations for an npn transistor whose base terminal is designated incoming. Terminals labeled in upper case letters denote the fixed terminal connection. Only npn transistors are shown although analogous configurations are present for pnp transistors in accordance with the present invention.
  • Each entry shows the connections that the cc-bot makes when executing the instruction listed in the first column. The last two columns show self-connections, some of which are frequently used by circuit designers. In the last two columns the fixed connection is a self-connection. "PS” denotes the power supply (only the positive version is shown), and "N.A.” denotes "not applicable”.
  • the cc-bot approach to representing circuits embodies the desirable properties outlined above.
  • the encoding has syntactic closure since any combination of instructions produces a valid circuit graph, and since every instruction contained in the genome results in a circuit component, there are no non-coding genome segments.
  • the circuit construction process is time- proportionate to the number of circuit components since it does not require any repair (e.g., removal of unconnected nodes) operations.
  • the cc-bot approach can generate a wide range of circuit graph topologies.
  • the topological restriction is as follows: circuit branches off of the main constructing thread cannot, in general, contain more than one node (there are some exceptions to this).
  • the constructing thread is the sequence of components that are created by the move-to-new instructions.
  • the constructing thread itself can be of varying lengths and can contain both series and parallel configurations.
  • the evolutionary search employed by the present invention is based on a genetic algorithm (GA).
  • GA of the present invention has some elements in common with genetic programming since the genomes of the invention resemble computer programs and acts upon dynamically-sized representations.
  • the GA operates on a population of dynamically-sized bytecoded arrays.
  • the representation used can increase or decrease in size, as opposed to being of a fixed size.
  • the "size" of a circuit is simply the number of components contained in the circuit. For example, a circuit having five resistors and two capacitors has a size of seven. This allows the representation to represent circuits of any size up to a pre- specified maximum size. Since computers have finite memory storage, a maximum size is enforced so that a circuit that would consume all of the computer's memory is prevented from being represented. This maximum circuit size, or MCS, can be set to whatever value is appropriate for the computer on which the algorithm will execute upon.
  • Providing for dynamic sizing means that the artificial evolution process is able to manipulate the size of a circuit in addition to the connections, component types, and component values. If more components are needed to achieve a desired electronic function, the evolutionary algorithm can increase the size of the circuit. If fewer components are needed, components can be pruned away.
  • Dynamic sizing is implemented by interpreting the first value in the instruction list as the number of components.
  • This first value in the instruction list is called the circuit size value, or CSV.
  • CSV circuit size value
  • the CSV could be greater than the maximum size allowed.
  • a maximum size of about 400 bytes (100-150 circuit components; i.e., one byte to select as instructions opcode and additional bytes to select the opcode's component value) is imposed in order to accommodate population sizes of up to about 18,000 individuals.
  • the crossover rate in a preferred embodiment is set at 0.8 (but can range between 0 and 1 ) and mutation
  • crossover per locus rates set to between about 0.05-0J0.
  • Each crossover is single-point with each parent having a separately chosen crossover point.
  • Crossover points are randomly selected and are constrained to lie on component boundaries to yield circuits having at least ten components and at most about 150 components.
  • Various other acceptable settings parameters and component limits would be apparent to a person skilled in the art without departing from the scope of the present invention.
  • FIG. 6 An overview of the evolution process is depicted in FIG. 6.
  • the present invention employs the public-domain Berkeley SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulation program to simulate generated circuits.
  • the array of bytecodes 602 are interpreted (by decoding as shown at 604) in the manner described in the previous section, and results in a SPICE netlist 606 representation.
  • the netlist is processed by SPICE at 608 and the output from SPICE is then used to compute fitness (at
  • the fitness of a circuit is its ideal or "target "output, measured by voltage, current and or reactance, for example.
  • Other circuit fitness metrics would be apparent to one skilled in the relevant art. Since most of the processing time is spent simulating circuit designs, which are independent of one and other, parallelizing the system is greatly beneficial.
  • the parallel genetic algorithm implemented uses master/slave style parallelism over a network of UNIX-based workstations. (See Goldberg, D.E., Genetic Algorithms in Search, Optimization, and Machine Learning, Addison- Wesley, Reading, MA (1989).)
  • FIG. 7 An exemplary master/slave circuit generation system is illustrated in FIG. 7.
  • a controlling host computer performs GA operators and distributes a population of bytecoded-individuals (i.e.. individual evolved circuits) to specified number of worker nodes using socket connections.
  • the worker nodes decode the individuals into SPICE netlists, which are then fed into SPICE via FIFO pipes to minimize disk activity.
  • Fitness is calculated using SPICE's output, and then sent back to the host. Hundreds of individuals (and fitness scores) are packaged into a single message so that external network congestion delays are minimized.
  • the system currently runs on Sun workstations and a variety of other UNIX systems (e.g. SGI workstations, Silicon
  • Circuit simulation throughput is a key performance metric, and typical throughputs ranged between 100-150 circuits per cpu second (a "central processing unit" second refers to cpu time only and disregards operating system time). For example, in one of the amplifier design task runs described in the next section, each of three processing nodes was able to simulate 142 circuits per cpu second, giving an aggregate processing rate of 426 circuits per cpu second.
  • Amplifiers are very common in analog circuit design and are a good choice for experiments for many of the same reasons that filters are.
  • Transistors are used in the amplifier design experiments since the vast majority of such designs today are transistor-based. All of the evolved designs presented below meet the target specifications. For filters, that meant satisfying four parameters.
  • gain target was a range of values: from 70 dB to the maximum gain attainable for the circuit.
  • Each evolved circuit was hand-probed using simulation software to verify that internal currents and voltages remained at realistic values. This step suggests that these circuits can be physically implemented.
  • a low-pass filter is a circuit the allows low frequencies to pass through it, but stops high frequencies from doing so. In other words, it is frequency selective in that it "filters out” frequencies above a specified frequency.
  • the unshaded area in FIG. 8 depicts the region of operation for low-pass filters. Below the frequency f p the input signal is passed to the output, potentially reduced (attenuated) by K p decibels (dB). This region is known as the passband. Above the frequency , in the region is called the stopband, the input signal is markedly decreased by K s decibels. Between the passband and stopband the frequency response curve transitions from low to high attenuation. The parameter located in this region,/, is known as the cutoff frequency.
  • Amplifier circuits generate an output signal that consists of the input signal multiplied by a gain factor, A.
  • Voltage gain is denoted Av and is equivalent to u i p n vv ft is common to express gain values in decibels (dB) using 20 log(A), where the logarithm is base 10.
  • Amplifiers can be either inverting or non- inverting, where an inverted output signal has a 180 degree phase shift compared to the input.
  • the dc gain of an amplifier refers to the gain when only constant voltage/current sources are applied.
  • the ac or small-signal gain is the gain of an ac input signal irrespective of any dc components in the output signal.
  • a dc component that shifts the entire ac signal up or down is called the dc bias of the circuit.
  • dc bias A dc component that shifts the entire ac signal up or down.
  • the genetic algorithm parameters remained the same within a given experiment, but changed according to the design task to allow for more evaluations (the total number evaluations is the product of population size and the number of generations).
  • Filter 1 runs had 30.000 evaluations, filter 2 had 3.6 million, and filter 3 had 1 million.
  • fitness was calculated to promote the regression of the evolved circuit's frequency response toward that of the target. Error values were computed as the absolute value of the difference of the individual's output and the target output. These error values were summed across evaluation points to arrive at a fitness value.
  • the first filter design task was set up to generate a filter suitable for use in an electronic stethoscope.
  • it is desired to filter out the extraneous high-frequency sounds picked up by a microphone that make it difficult to listen to (low-frequency) bodily sounds (e.g., a heart beating).
  • the frequency response specifications do not need to be extremely accurate since the human ear cannot discern frequencies that are close together.
  • the target frequency response data was taken from an actual electronic stethoscope, which was built with a cutoff frequency of 796 Hz corresponding to an output voltage of approximately 1 volt. This circuit is relatively easy to design and so we chose it as our first design task.
  • the cc-bot instruction set consisted often instructions, five for resistors and five for capacitors, which allowed for the construction of an RC low-pass filter.
  • the evolved circuit is shown in FIG. 10A and its frequency response, which matches almost exactly the target is shown in FIG. 10B. It was found in generation 3 of a 10-generation run that had a population size of 3000.
  • the circuit exhibits the standard design for simple low-pass filters: a resistor (R 2 ) in series with the source to form a voltage divider at low frequencies (C, open), and a capacitor (C,) across the output to block high frequencies.
  • the second low-pass filter design task had specifications that were more difficult to achieve than the first filter: both the passband and stopband were longer thus requiring the transition to be sharper.
  • the inventors chose a circuit that can be built using a 3rd-order Butterworth filter and having a frequency response of the form, as seen in FIG. 9. The specifications are listed under filter number two in Table II. Such a filter design can be derived using a ladder topology containing two capacitors and one inductor and component values found in published tables. Because it was desired to design an LC low-pass filter, the cc-bot instruction set consisted of only capacitor and inductor instructions. The evolved circuit that meets these specifications is shown in FIG. 11A and its frequency response is shown in FIG. 11 B. It was found in generation 22 of a run that had a population size of 18,000.
  • CAPC0002 2 3 3.547581e-05 CAPC0003 3 2 9.862769e-05 RSTR0001 3 2 1.042709e+04 LIND0001 1 3 2.147189e-01 LIND0002 3 2 5.285780e-03 LIND0003 3 4 7.713100e-01 CAPC0004 4 6 2.519509e-05 CAPC0005 0 6 1.048100e-07 LIND0004 i 6 2.008357e-01 RSTR0002 6 7 3.648645e+04 CAPC0006 ⁇ ⁇ 6 1.261844e-04 LIND0005 1 7 2.113217e-01 LIND0006 7 6 1.017696e-03
  • CAPC0007 8 2.449500e-07 LIND0008 7 1.579361e+00 LIND0009 8 3.300694e-01 LIND0010 9 5.376858e-01 CAPC0008 9 2.506300e-07 LIND0011 8 4.863538e-01 LIND0012 10 4.364222e-01 CAPC0009 10 1.256400e-07
  • the magnitude of the gain of the amplifier is simply R B /R S , where R s . is the source resistor.
  • Fitness was calculated in a manner similar to the work on amplifiers in (Koza, J.R., et al, IEEE Trans, on Evolutionary Computation 1(2): X 09- 128 (1997)).
  • An error value is computed as the sum of the dc gain penalty (the target gain minus the observed gain), the dc bias (zero dc bias is ideal), and the degree to which the dc gain is linear.
  • the maximum voltage gain was set at 120 dB (10°).
  • the amplifier having the best performance had a dc gain of 74.53 dB
  • Figure 14 shows the schematic for this circuit. It was found in generation 4866, and had a dc bias of 3.64 volts and a power dissipation of 0.82 watts.
  • the dc behavior can best understood by examining the major current pathways in the circuit.
  • the current through the load is the key quantity since it is converted to a voltage by the load resistor and hence forms the circuit's output.
  • FiG. 15A shows the time domain response. Amplification of a 1 kHz sine wave having a 1 microvolt amplitude can clearly be seen in FIG. 15B.
  • FIG. 15C shows the frequency response. The ac gain remains flat at 74.36 dB until it loses 3 dB at 7.59 kHz (its 3 dB bandwidth).
  • FIG. 16 shows the dc transfer characteristic. The dc bias of 3.64 volts can be seen at the voltage input of zero volts.
  • the maximum voltage gain was set at 100 dB (10 5 ).
  • the amplifier having the best performance had a dc gain of
  • FIG. 17 shows the schematic for this circuit. Itwas found in generation 3635. and had a dc bias of 5.44 volts and a power dissipation of 8J 7 watts.
  • the dc current delivered to the load is mostly supplied by the 15 volt battery attached to the collector of transistor Q7.
  • Transistor Q7 is conducting with the sum of its base and collector currents owing out of its emitter.
  • Q7's base current of 13 mA is supplied by transistor Q6.
  • FIG. 18 A An inverted, amplification signal is illustrated in in FIG. 18B.
  • FIG. 18C shows the frequency response.
  • the circuit has a flat-band gain of 85.46 dB and a 3 dB bandwidth of 282.8 kHz (FIG. 19B).
  • FIG. 19 shows the dc transfer characteristic.
  • the dc bias of 5.44 volts can be seen at the voltage input of zero volts.
  • the slope, the magnitude of which is the gain, is negative since the amplifier is inverting the signal.
  • the present invention may be implemented using hardware, software or a combination thereof and may be implemented in one or more computer systems or other processing systems.
  • the invention is directed toward one or more computer systems capable of carrying out the functionality described herein.
  • An example of a computer system 2000 is shown in FIG.20.
  • the computer system 2000 includes one or more processors, such as processor 2004.
  • the processor 2004 is connected to a communication infrastructure 2006 (e.g., a communications bus, cross-over bar, or network).
  • a communication infrastructure 2006 e.g., a communications bus, cross-over bar, or network.
  • Computer system 2000 can include a display interface 2005 that forwards graphics, text, and other data from the communication infrastructure 2002 (or from a frame buffer not shown) for display on the display unit 2030.
  • Computer system 2000 also includes a main memory 2008, preferably random access memory (RAM), and may also include a secondary memory 2010.
  • the secondary memory 2010 may include, for example, a hard disk drive 2012 and/or a removable storage drive 2014, representing a floppy disk drive, a magnetic tape drive, an optical disk drive, etc.
  • the removable storage drive 2014 reads from and/or writes to a removable storage unit 2018 in a well known manner.
  • Removable storage unit 2018 represents a floppy disk, magnetic tape, optical disk, etc. which is read by and written to by removable storage drive 2014.
  • the removable storage unit 2018 includes a computer usable storage medium having stored therein computer software and/or data.
  • secondary memory 2010 may include other similar means for allowing computer programs or other instructions to be loaded into computer system 2000.
  • Such means may include, for example, a removable storage unit 2022 and an interface 2020. Examples of such may include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM, or PROM) and associated socket, and other removable storage units 2022 and interfaces 2020 which allow software and data to be transferred from the removable storage unit 2022 to computer system 2000.
  • Computer system 2000 may also include a communications interface 2024.
  • Communications interface 2024 allows software and data to be transferred between computer system 2000 and external devices.
  • Examples of communications interface 2024 may include a modem, a network interface (such as an Ethernet card), a communications port, a PCMCIA slot and card, etc.
  • Signal 2028 Software and data transferred via communications interface 2024 are in the form of signals 2028 which may be electronic, electromagnetic, optical or other signals capable of being received by communications interface 2024. These signals 2028 are provided to communications interface 2024 via a communications path (i.e., channel) 2026.
  • This channel 2026 carries signals 2028 and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, an RF link and other communications channels.
  • computer program medium and “computer usable medium” are used to generally refer to media such as removable storage drive 2014. a hard disk installed in hard disk drive 2012. and signals 2028.
  • These computer program products are means for providing software to computer system 2000.
  • the invention is directed to such computer program products.
  • Computer programs are stored in main memory 2008 and/or secondary memory 2010. Computer programs may also be received via communications interface 2024. Such computer programs, when executed, enable the computer system 2000 to perform the features of the present invention as discussed herein. In particular, the computer programs, when executed, enable the processor 2004 to perform the features of the present invention. Accordingly, such computer programs represent controllers of the computer system 2000.
  • the software may be stored in a computer program product and loaded into computer system 2000 using removable storage drive 2014, hard drive 2012 or communications interface 2024.
  • the control logic when executed by the processor 2004, causes the processor 2004 to perform the functions of the invention as described herein.
  • the invention is implemented primarily in hardware using, for example, hardware components such as application specific integrated circuits (ASICs).
  • ASICs application specific integrated circuits
  • the invention is implemented using a combination of both hardware and software.
  • the inventors have demonstrated shown that a linear circuit representation and evolutionary search can automatically produce circuit designs of low to medium difficulty in two applications. Detailed simulations of the designs suggest that all are electrically well-behaved and thus suitable for physical implementation. While the evolved designs presented do not exhibit the level of performance of their hand-designed predecessors, the main point was to show that a new representation technique with many desirable properties could automatically design practical circuits.
  • the circuit representation method devised permits a wide range of circuits to be constructed, and results in a construction process that is unburdened with repair operations.
  • the representation is syntactically closed, making it well-suited for evolutionary search. To gain performance on par with circuits designed by engineers, it will be necessary to place further constraints on the fitness functions. This is an area of future work. With the encouraging results of the system, the inventors are optimistic that a subset of analog circuit design tasks can be routinely accomplished by means of evolutionary computation in the future.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne un système, un procédé et un produit de programmation informatique pour la conception de circuit analogique au moyen d'une technique de représentation génomique linéaire et de dépliement. Un ensemble fini d'instructions de placement de composants est défini, permettant le placement de composants dans un circuit entre un noeud d'entrée et un noeud de sortie. Chaque instruction possède un code d'opération spécifiant la connectivité d'un composant associé et d'une valeur de composant. Plusieurs tracés de circuit sont générés, lesquels comprennent chacun plusieurs instructions sélectionnées par le mappage du code d'opération et des valeur de composant avec des segments génomiques linéaires. Les tracés sont convertis en listes d'interconnexions qui sont testées dans un programme informatique de simulation, de manière qu'un ou plusieurs circuits évolués se rapprochant le plus d'une fonction de cote soient isolés.
PCT/US1999/006369 1999-03-24 1999-03-24 Systeme, procede et produit de programmation informatique pour la conception automatisee de circuits au moyen d'algorithmes genetiques lineaires Ceased WO2000057550A2 (fr)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7370019B2 (en) 2005-06-23 2008-05-06 Ecole Polytechnique Federal De Lausanne Method and device for evolving a network using a genetic representation
US9798846B2 (en) 2015-02-10 2017-10-24 Thalia Design Automation Ltd. Dynamic weighting and ranking of circuit designs for analog circuit design optimization
US10271437B2 (en) 2014-08-14 2019-04-23 The United States Of America As Represented By The Secretary Of The Army Motion-based reconfigurable microelectronics system
CN113381700A (zh) * 2021-06-29 2021-09-10 哈尔滨工业大学 一种高频无源rc积分放大器的rc参数设计方法
WO2024127195A1 (fr) * 2022-12-12 2024-06-20 3M Innovative Properties Company Systèmes, supports et procédés de développement de métasurface

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KOZA, JOHN R. ET AL., "Automated Synhesis of Analog Electrical Circuits by Means of Genetic Programming", in IEEE Transactions on Evolutionary Computation, July 1997, Vol. 1, No. 2, pages 109-128, XP002933065 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7370019B2 (en) 2005-06-23 2008-05-06 Ecole Polytechnique Federal De Lausanne Method and device for evolving a network using a genetic representation
US10271437B2 (en) 2014-08-14 2019-04-23 The United States Of America As Represented By The Secretary Of The Army Motion-based reconfigurable microelectronics system
US11229125B2 (en) 2014-08-14 2022-01-18 The United States Of America As Represented By The Secretary Of The Army Motion-based reconfigurable microelectronics system
US9798846B2 (en) 2015-02-10 2017-10-24 Thalia Design Automation Ltd. Dynamic weighting and ranking of circuit designs for analog circuit design optimization
US10025897B2 (en) 2015-02-10 2018-07-17 Thalia Design Automation Ltd. Generation of circuit design populations for analog circuit design optimization
US10055527B2 (en) 2015-02-10 2018-08-21 Thalia Design Automation Ltd. Yield process for analog circuit design optimization
US10108770B2 (en) 2015-02-10 2018-10-23 Thalia Design Automation Ltd. Corner process for analog circuit design optimization
CN113381700A (zh) * 2021-06-29 2021-09-10 哈尔滨工业大学 一种高频无源rc积分放大器的rc参数设计方法
CN113381700B (zh) * 2021-06-29 2024-01-30 哈尔滨工业大学 一种高频无源rc积分放大器的rc参数设计方法
WO2024127195A1 (fr) * 2022-12-12 2024-06-20 3M Innovative Properties Company Systèmes, supports et procédés de développement de métasurface

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