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WO1999031665A1 - Memory addressing - Google Patents

Memory addressing Download PDF

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Publication number
WO1999031665A1
WO1999031665A1 PCT/IE1998/000104 IE9800104W WO9931665A1 WO 1999031665 A1 WO1999031665 A1 WO 1999031665A1 IE 9800104 W IE9800104 W IE 9800104W WO 9931665 A1 WO9931665 A1 WO 9931665A1
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WO
WIPO (PCT)
Prior art keywords
circuit device
access
address
external processor
registers
Prior art date
Application number
PCT/IE1998/000104
Other languages
French (fr)
Inventor
Kevin Dewar
Original Assignee
Tellabs Research Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tellabs Research Limited filed Critical Tellabs Research Limited
Priority to AU16802/99A priority Critical patent/AU1680299A/en
Priority to EP98961334A priority patent/EP1040483A1/en
Publication of WO1999031665A1 publication Critical patent/WO1999031665A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Definitions

  • the invention relates to memory addressing and/or register addressing, and particularly to internal or external addressing of memory and/or registers associated with a dedicated circuit device such as an ASIC or an FPGA or other dedicated circuit with a requirement for a low level of interaction with an external processor over a small bus.
  • such devices comprise a microprocessor interface to allow an external microprocessor access internal or external memory or registers.
  • an external microprocessor access internal or external memory or registers.
  • it is known to directly memory -map the ASIC registers into the address space of the microprocessor.
  • this may lead to a requirement for a large number of address pins on the ASIC if there are a large number of internal locations.
  • Another object is to provide an interface which is common to a number of different dedicated devices, and to provide a more common accessing method.
  • a still further object is to improve independence of dedicated circuits so that they are more tolerant of processor faults.
  • Another object is to allow handling of larger internal and external address space in a simple and flexible manner.
  • circuit device comprising an external processor interface comprising:-
  • a controller comprising means for connection to actual memory, and means for performing reads and writes to the actual memory using addresses and data written to the access registers via the external processor address and data ports.
  • the controller comprises means for performing a write operation by:-
  • the controller comprises means for performing a read operation by:-
  • the controller comprises means for reading an actual memory address from a plurality of access registers if the address is wider than the address port.
  • the processor interface comprises a plurality of controllers, each connected to interface between the access registers and an associated actual memory.
  • a controller is connected to interface between the access registers and memory external to the circuit device.
  • a controller is connected to interface between the access registers and internal registers.
  • the controller comprises means for automatically incrementing actual memory addresses for efficient access to contiguous blocks.
  • the controller comprises means for disabling actual memory writes until an unlock value is written to an access lock register.
  • the circuit device is an ASIC.
  • the ASIC is an ATM cell processing ASIC.
  • the invention provides a method carried out by a circuit device and an external processor for performing a write operation to a memory associated with the circuit device, the method comprising the steps of:-
  • the external processor writing the address of the memory location to an access register of the circuit device
  • the invention provides a method carried out by a circuit device and an external processor for performing a read operation from a memory associated with the circuit device, the method comprising the steps of:-
  • the external processor writing the address of the memory location to an access register of the circuit device
  • Fig. 1 is an overview schematic representation of an ASIC circuit device connected to a host microprocessor and to external RAM;
  • Fig. 2 is a schematic representation of a microprocessor interface of the ASIC.
  • an ASIC 1 of the invention connected to a host microprocessor 2 and to external RAM 3.
  • the ASIC 1 comprises a microprocessor interface 10 having access registers 11 and a set of memory controllers 12. Other ASIC functions are indicated generally by the numeral 13.
  • the ASIC 1 also includes internal registers 14 which are one byte wide and have a total capacity of 1024 bytes.
  • the interface 10 comprises a UPI 17 which interfaces between external ports and the access registers 1 1.
  • the external ports include a 5-bit address port 18, an 8-bit data port 19, and two control ports 20 and 21.
  • the access registers 17 include address registers, read data registers, a lock register, and auto increment logic.
  • the memory controllers 12 comprise an internal register access controller 12(a) for controlling access to the internal registers 14. They also include an SRAM port controller 12(b) connected to the external memory interface 15 shown in Fig. 1.
  • the controllers 12 include a RAM port controller 12(c), also connected to the external memory interface 15.
  • Fig. 1 also shows a chip boundary 22 and a core boundary 23. In operation, reads and writes are performed by the external processor 2 via the access registers to a set of a larger number of "actual" locations. Reading an actual memory location requires two steps as follows:-
  • a write operation requires two steps as follows:-
  • Summary_Status register which allows important information to be read out directly (i.e. with only a single access).
  • Access_Lock register which allows the device to be write-protected.
  • the internal register access controller 12(a) then performs the write to the register 14 as instructed by the external processor 2 via the access registers 11.
  • the external processor 2 may require the value 55AA55AA to be written to location ABCD05 of the RAM 3.
  • the external processor performs the following writes:-
  • the SRAM port controller 12(b) then uses these writes to perform the actual write to the SRAM 3 via the external memory interface.
  • the access registers are the locations that are directly visible in the top- level address space. Some of these registers are not simple read/write registers. Some locations (and bits within locations) are Read-Only (typically status bits) and other bits/locations are Write Only i.e. they are not real registers but are targets used to initiate some action (e.g. a write to SRAM). Some registers are read/write in the normal sense (i.e. it is possible to read back a value just written) whilst others are bi-directional where they can be used as targets for both read and write operations but what is read is not the most recently written value.
  • Accessing an internal register is accomplished by setting up the address of the register in access registers Reg_Addr_U and Reg_Addr_L and then either writing the required new value to access register Reg_Data (causing this value to be subsequently transferred to the actual internal register) or reading the value of the internal register from Reg_Data (where it will have been copied from the internal register by the act of setting up the address).
  • an address auto-increment feature is implemented. This feature causes an automatic post-increment of the register address or SRAM address following an access to either. This means that to access a contiguous series of registers or SRAM locations it is only necessary to set up the address of the starting location.
  • an Access_Lock register is provided. Writes to internal registers of SRAM will only succeed if the Access_Lock register has previously been written with the UNLOCK value (0xA5). During normal operation, once configuration is complete, the ASIC should be kept locked except for a configuration change. This will minimize the time during which the ASIC is potentially sensitive to a faulty processor or software.
  • stat_b read_access_reg(reg_data);
  • orig_val read_access_reg(ref_data); /* get original value */ write_access_reg(reg_data); /* set lower byte+0x20 again (because of auto-increment) */ write_access_ref(reg_data, orig_val&0xf3); /* sets lower 4 bits to '3' */
  • the invention allows a dedicated device such as an ASIC or an FPGA to require much fewer pins for processor interfacing. It also achieves more consistency in access methods to registers and memory, both internal and external. Another advantage is that it decouples the timing of the external and internal interfaces.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Storage Device Security (AREA)

Abstract

An ASIC circuit device microprocessor interface (10) has a UPI (17) which interfaces between external ports (18-21) and internal access registers (11). The access registers are connected to a RAM port controller (12(c)) and an internal register access controller (12(a)). These controllers interface between the access register (11) and the relevant memory or registers. Reads and writes are performed by an external processor (2) using the access registers (11).

Description

""Memory Addressing"
INTRODUCTION
Field of the Invention
The invention relates to memory addressing and/or register addressing, and particularly to internal or external addressing of memory and/or registers associated with a dedicated circuit device such as an ASIC or an FPGA or other dedicated circuit with a requirement for a low level of interaction with an external processor over a small bus.
Prior Art Discussion
Generally, such devices comprise a microprocessor interface to allow an external microprocessor access internal or external memory or registers. For example, to allow reading and writing of registers within an ASIC, it is known to directly memory -map the ASIC registers into the address space of the microprocessor. However, this may lead to a requirement for a large number of address pins on the ASIC if there are a large number of internal locations.
This requirement also extends to external memory of the ASIC in many instances as there is often a requirement for the microprocessor to access this memory through the ASIC's microprocessor interface. Again, direct memory-mapping can lead to a requirement for a large number of pins on the ASIC.
A problem with these arrangements is that the performance of the dedicated device is linked in a very close manner to that of the processor. This takes away from independence of the ASIC and may lead, for example, to the processor writing incorrect values to the ASIC. For example, if a processor failure results in erroneous writes to the ASIC, there may be severe disruption of operation of the ASIC. Objects of the Invention
It is therefore an object of the invention to provide for memory addressing without the requirement for a large number of address pins on a dedicated device.
Another object is to provide an interface which is common to a number of different dedicated devices, and to provide a more common accessing method.
A still further object is to improve independence of dedicated circuits so that they are more tolerant of processor faults.
Another object is to allow handling of larger internal and external address space in a simple and flexible manner.
SUMMARY OF THE INVENTION
According to the invention, there is provided a circuit device comprising an external processor interface comprising:-
access registers connected to external processor address and data ports; and
a controller comprising means for connection to actual memory, and means for performing reads and writes to the actual memory using addresses and data written to the access registers via the external processor address and data ports.
In one embodiment, the controller comprises means for performing a write operation by:-
reading from an access register the address of an actual memory location, the address being provided by an external processor; reading from an access register the data to be written, the data being provided by the external processor; and
writing the data to the addressed actual memory location.
In another embodiment, the controller comprises means for performing a read operation by:-
reading from an access register the address of an actual memory location provided by the external processor;
reading the data in the addressed actual memory location; and
writing the data to an access register for subsequent reading by the external processor.
Preferably, the controller comprises means for reading an actual memory address from a plurality of access registers if the address is wider than the address port.
In one embodiment, the processor interface comprises a plurality of controllers, each connected to interface between the access registers and an associated actual memory.
In another embodiment, a controller is connected to interface between the access registers and memory external to the circuit device.
In a further embodiment, a controller is connected to interface between the access registers and internal registers.
Preferably, the controller comprises means for automatically incrementing actual memory addresses for efficient access to contiguous blocks. In one embodiment, the controller comprises means for disabling actual memory writes until an unlock value is written to an access lock register.
In one embodiment, the circuit device is an ASIC.
In one embodiment, the ASIC is an ATM cell processing ASIC.
According to another aspect, the invention provides a method carried out by a circuit device and an external processor for performing a write operation to a memory associated with the circuit device, the method comprising the steps of:-
the external processor writing the address of the memory location to an access register of the circuit device;
the external processor writing the write data value to an access register; and
a controller in the circuit device writing the data value to the addressed memory location.
According to a further aspect, the invention provides a method carried out by a circuit device and an external processor for performing a read operation from a memory associated with the circuit device, the method comprising the steps of:-
the external processor writing the address of the memory location to an access register of the circuit device;
a controller in the circuit device reading the value from the addressed memory location; and
the external processor reading back the fetched data value from the access register. DETAILED DESCRIPTION OF THE INVENTION
Brief Description of the Drawings
The invention will be more clearly understood from the following description of some embodiments thereof given by way of example only with reference to the following drawings in which:-
Fig. 1 is an overview schematic representation of an ASIC circuit device connected to a host microprocessor and to external RAM; and
Fig. 2 is a schematic representation of a microprocessor interface of the ASIC.
Description of Embodiments
Referring to the drawings, there is shown an ASIC 1 of the invention connected to a host microprocessor 2 and to external RAM 3. The ASIC 1 comprises a microprocessor interface 10 having access registers 11 and a set of memory controllers 12. Other ASIC functions are indicated generally by the numeral 13. The ASIC 1 also includes internal registers 14 which are one byte wide and have a total capacity of 1024 bytes.
Referring now to Fig. 2, the microprocessor interface 10 is illustrated in more detail. The interface 10 comprises a UPI 17 which interfaces between external ports and the access registers 1 1. The external ports include a 5-bit address port 18, an 8-bit data port 19, and two control ports 20 and 21. The access registers 17 include address registers, read data registers, a lock register, and auto increment logic. The memory controllers 12 comprise an internal register access controller 12(a) for controlling access to the internal registers 14. They also include an SRAM port controller 12(b) connected to the external memory interface 15 shown in Fig. 1. Finally, the controllers 12 include a RAM port controller 12(c), also connected to the external memory interface 15. Fig. 1 also shows a chip boundary 22 and a core boundary 23. In operation, reads and writes are performed by the external processor 2 via the access registers to a set of a larger number of "actual" locations. Reading an actual memory location requires two steps as follows:-
1. writing the address of the actual location into the access registers, and
2. reading the value from the access register which will contain the fetched value from the previously specified address.
A write operation requires two steps as follows:-
1. writing the address of the actual location into the access registers,
2. writing the desired data value to the appropriate access register (for subsequent transfer to the real location).
In more detail, the following is the set of access registers
Figure imgf000009_0001
This set supports four main features:-
1. Summary_Status register which allows important information to be read out directly (i.e. with only a single access).
2. Access_Lock register which allows the device to be write-protected.
Registers to allow access to 8-bit wider internal locations within a 16-bit internal byte-address space. 4. Registers to allow access to SRAM connected externally to the ASIC, with a 32-bit data word and 20-bit word address space.
The following simple examples illustrate the manner in which the access registers 11 are used. For a write of a data value 55 to the location 01 CD of the internal registers 14, the processor 2 performs the following writes:-
01 to access register 02,
CD to access register 03, and
55 to access register 04.
The internal register access controller 12(a) then performs the write to the register 14 as instructed by the external processor 2 via the access registers 11.
In another example, the external processor 2 may require the value 55AA55AA to be written to location ABCD05 of the RAM 3. The external processor performs the following writes:-
AB to access register 10,
CD to access register 11 ,
05 to access register 12,
55 to access register 14,
A A to access register 15,
55 to access register 16, and AA to access register 17.
The SRAM port controller 12(b) then uses these writes to perform the actual write to the SRAM 3 via the external memory interface.
In more detail, the access registers are the locations that are directly visible in the top- level address space. Some of these registers are not simple read/write registers. Some locations (and bits within locations) are Read-Only (typically status bits) and other bits/locations are Write Only i.e. they are not real registers but are targets used to initiate some action (e.g. a write to SRAM). Some registers are read/write in the normal sense (i.e. it is possible to read back a value just written) whilst others are bi-directional where they can be used as targets for both read and write operations but what is read is not the most recently written value.
Accessing an internal register is accomplished by setting up the address of the register in access registers Reg_Addr_U and Reg_Addr_L and then either writing the required new value to access register Reg_Data (causing this value to be subsequently transferred to the actual internal register) or reading the value of the internal register from Reg_Data (where it will have been copied from the internal register by the act of setting up the address).
To allow more efficient access to contiguous blocks of internal registers and external SRAM, an address auto-increment feature is implemented. This feature causes an automatic post-increment of the register address or SRAM address following an access to either. This means that to access a contiguous series of registers or SRAM locations it is only necessary to set up the address of the starting location.
To help protect against accidental corruption of the internal configuration space and the external SRAM by a failed microprocessor (or software), an Access_Lock register is provided. Writes to internal registers of SRAM will only succeed if the Access_Lock register has previously been written with the UNLOCK value (0xA5). During normal operation, once configuration is complete, the ASIC should be kept locked except for a configuration change. This will minimize the time during which the ASIC is potentially sensitive to a faulty processor or software.
The following are detailed examples of how some accesses are performed:
Reading various internal status registers:
/* partial C for accessing internal status registers */ #defιne reg_addr_u 0x02 #defιne reg_addr_l 0x03 #defιne reg_data 0x04
/* read status registers at addresses 0 -> 7 */ write_access_reg (reg_addr_u,0x00); /* set upper bit=0 */ write_access_reg (reg_addr_l,0x00); /* set lower byte=0 */ for (i=0; i<7; i++) status_array[i] = read_access_reg(reg_data); /* do read and take advantage of auto- increment */
/* now read status at addresses Ox la and 0x7c */ write_access_reg(reg_addr_l,0xla); /* set lower byte=0x la (knowing that upper bit still = 0) */ stat_a = read_access_reg(reg_data); write_access_reg(ref_addr_l ,0x7c; /* set lower byte=0x7c (knowing that upper bit still
= 0) */ stat_b = read_access_reg(reg_data);
Writing various configuration registers: /* partial C for setting configuration registers */
/* initialize registers at addresses 0x12 - 0x15 */
/* assumes that we have previously unlocked the AccessJLock reg */
write_access_reg(reg_addr_u,0x00); /* set upper bit=0 */ write_access_reg(reg_addr_l,0xl2); /* set lower byte= 12 */ write_access_reg(reg_data,0x04); /* write 0x04 to 0x12 */ write_access_reg(reg_data,0x05); /* write 0x05 to 0x13 (take advantage of auto- increment) */ write_access_reg(reg_data,0x06); /* write 0x06 to 0x14 (take advantage of auto- increment) */ write_access_reg(reg_data,0x07); /* write 0x07 to 0x15 (take advantage of auto- increment) */
/* set lower 4 bits of reg at address 0x20 (leave upper 4 unchanged) */ write_access_reg(reg_addr_l,0x20); /* set lower byte=0x20 (knowing that upper bit still
= 0) */ orig_val = read_access_reg(ref_data); /* get original value */ write_access_reg(reg_data); /* set lower byte+0x20 again (because of auto-increment) */ write_access_ref(reg_data, orig_val&0xf3); /* sets lower 4 bits to '3' */
It will be appreciated that the invention allows a dedicated device such as an ASIC or an FPGA to require much fewer pins for processor interfacing. It also achieves more consistency in access methods to registers and memory, both internal and external. Another advantage is that it decouples the timing of the external and internal interfaces.
The invention is not limited to the embodiments described, but may be varied in construction and detail within the scope of the claims.

Claims

Claims
1. A circuit device comprising an external processor interface comprising:-
access registers connected to external processor address and data ports; and
a controller comprising means for connection to actual memory, and means for performing reads and writes to the actual memory using addresses and data written to the access registers via the external processor address and data ports..
2. A circuit device as claimed in claim 1, wherein the controller comprises means for performing a write operation by:-
reading from an access register the address of an actual memory location, the address being provided by an external processor;
reading from an access register the data to be written, the data being provided by the external processor; and
writing the data to the addressed actual memory location.
3. A circuit device as claimed in claims 1 or 2. wherein the controller comprises means for performing a read operation by:
reading from an access register the address of an actual memory location provided by the external processor;
reading the data in the addressed actual memory location; and writing the data to an access register for subsequent reading by the external processor.
4. A circuit device as claimed in any preceding claim, wherein the controller comprises means for reading an actual memory address from a plurality of access registers if the address is wider than the address port.
5. A circuit device as claimed in any preceding claim, wherein the processor interface comprises a plurality of controllers, each connected to interface between the access registers and an associated actual memory.
6. A circuit device as claimed in claim 5, wherein a controller is connected to interface between the access registers and memory external to the circuit device.
7. A circuit device as claimed in claim 6, wherein a controller is connected to interface between the access registers and internal registers.
8. A circuit device as claimed in any preceding claim, wherein the controller comprises means for automatically incrementing actual memory addresses for efficient access to contiguous blocks.
9. A circuit device as claimed in any preceding claim, wherein the controller comprises means for disabling actual memory writes until an unlock value is written to an access lock register.
10. A circuit device as claimed in any preceding claim, wherein the circuit device is an ASIC.
11. A circuit device as claimed in claim 10, wherein the ASIC is an ATM cell processing ASIC.
12. A method carried out by a circuit device and an external processor for performing a write operation to a memory associated with a circuit device, the method comprising the steps of:-
the external processor writing the address of the memory location to an access register of the circuit device,
the external processor writing the write data value to an access register, and
a controller in the circuit device writing the data value to the addressed memory location.
13. A method carried out by a circuit device and an external processor for performing a read operation from a memory associated with a circuit device, the method comprising the steps of:-
the external processor writing the address of the memory location to an access register of the circuit device,
a controller in the circuit device reading the value from the addressed memory location, and
the external processor reading back the fetched data value from the access register.
PCT/IE1998/000104 1997-12-15 1998-12-15 Memory addressing WO1999031665A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU16802/99A AU1680299A (en) 1997-12-15 1998-12-15 Memory addressing
EP98961334A EP1040483A1 (en) 1997-12-15 1998-12-15 Memory addressing

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
IE970886 1997-12-15
IE970886 1997-12-15
IES980710 1998-08-31
IES980710 IES80916B2 (en) 1997-12-15 1998-08-31 Memory addressing

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US9015516B2 (en) 2011-07-18 2015-04-21 Hewlett-Packard Development Company, L.P. Storing event data and a time value in memory with an event logging module

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US5243703A (en) * 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
US5537353A (en) * 1995-08-31 1996-07-16 Cirrus Logic, Inc. Low pin count-wide memory devices and systems and methods using the same
GB2306238A (en) * 1995-10-10 1997-04-30 Holtek Microelectronics Inc Interface circuit and method for memory access
EP0803816A2 (en) * 1996-04-24 1997-10-29 Cirrus Logic, Inc. A memory system with multiplexed input-output port and memory mapping capability and systems and methods using the same

Patent Citations (4)

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US5243703A (en) * 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
US5537353A (en) * 1995-08-31 1996-07-16 Cirrus Logic, Inc. Low pin count-wide memory devices and systems and methods using the same
GB2306238A (en) * 1995-10-10 1997-04-30 Holtek Microelectronics Inc Interface circuit and method for memory access
EP0803816A2 (en) * 1996-04-24 1997-10-29 Cirrus Logic, Inc. A memory system with multiplexed input-output port and memory mapping capability and systems and methods using the same

Cited By (4)

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US9015516B2 (en) 2011-07-18 2015-04-21 Hewlett-Packard Development Company, L.P. Storing event data and a time value in memory with an event logging module
US9418027B2 (en) 2011-07-18 2016-08-16 Hewlett Packard Enterprise Development Lp Secure boot information with validation control data specifying a validation technique
US9465755B2 (en) 2011-07-18 2016-10-11 Hewlett Packard Enterprise Development Lp Security parameter zeroization
US9483422B2 (en) 2011-07-18 2016-11-01 Hewlett Packard Enterprise Development Lp Access to memory region including confidential information

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Publication number Publication date
IES980710A2 (en) 1999-06-30
AU1680299A (en) 1999-07-05
EP1040483A1 (en) 2000-10-04
IES80916B2 (en) 1999-06-30

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