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WO1998034268A3 - Procede de fabrication de circuits integres aux dimensions reduites - Google Patents

Procede de fabrication de circuits integres aux dimensions reduites Download PDF

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Publication number
WO1998034268A3
WO1998034268A3 PCT/US1998/001942 US9801942W WO9834268A3 WO 1998034268 A3 WO1998034268 A3 WO 1998034268A3 US 9801942 W US9801942 W US 9801942W WO 9834268 A3 WO9834268 A3 WO 9834268A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuits
fabrication
crystalline silicon
reduced
fabrication method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1998/001942
Other languages
English (en)
Other versions
WO1998034268A2 (fr
Inventor
Somit Talwar
Karl-Josef Kramer
Guarav Verma
Kurt Weiner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ultratech Inc
Original Assignee
Ultratech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ultratech Inc filed Critical Ultratech Inc
Priority to EP98909985A priority Critical patent/EP1012879B1/fr
Priority to KR10-1999-7006907A priority patent/KR100511765B1/ko
Priority to DE69807718T priority patent/DE69807718T2/de
Priority to JP53316598A priority patent/JP2001509316A/ja
Publication of WO1998034268A2 publication Critical patent/WO1998034268A2/fr
Publication of WO1998034268A3 publication Critical patent/WO1998034268A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/061—Gettering-armorphous layers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

La pré-amorphisation d'une couche superficielle de silicium cristallin sur une infime épaisseur (p.ex., inférieure à 100 nm) apporte une solution aux problèmes de fabrication au moyen (1) d'une haute conduction thermique dans le silicium cristallin et (2) d'effets d'ombrage et de télescopage des diffractions par une porte déjà fabriquée d'un transistor à effet de champ sur rayonnement laser incident. Dans le passé, ces problèmes ont empêché d'utiliser efficacement le dopage laser par immersion de gaz de projection, de la technique antérieure, dans la fabrication de circuits intégrés comprenant des transistors à effet de champ MOS utilisant une technologie de jonction au 100 nm, voire encore moins.
PCT/US1998/001942 1997-01-31 1998-01-29 Procede de fabrication de circuits integres aux dimensions reduites Ceased WO1998034268A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP98909985A EP1012879B1 (fr) 1997-01-31 1998-01-29 Procede de fabrication de circuits integres aux dimensions reduites
KR10-1999-7006907A KR100511765B1 (ko) 1997-01-31 1998-01-29 소형 집적회로의 제조방법
DE69807718T DE69807718T2 (de) 1997-01-31 1998-01-29 Herstellungsverfahren für integrierte schaltkreise mit reduzierter dimension
JP53316598A JP2001509316A (ja) 1997-01-31 1998-01-29 低減寸法集積回路の製造法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/792,107 US5908307A (en) 1997-01-31 1997-01-31 Fabrication method for reduced-dimension FET devices
US08/792,107 1997-01-31

Publications (2)

Publication Number Publication Date
WO1998034268A2 WO1998034268A2 (fr) 1998-08-06
WO1998034268A3 true WO1998034268A3 (fr) 1999-02-18

Family

ID=25155818

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/001942 Ceased WO1998034268A2 (fr) 1997-01-31 1998-01-29 Procede de fabrication de circuits integres aux dimensions reduites

Country Status (6)

Country Link
US (1) US5908307A (fr)
EP (1) EP1012879B1 (fr)
JP (1) JP2001509316A (fr)
KR (1) KR100511765B1 (fr)
DE (1) DE69807718T2 (fr)
WO (1) WO1998034268A2 (fr)

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US6037640A (en) * 1997-11-12 2000-03-14 International Business Machines Corporation Ultra-shallow semiconductor junction formation
US5956603A (en) * 1998-08-27 1999-09-21 Ultratech Stepper, Inc. Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits
US6355543B1 (en) * 1998-09-29 2002-03-12 Advanced Micro Devices, Inc. Laser annealing for forming shallow source/drain extension for MOS transistor
US6297115B1 (en) * 1998-11-06 2001-10-02 Advanced Micro Devices, Inc. Cmos processs with low thermal budget
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EP1012879A4 (fr) 2000-06-28
EP1012879B1 (fr) 2002-09-04
JP2001509316A (ja) 2001-07-10
KR20000070658A (ko) 2000-11-25
WO1998034268A2 (fr) 1998-08-06
DE69807718D1 (de) 2002-10-10
DE69807718T2 (de) 2003-07-31
KR100511765B1 (ko) 2005-09-05
US5908307A (en) 1999-06-01
EP1012879A2 (fr) 2000-06-28

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