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WO1996008868A3 - Delay unit and transmission system using such a delay unit - Google Patents

Delay unit and transmission system using such a delay unit Download PDF

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Publication number
WO1996008868A3
WO1996008868A3 PCT/IB1995/000739 IB9500739W WO9608868A3 WO 1996008868 A3 WO1996008868 A3 WO 1996008868A3 IB 9500739 W IB9500739 W IB 9500739W WO 9608868 A3 WO9608868 A3 WO 9608868A3
Authority
WO
WIPO (PCT)
Prior art keywords
delay unit
transmission system
control signal
signal controlling
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB1995/000739
Other languages
French (fr)
Other versions
WO1996008868A2 (en
Inventor
De Vries Hendricus The Penning
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Philips Norden AB
Original Assignee
Philips Electronics NV
Philips Norden AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV, Philips Norden AB filed Critical Philips Electronics NV
Priority to JP8510043A priority Critical patent/JPH09505966A/en
Priority to EP95929185A priority patent/EP0729671A1/en
Publication of WO1996008868A2 publication Critical patent/WO1996008868A2/en
Publication of WO1996008868A3 publication Critical patent/WO1996008868A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/0026—Layout of the delay element using circuits having two logic levels using memories or FIFO's

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

In a delay element (2) according to the prior art, comprising a FIFO (2) it is only possible to obtain a delay value which is equal to an integer number of symbol periods. By using a phase shifter (8) for obtaining an arbitrary phase shift between a write control signal controlling a write operation of the FIFO memory and a read control signal controlling a read operation of the FIFO memory, a delay value being not an integer value of the symbol period can be obtained.
PCT/IB1995/000739 1994-09-15 1995-09-06 Delay unit and transmission system using such a delay unit Ceased WO1996008868A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8510043A JPH09505966A (en) 1994-09-15 1995-09-06 Delay unit and transmission system using such delay unit
EP95929185A EP0729671A1 (en) 1994-09-15 1995-09-06 Delay unit and transmission system using such a delay unit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP94202662 1994-09-15
EP94202662.6 1994-09-15

Publications (2)

Publication Number Publication Date
WO1996008868A2 WO1996008868A2 (en) 1996-03-21
WO1996008868A3 true WO1996008868A3 (en) 1996-05-30

Family

ID=8217197

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1995/000739 Ceased WO1996008868A2 (en) 1994-09-15 1995-09-06 Delay unit and transmission system using such a delay unit

Country Status (3)

Country Link
EP (1) EP0729671A1 (en)
CN (1) CN1137845A (en)
WO (1) WO1996008868A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5974103A (en) * 1996-07-01 1999-10-26 Sun Microsystems, Inc. Deterministic exchange of data between synchronised systems separated by a distance
DE19908929A1 (en) * 1999-03-02 2000-09-21 Headroom Videotechnik Gmbh Process for the synchronization of a transmission device in telecommunications technology
KR100624296B1 (en) * 2004-11-08 2006-09-19 주식회사 하이닉스반도체 Semiconductor memory device
DE102012211178B4 (en) 2011-06-29 2022-06-30 Skyworks Solutions, Inc. Dynamic time alignment of audio signals in simulcast radio receivers
CN105262462B (en) * 2015-10-21 2018-03-20 圣邦微电子（北京）股份有限公司 A kind of digital delay implementation method and circuit for integrated circuit
CN109900971B (en) * 2017-12-11 2023-01-24 长鑫存储技术有限公司 Pulse signal processing method and device and semiconductor memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
US5015872A (en) * 1988-07-06 1991-05-14 Ant Nachrichtentechnik Gmbh Method and circuit arrangement for generating a phase shifted clock pulse signal
US5272694A (en) * 1991-03-21 1993-12-21 France Telecom Synchronization of terminal stations in a multirate half-duplex tree-structured network

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
US5015872A (en) * 1988-07-06 1991-05-14 Ant Nachrichtentechnik Gmbh Method and circuit arrangement for generating a phase shifted clock pulse signal
US5272694A (en) * 1991-03-21 1993-12-21 France Telecom Synchronization of terminal stations in a multirate half-duplex tree-structured network

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, Volume 19, No. 8, January 1977, W.F. MCCARTHY et al., "High-Frequency Analog Electronic Delay Using Phase-Locked-Loop Techniques", page 3131 - page 3132. *
PATENT ABSTRACTS OF JAPAN, Vol. 13, No. 198, E-756; & JP,A,1 019 822, (NEC. CORP.), 23 January 1989. *

Also Published As

Publication number Publication date
CN1137845A (en) 1996-12-11
EP0729671A1 (en) 1996-09-04
WO1996008868A2 (en) 1996-03-21

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