[go: up one dir, main page]

WO1996008036A1 - Procede de fabrication de structures micromecaniques au moyen d'une technique d'attaque par ions reactifs - Google Patents

Procede de fabrication de structures micromecaniques au moyen d'une technique d'attaque par ions reactifs Download PDF

Info

Publication number
WO1996008036A1
WO1996008036A1 PCT/NL1995/000221 NL9500221W WO9608036A1 WO 1996008036 A1 WO1996008036 A1 WO 1996008036A1 NL 9500221 W NL9500221 W NL 9500221W WO 9608036 A1 WO9608036 A1 WO 9608036A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
etching
etch gas
etched
process according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/NL1995/000221
Other languages
English (en)
Inventor
Henricus Venantius Jansen
Meint Jelle De Boer
Rob Legtenberg
Job Elders
Michael Curt Elwenspoek
Johannes Hermanus Josephus Fluitman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stichting voor de Technische Wetenschappen STW
Original Assignee
Stichting voor de Technische Wetenschappen STW
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stichting voor de Technische Wetenschappen STW filed Critical Stichting voor de Technische Wetenschappen STW
Priority to AU26839/95A priority Critical patent/AU2683995A/en
Publication of WO1996008036A1 publication Critical patent/WO1996008036A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00626—Processes for achieving a desired geometry not provided for in groups B81C1/00563 - B81C1/00619
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C99/00—Subject matter not provided for in other groups of this subclass
    • B81C99/0055—Manufacturing logistics
    • B81C99/0065—Process control; Yield prediction
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y15/00—Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0132—Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0135—Controlling etch progression
    • B81C2201/0138—Monitoring physical parameters in the etching chamber, e.g. pressure, temperature or gas composition

Definitions

  • the invention relates to a process for producing micro(electro)mechanical structures in a substrate using standard Reactive Ion Etching (RIE), wherein the substrate is etched with a silicon etch gas mixture.
  • RIE Reactive Ion Etching
  • the invention relates in particular to such a RIE process that can be carried out in a single run.
  • Plasma etching can be divided into three main groups; the physical ion beam etching (IBE), the synergetic reactive ion etching (REE), and the chemical plasma etching (PE).
  • IBE physical ion beam etching
  • REE synergetic reactive ion etching
  • PE chemical plasma etching
  • IBE shows only positively tapered profiles, low etch rates, and low selectivity
  • PE gives rise to isotropic profiles, high etch rates, and high selectivity.
  • RLE it is possible to provide the plasma with a chemical etchant for the etching of the substrate, a passivator for blocking the etching at the sidewalls of a trench, and an ion source for the local removal of the passivation layer at the bottom of the etching trenches.
  • RLE processes which use the deposition of a passivating film are called: ion-inhibitor RIE.
  • etching polymers When etching polymers, it is not necessary to passivate the trench sidewalls. In these cases the etching is possible because of ion bombardment. This is a typical reactive ion beam etching (RIBE) process, but can also be fulfilled at higher pressures with an RIE apparatus. RIE processes which use only the incoming ions are called; ion-induced RIE. To increase the etch rate, standard RIE is modified to create a higher density plasma [1-6], but these etchers are expensive and therefore less attractive. Normally, halogen-based plasmas are used for the chemical etching of silicon, because of their high etch rates [1-13]. Except for the fluorine-based plasmas, these gases are particularly hazardous (e.g.
  • the passivation layer can be grown: 1 from polymer precursors which are lead into the plasma [8-10], 2 by resputtering mask material [11], 3 by inserting gases which act as an oxidant (forming siliconoxyhalogen) [1,12,13], or 4 by freezing the normally volatile reaction products of the silicon with the radicals at the trench walls [3,4].
  • the deposition of a halocarbon polymer film has the disadvantage that this film is thermally less stable than a growing inorganic siliconoxyhalogen film and the freezing of reaction products uses the expensive (cryogenic) coolers.
  • the resputtering of mask material is not acceptable because areas which should stay clean are also contaminated.
  • the passivating film is very thin the incoming ions should not be highly energetic, so the selectivity will be very high and the substrate damage will be low. Also, because of the low energy of the ions, trenching and faceting are not found and it is very easy to change the direction of the impinging ions thus changing the etched profile.
  • a major problem during etching silicon vertically is the forming of "grass" on the silicon surface, because of all kinds of micromasks deposited or grown on the silicon.
  • low pressure oxygen plasmas are' used for etching polymers.
  • such a plasma creates a high d.c. self-bias voltage which is responsible for substrate- and mask-damage.
  • etching a polymer in low pressure RIE identical grass problems are observed as in the case of etching silicon.
  • Etching rates and profiles are observed to depend on feature size (i.e. aspect ratio dependent etching: ARDE) and pattern density (i.e. microloading) for Si, SiO 2 , polymers, metals and group III-V elements also referred to as microscopic non-uniformities [15].
  • feature size i.e. aspect ratio dependent etching: ARDE
  • pattern density i.e. microloading
  • MEMS electronic mechanical systems
  • RIE Reactive Ion Etching
  • RIE reactive ion etching
  • a third object ⁇ f the present invention is to achieve highly controllable trench profiles by means of standard RIE.
  • a next object of the present invention is to achieve high etch rates with good uniformity over the wafer.
  • a further object of the invention is to use high pressure RIE (> 50 mTorr) during the trench etching in order to obtain very low d.c. self-bias voltages (down to 10 V) in order to prevent electronics already in the substrate to be damaged. Due to the low bias voltage it is easy to bend the incoming ions to the sidewalls in order to create all kinds of profiles.
  • the ion energy is between 10 en 90 eV, preferably between 10 and 50, particularly between 10 and 20 eV. Such low voltages are unique for relative simple RIE equipments. As a further important advantage of the low ion energy, the very high mask selectivity is mentioned. So only very thin metal layers ( ⁇ 50 nm) will suffice to etch deep trenches.
  • a still further object of the invention is to add CHF 3 or another halocarbon in to the SF g 0 2 plasma to prevent the forming of grass to get very smooth sidewalls and bottoms. At the same time it is possible to control the trench profile very easy and accurate with this halocarbon adding.
  • Another object of the present invention is to use the Black Silicon Method together with the profiles and d.c. bias voltage diagrams. The diagrams include the influence of the oxygen and CHF 3 content and the influence of the power and pressure on the trench profile and d.c. bias voltage. Herein, the formation of "grass" is used to find the desired profile.
  • Yet another object is to prevent ARDE effects such as RIE lag and sidewall bowing by varying the gas mixture while using the BSM.
  • the tip radius is smaller than 5 nm while using an insulating mask for the tip mask [17].
  • the one-run multi-step process proposed according to the invention is a more sophisticated dry release technique able to extend the limits of microtechnology.
  • a MEM comb-driven xy-stage is given.
  • very deep trenches up to 200 ⁇ m
  • high aspect ratios of about 10 or higher
  • silicon and polymers can be etched using a fluorine-based plasma, such as SF 6 0 2 /CHF 3 .
  • Isotropic, positively and negatively (i.e. reverse) tapered as well as tully vertical walls with smooth surfaces are achieved in silicon or in polymers by controlling the plasma chemistry, which is independent of crystal orientation and doping.
  • a convenient way to find the processing conditions needed for a vertical wall is described: the Black Silicon Method. This new procedure is checked for three different Reactive Ion
  • MEMS can be manufactured in a on-run multi-step dry REE process which uses e.g. commercially available silicon on insulator (SOI) wafers.
  • SOI silicon on insulator
  • the process comprises, after step b), the step of: c) etching the floor of the primary microstructure using said first silicon etch gas.
  • the process according to the invention further comprises the step of: e) depositing a halocarbon film on the surface of the final microstructure.
  • each gas has a specific function and influence, so the etched profile is easily controlled just by changing the flow rate of one of these gases.
  • SF 6 produces the F* radicals for the chemical etching of the silicon forming the volatile SiF 4
  • O 2 creates the O* radicals to passivate the silicon surface with SiO ⁇ F
  • CHF 3 (or another halocarbon) is the source for the CF ⁇ + (or other halocarbon) ions which etch the SiO ⁇ F layer in one direction forming the volatile CO ⁇ F y .
  • SF X + ions are also able to remove the oxyfluoride by way of the volatile SO ⁇ F gases, but the SF 6 flow is fixed on the 0 2 flow to ensure a vertical wall.
  • the CHF 3 gas is a nearly independent source of oxyfluoride etching ions.
  • the SF 6 O 2 /CHF 3 chemistry allows etching of highly controllable profiles in silicon at very low ion energies (10-90eV) and high etch rates (up to 5 ⁇ m/min).
  • the low ion energy prevents substrate damage (electronics), mask erosion (the selectivity to metal masks is practically infinite), and makes it easy to change the profile of the trench.
  • the ion energy is ruled by the potential which is developed between the plasma and the powered electrode; the d.c. self-bias.
  • the d.c. self-bias decreases when the power decreases or the pressure increases.
  • the pressure may be e.g.
  • SF 6 /O 2 /CHF 3 plasma is described here as suitable for the process of the invention, the process also works with other silicon etch gases e.g. CF , NF 3 , SiF 4 , CF 3 Br, CC1 4 or Cl 2 .
  • silicon etch gases e.g. CF , NF 3 , SiF 4 , CF 3 Br, CC1 4 or Cl 2 .
  • every plasma mixture which consists of a chemical etchant, a passivator and an ion source can be used, even when the substrate is not silicon, but e.g. a polymer.
  • trifluoromethane (CHF 3 ) can be used as a source of
  • CHal ⁇ * species examples include other halomethanes and haloethanes containing a plurality of fluorine and/or chlorine atoms, preferably fluorine atoms. If the halocarbon does not contain hydrogen atoms (such as CF 4 and C 2 F 6 ), it is preferred that hydrogen (H ⁇ is added.
  • the silicon loading of the substrate should be sufficiently high, e.g. at least 10%. If the substrate has a lower silicon loading, additional silicon may be added to the etching chamber in any form.
  • the present process can also be used for etching polymer structures such as polyimides, polycarbonates, polyacrylates (PMMA) and polystyrene.
  • THE BLACK SILICON METHOD A strong method is found to determine the vertical profile regime. This method uses the fact that the silicon is turned black when the vertical wall recipe is found. This method will be called the "Black Silicon Method". Before the Black Silicon Method is formulated below, the reason for this effect will be explained and a way to get rid of this blackening will be described. The origin of black silicon: As stated, there is a constant competition between the fluorine radicals that etch and the oxygen radicals that passivate the silicon. At a certain oxygen content there is such a balance between the etching and the passivation that a nearly vertical wall results.
  • spikes will appear.
  • These spikes consist of a silicon body with a thin passivating siliconoxyfluoride skin. They will become higher in time and, depending on the etch rate, they will exceed the wavelength of incoming light after some time. This light will be "caught” in the areas between the spikes and cannot leave the silicon surface any more. So, all the light is collected by the etching surface and it is turned into black. In fact, this optical diffuser could be used for all kinds of applications where the reflection of light from the surrounding is not desired, e.g. laser applications or sunlight collectors.
  • An etched silicon piece under directional conditions may result in spikes which are 50 ⁇ m in height and a few ⁇ m in width.
  • the origin of micromasks is caused by native oxide, dust, and so on, which is already on the wafer before etching. However, they are also formed during the etching because silicon oxide particles coming from the plasma are ad ⁇ sorbing at the silicon surface or because of the oxidation of the silicon surface together with the angle dependent ion etching of this oxide layer.
  • Another source of particles during etching which will act as micromasks is the resputtering of mask material due to imparting ions.
  • Preventing black silicon Spikes which are formed because of dirty wafers before etching are easily controlled by giving the wafer a precleaning step. For instance, native oxide can be removed with the help of an HF dip and dust is less a problem when using the lift-off technique in applying the mask layer, instead of the normally used chemical etching of the mask material with the help of a resist pattern.
  • the micromasks which originate during etching must be controlled in a different way. First of all, the resputtering of mask material can be suppressed when the ion energy is low or when the right materials are chosen.
  • the silicon oxide particles are less a problem when the selectivity between the silicon and the silicon oxide is minimised, but this only occurs when the incoming ions are highly energetic and at these moments the process is not favourable any more because of substrate damage and the just mentioned mask erosion.
  • it is possible to prevent spikes from forming by constantly underetching the micromasks isotropically or etching the features with a slightly negative undercut.
  • the isotropic solution makes only sense when it is used as a post etch, because otherwise the feature density is limited.
  • the negative underetching is an excellent way to control the smoothness of the substrate surface barely limiting the feature size density.
  • CHF 3 to an SF 6 /0 2 plasma is described and its ability to prevent grass.
  • Yet another approach to attack the grass problem is the application of different masks.
  • the Black Silicon Method is tested for three different REE systems. Most experiments are performed with a plan parallel plate reactor "plasmafab 340" from the STS company and a second plan parallel plate single wafer reactor “plasmathe ⁇ n 500" showed identical results.
  • a third system, the hexode "AME-8100" from Applied Materials, is used for the batch fabrication of silicon wafers and is also able to achieve vertical profiles.
  • the etch rates are approximately one order in magnitude lower than for the single wafer etchers and for this reason less powerful. This is because the wafers are much longer exposed to the aggressive plasma chemistry giving rise to surface roughening when etching very deep trenches in silicon. The etch rate can be increased by decreasing the reactor loading.
  • Sharp positively tapered silicon tips for AFM applications can be fabricated with the BSM in allowing a controllable underetching. It is possible to fabricate spikes having an aspect ratio of 50 or more and a tip radius smaller than 5 nm. To achieve such sharp tips a remarkable phenomena is used which occurs during the REE of these tips. When an insulating mask is used for the pattern transfer, this mask will slip over after the mask is completely underetched. This is caused by electrostatic forces which exist during the REE of silicon. This mask is protecting the sharp tip after that moment from incoming energetic ions, so overetching is not a big problem.
  • the Black Silicon Method was developed for silicon trench etching, but it is found that this method works for polymer trench etching as well. Although the appearance of a polymer surface after anisotropic etching is not black but rather diffuse, the mechanism is the same. For this reason a more general name for this method is chosen; the Black Substrate Method. THE BLACK SILICON METHOD (BSM) MULTI-STEP ONE-RUN To solve the problems connected with releasing the etched microstructures, a new technique has been developed which has the ability to etch, passivate, and release MEMS in one run. This technique, the so-called BSM multi-step one-run process, is developed on an Electrotech, Plasmafab 310-340 twin deposition/etch parallel-plate system operating at 13.56 MHz, but is not restricted to that system.
  • the technique starts with commercially available SOI (Silicon On Insulator) wafers. After the deposition of a 30 nm (lift-off) mask for the pattern definition, the movable structures can be fabricated in only one RIE run with four individual steps): 1) The (an)isotropic REE (SF f /O ⁇ /CHF ⁇ of the top Si, 2) the REE (CHF 3 ) of the insulator together with the passivation (C ⁇ F y film) of the sidewalls of the structures, 3) the REE (SF 6 /O 2 /CHF 3 ) of the floor, and 4) the REE (SF 6 ) of the bulk Si.
  • SOI Silicon On Insulator
  • the process can be finished with a conformal step coverage of a C ⁇ F film to protect the released structures from the environment [14].
  • these fluorocarbon (FC) films do have an extremely low surface tension and therefore they repel water and others. With this technique it is possible to release long thin Si beams successfully. Examples of the steps are summarised below:
  • SIMPLE Silicon Micromachining by single step PLasma
  • Anisotropic etching The profile has to be vertical with a little underetch making it possible to deposit a FC layer where no ion bombardment occurs i.e. under the "roof of the mask.
  • the profile can be adjusted by using the BSM method. Also RIE-lag can be suppressed by applying this method.
  • the etch process has to be stopped, to avoid unwanted under etching. This is a crucial step because when the SiO 2 is reached, the loading is decreasing causing a strong enhancement in lateral etching. The etching process is stopped by e.g. visual inspection.
  • FC is a function of e.g. pressure and self-bias. This layer is protection the sidewalls during isotropic etching.
  • power flux 0.3 W/cm 2
  • self-bias 40 V
  • pressure 75 mTorr
  • Isotropic etching Before starting the isotropic etching with an SF 6 plasma it is necessary to "clear" the floor of the trenches first with an oxygen-based plasma such as SF 6 O 2 /CHF 3 .
  • BSM SISI A disadvantage of the BSM SOI technique is that -after releasing the free hanging structures- deep trenches are found and the under etch rate is limited due to the relatively high Si loading.
  • SISI Silicon on Insulator on Silicon on Insulator
  • BSM SCS This technique is strongly correlated to the SCREAM process [9]. Differences are that the BSM SCS process is fluorine-based whereas the SCREAM process is chlorine-based and the passivation of the sidewalls is different. SCREAM uses Si0 2 which is deposited with a different apparatus and stress could be a notorious problem. BSM SCS uses "in-situ" deposited fluorocarbon (FC) to protect the sidewalls. FC has a low Youngs modulus of elasticity and therefore it does not suffer from stress effects like bending or buckling.
  • BSM EPI This technique is related to the SIMPLE process [16]. However, SIMPLE is chlorine-based whereas BSM EPI is fluorine-based. Advantages of fluorine over chlorine is the much higher under etch rate for fluorine-based plasmas. Moreover, the doping level is not restricted to highly doped arsenic (As) as a doping impurity.
  • the present invention is directed to a new and unique process for the fabrication of deep trenches in to a substrate using a non-toxic and non-hazardous, preferably fluorine-based mixture in an inexpensive "standard" reactive ion etcher with excellent profile control, high aspect ratio, high etch rates, good uniformity, high selectivity, low surface-damage and -roughening.
  • the process provides a significant advantage in the manufacture of deep trenches at very low d.c. bias voltages for their use in e.g. submicron transistor trench isolation, MEMS applications (e.g. electrostatic actuators or smart sensors), and the fabrication of cheap silicon or polymer-based moulds.
  • MEMS applications e.g. electrostatic actuators or smart sensors
  • the formation of grass can be used positively in sunlight collectors and anti-reflection coatings for e.g. laser applications.
  • the BSM multi-step one-run process is favourable for the releasing of MEMS with long thin beams. It includes the Black Silicon Method as an excellent tool for profile control and to suppress RIE-lag. Instead of SiO 2 , a thin metal (30 nm Cr) layer is used as a mask, which has an almost infinite selectivity with respect to Si and creates less additional stress problems (bending).
  • the fluorocarbon layer has a low Young's modulus which prevents stress problems in long thin beams (buckling).
  • the intermediate layer of SOI prevents the beam for hollowing out during the isotropic etch making an exact definition of the structure height possible.
  • Wafers which are purposely not cleaned or even oxidised in an oxygen plasma and etched in the Black Silicon Regime can be used as an optical diffuser for e.g. laser applications. It is possible to create spikes at well-defined locations in order to form a tip for the use in AFM applications.
  • FIG 1 a micromachined xy -stage is shown. The structure is etched during one run with standard REE. After the directional etching, the sidewalls are passivated using a low pressure CHF3 plasma and the xy stage is etched free with the help of an isotropic SF 6 plasma.
  • the structure is passivated with a fluorocarbon layer using a high pressure CHF 3 plasma [14].
  • CHF 3 plasma a high pressure CHF 3 plasma [14].
  • the Black Silicon Method is described for the SF 6 /O 2 /CHF 3 plasma, it will also works for other silicon etch gases e.g. CF 4 , NF 3 , SiF 4 , CF 3 Br, CC1 4 or Cl 2 .
  • every plasma mixture which consists of a chemical etchant, a passivator and an ion source can be used for the Black Silicon Method, even when the substrate is not silicon at all but e.g. a polymer. All together it is shown that the Black Silicon Method is a very strong tool for etching high structures with excellent profile control using an SF 6 /0 2 /CHF 3 plasma.
  • the black silicon method is a powerful tool in finding recipes for the fabrication of MEMS building blocks (trenches, needles) such as, scanning probe tips, multi-electrodes for neuroelectronic interfaces, micro filtration systems, shadow masks, suspensions for rigid disk data storage, micromoulds, submicron trenches for IC- applications, gratings for biomedical and optical applications, membrane structures for tunable ER filters, integration of sensors and actuators with Integrated-circuits and components for liquid handling systems (e.g. pumps valves)
  • MEMS building blocks such as, scanning probe tips, multi-electrodes for neuroelectronic interfaces, micro filtration systems, shadow masks, suspensions for rigid disk data storage, micromoulds, submicron trenches for IC- applications, gratings for biomedical and optical applications, membrane structures for tunable ER filters, integration of sensors and actuators with Integrated-circuits and components for liquid handling systems (e.g. pumps valves)
  • deep trenches can be etched in silicon or polymers using the SF 0 2 gas mixture to which CHF 3 or another halocarbon may be added. If desired, the silicon etch process is independent of crystal orientation and doping.
  • deep trenches can be etched in silicon or polymers with excellent profile control. Isotropic, positively and negatively (i.e. reverse) tapered as well as fully vertical walls are achieved by controlling the plasma chemistry (i.e the gas flows, the pressure, and the power density).
  • deep trenches can be etched in silicon or polymers with aspect ratios ranging of at least 10, or in case of polymers, up to 20 or even 30.
  • cryogenic cooling and/or new plasma sources such as Inductively Coupled Plasma (ICP)
  • ICP Inductively Coupled Plasma
  • Etch rates ranging up to 5 microns per minute and an etch uniformity better than 5%. over the wafer can be achieved.
  • deep trenches can be etched in silicon or polymers with mask selectivity greater than 10,000 or even greater than 100,000 for metals and greater than a thousand for silicon dioxide.
  • the deep trenches can be obtained in silicon or polymers with a surface roughness lower than 100 nm of trenches more than 100 microns deep.
  • Devices can also be passivated completely with a halocarbon polymer using a high pressure CHF 3 or other halocarbon plasma.
  • the deposition can be performed at the target plates (i.e. the powered electrode) of the REE, in the plasma glow, or downstream.
  • the properties of the deposited coating/polymer can be varied as desired.
  • Silicon sunlight collectors can be manufactured, wherein the surface etched is completely black as a result of the black silicon regime.
  • the black silicon absorbs all the incoming light, making a high efficiency sunlight collector.
  • Another use of the black silicon is as an anti-reflection coating in e.g. laser applications.
  • micromachined xy-stage is shown fabricated with the help of the BSM
  • FIG. 2 shows the essential steps of the present process.
  • deep submicron trench isolation for e.g. vertical transistors can be etched.
  • An important feature of the invention is the very low bias voltage which is needed to create these openings, and as a result, electronics are not damaged during the trench etching.
  • the present process also allows the production of moulds for duplication applications. For these applications slightly positively tapered moulds are needed with a low surface roughness. Release of the mould is made much easier by the deposit of an anti- sticking layer on top of the freshly etched silicon mould. After the filling and hardening of the duplication polymer in the silicon mould, the duplication polymer is released easily because of the low adhesion of the anti-sticking layer.
  • the anti-sticking layer can be deposited with e.g. the same RIE apparatus, using the halocarbon plasma described above.
  • Scanning probe tips, needles All kinds of tips can be created with profiles and radii on request for AFM, STM, MFM applications. Sharp positively tapered silicon tips for AFM applications can be fabricated with the BSM in allowing a controllable under etching. It is possible to fabricate spikes having an aspect ratio of 50 or more and a tip radius smaller than 5 nm. Changing the chemistry in a different direction (eg. more CHF3) creates negatively tapered profiles. These probes can be used for filter or MFM applications. The same approach can be used for fabrication of an array of needles for 3D neuro-electronic interface devices for neuromuscular control and also needles for injection of DNA into cells can be fabricated.
  • Microfiltration systems Micro filtration sieve membrane sieve for industrial and biomedical applications.(e.g inkjet filters for printers, blood filtration, beer filtration)) Shadow masks: For the fabrication of high resolution mask patterning in deep holes and its application to an electrical wafer feed through.
  • Suspensions for rigid disk storage media Silicon micromachined slider suspension with integrated friction forces sensors for rigid disk storage media.
  • Micromoulds A variety of mould inserts (in polymers, semiconductors, metals, insulators) can be fabricated, either for electroplating and/or for moulding and embossing processes. These mouldings can also be used for direct patterning in polymers. For instance for filter applications
  • Gratings Gratings with dimensions of 0.1 micron up to hundreds of microns for bio-medical applications and optical applications can be constructed.
  • Suhmicron structures Submicron trench etching for IC-applications (DRAM, SRAM devices).
  • the black silicon one run process is a powerful tool for the fabrication of movable structures for micro electromechanical systems (MEMS) using single crystalline silicon (SCS) substrates, polymer substrates, metal substrates (Ti) or multilayer substrates (e.g. SOI, BESOI, SIMOX, epiwafers with buried layers and SISI multilayer wafers).
  • SCS single crystalline silicon
  • Ti metal substrates
  • multilayer substrates e.g. SOI, BESOI, SIMOX, epiwafers with buried layers and SISI multilayer wafers.
  • electrostatically driven xy-stages for AFM, STM, MFM and XPS applications and stepping motors for high resolution positioning over large distance;
  • Other examples are accelerometers with displacement sensor, electrostatic voltameter, static friction sensor, impact test sensor, resonant microstructure, electromechanical filter, vibromotor optical shutter, tuning fork rate gyroscopes, electromechanical transistor, microgrippers, fibercutters, logic elements., micromotors, microturbines, robotics, active joints, microflies, microphones, microrelays, microswitches, and gas flow meters.
  • Starting wafer p- or n-type, e.g. 300 microns thick SCS, SOI or EPI.
  • a thin (e.g. 50 nm) metal layer e.g. Cr, Al, Ni, or Y
  • a thin metal layer e.g. Cr, Al, Ni, or Y
  • a pure SF 6 (or other fluorine-based) plasma is started, optionally mixed with nitrogen or oxygen to increase fluorine atom concentration in the plasma and thus the etch rate.
  • SF 6 or other fluorine-based plasma
  • nitrogen or oxygen to increase fluorine atom concentration in the plasma and thus the etch rate.
  • Figure 1 shows a micromachined xy stage etched withe help of the present Black
  • Step i deposition and patenting mask
  • step ⁇ anisotropic etching
  • step iii deposition PECVD oxide protection
  • step iv local reomval
  • FIG. 3 is diagram showing the influence of power, pressure and flow on the profile.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Automation & Control Theory (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé de fabrication de structures micromécaniques attaquées chimiquement au moyen d'une technique d'attaque par ions réactifs (RIE) qui consiste à attaquer un substrat à l'aide d'un mélange de gaz d'attaque de silicium, de sorte qu'un rapport de forme d'au moins 10 soit obtenu. Ce procédé comprend les étapes suivantes: a) attaque anisotrope au moyen d'un premier gaz d'attaque de silicium, pour la production d'une microstructure primaire; b) dépôt d'une pellicule d'hydrocarbure halogéné sur les parois de la microstructure primaire; d) attaque isotrope au moyen d'un deuxième gaz d'attaque de silicium, pour la production d'une microstructure finale; lesdites étapes étant réalisées en une seule opération. D'autres étapes éventuelles consistent à: c) attaquer le plancher de la microstructure primaire au moyen dudit premier gaz d'attaque de silicium; e) déposer une pellicule d'hydrocarbure halogéné sur la surface de la microstructure finale. On peut éventuellement appliquer une pression élevée (5 - 30 Pa) et une énergie faible (10-90 eV) et utiliser, de préférence, un plasma d'hexafluorure de soufre/oxygène/trifluorométhane. On peut commander le procédé en contrôlant le noircissement d'une surface de silicium d'essai en fonction de la variation des paramètres de traitement.
PCT/NL1995/000221 1994-09-02 1995-06-22 Procede de fabrication de structures micromecaniques au moyen d'une technique d'attaque par ions reactifs Ceased WO1996008036A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU26839/95A AU2683995A (en) 1994-09-02 1995-06-22 Process for producing micromechanical structures by means of reactive ion etching

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP94202519.8 1994-09-02
EP94202519 1994-09-02

Publications (1)

Publication Number Publication Date
WO1996008036A1 true WO1996008036A1 (fr) 1996-03-14

Family

ID=8217159

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/NL1995/000221 Ceased WO1996008036A1 (fr) 1994-09-02 1995-06-22 Procede de fabrication de structures micromecaniques au moyen d'une technique d'attaque par ions reactifs

Country Status (2)

Country Link
AU (1) AU2683995A (fr)
WO (1) WO1996008036A1 (fr)

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0879635A1 (fr) * 1997-05-24 1998-11-25 Koninklijke Grolsch N.V. Dispositif pour filtrer un liquide fermenté
WO2000017095A1 (fr) * 1998-09-24 2000-03-30 Infineon Technologies Ag Structure de controle pour la fabrication d'espaces creux ou de zones de gravure sous-jacente dans des composants micromecaniques et/ou microelectroniques
DE19847455A1 (de) * 1998-10-15 2000-04-27 Bosch Gmbh Robert Verfahren zur Bearbeitung von Silizium mittels Ätzprozessen
US6084257A (en) * 1995-05-24 2000-07-04 Lucas Novasensor Single crystal silicon sensor with high aspect ratio and curvilinear structures
EP0964456A3 (fr) * 1998-06-09 2000-08-09 Siemens Aktiengesellschaft Condensateur à sillon profond
WO2000016041A3 (fr) * 1998-09-12 2000-09-28 Secr Defence Formation de barreaux suspendus au moyen de substrats soi et application a la fabrication d'un gyrometre vibrant
WO2001011666A3 (fr) * 1999-08-11 2001-08-16 Adc Telecommunications Inc Procede d'attaque de couche de tranche au moyen des couches multiples du meme materiau photoresistant et structure ainsi formee
US6316796B1 (en) 1995-05-24 2001-11-13 Lucas Novasensor Single crystal silicon sensor with high aspect ratio and curvilinear structures
WO2002029858A3 (fr) * 2000-09-29 2003-02-13 Infineon Technologies Corp Procede de gravure de tranchees profondes destine a reduire ou eliminer la formation de silicium noir
EP1316993A1 (fr) * 2001-11-29 2003-06-04 Denselight Semiconductors Pte Ltd. Gravure de semi-conducteurs
WO2002062698A3 (fr) * 2001-02-06 2003-07-17 Bosch Gmbh Robert Procede de realisation de structures superficielles micromecaniques, et capteur
RU2211504C1 (ru) * 2002-07-25 2003-08-27 Государственное образовательное учреждение высшего и послевузовского образования Нижегородский государственный технический университет Способ изготовления упругих элементов из монокристаллического кремния
WO2004016547A1 (fr) * 2002-08-02 2004-02-26 Robert Bosch Gmbh Procede pour fabriquer un dispositif micromecanique, notamment un miroir oscillant micromecanique
EP1220010A3 (fr) * 2000-12-29 2004-10-27 Texas Instruments Incorporated Méthodes de revêtement des dispositifs microméchaniques
US6946362B2 (en) 2002-09-06 2005-09-20 Hewlett-Packard Development Company, L.P. Method and apparatus for forming high surface area material films and membranes
WO2007051313A1 (fr) * 2005-11-07 2007-05-10 Fibics Incorporated Procedes de montage de circuits au moyen de faisceaux electroniques a faible energie d'impact
WO2007042521A3 (fr) * 2005-10-10 2008-06-12 X Fab Semiconductor Foundries Production de nanostructures en aiguilles auto-organisees et utilisations diverses de ces nanostructures
EP1786027A3 (fr) * 2005-11-14 2009-03-04 Schott AG Gravure au plasma de structures coniques
EP1827871A4 (fr) * 2004-12-23 2009-09-16 Lam Res Corp Procedes destines a eliminer du silicium noir et du carbure de silicium noir de surfaces d'electrodes de silicium et de carbure de silicium pour des appareils de traitement au plasma
EP1325884B1 (fr) * 2001-12-18 2010-02-17 Samsung Electronics Co., Ltd. Structure MEMS ayant un support/ancre fixe dans la couche sacrificielle, et sa méthode de fabrication
US7709285B2 (en) 2003-10-31 2010-05-04 Epcos Ag Method of manufacturing a MEMS device and MEMS device
US8058086B2 (en) 2005-10-10 2011-11-15 X-Fab Semiconductor Foundries Ag Self-organized pin-type nanostructures, and production thereof on silicon
RU2648287C1 (ru) * 2016-12-27 2018-03-23 Акционерное общество "Научно-исследовательский институт физических измерений" Способ изготовления упругих элементов микромеханических датчиков
RU2662499C1 (ru) * 2017-09-01 2018-07-26 Общество ограниченной ответственности "Игла" Способ изготовления микромеханических элементов из пластин монокристаллического кремния
RU2695771C1 (ru) * 2018-12-29 2019-07-25 Общество с ограниченной ответственностью "Игла" Способ изготовления микроиглы в интегральном исполнении с внутренними каналами
WO2021064070A1 (fr) * 2019-10-04 2021-04-08 Photonik-Zentrum Kaiserslautern e.V. Structuration d'une surface d'un matériau optique actif
CN112768348A (zh) * 2021-01-18 2021-05-07 复旦大学 一种铌酸锂材料刻蚀及提高侧壁角度的优化方法
CN114879458A (zh) * 2022-05-31 2022-08-09 上海稷以科技有限公司 一种改善谐振腔牺牲层释放效率的方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3627311A1 (de) * 1985-08-23 1987-02-26 Intel Corp Verfahren zum aetzen von silizium
US4968585A (en) * 1989-06-20 1990-11-06 The Board Of Trustees Of The Leland Stanford Jr. University Microfabricated cantilever stylus with integrated conical tip
EP0413040A1 (fr) * 1989-08-16 1991-02-20 International Business Machines Corporation Méthode de production de pointes ultrafines en silicium pour la profilométrie AFM/STM
US5198390A (en) * 1992-01-16 1993-03-30 Cornell Research Foundation, Inc. RIE process for fabricating submicron, silicon electromechanical structures
US5201992A (en) * 1990-07-12 1993-04-13 Bell Communications Research, Inc. Method for making tapered microminiature silicon structures
EP0536968A2 (fr) * 1991-10-08 1993-04-14 Nec Corporation Procédé de formation de trous de contact pendant la fabrication de composants semi-conducteurs
EP0565212A2 (fr) * 1986-12-19 1993-10-13 Applied Materials, Inc. Procédé de décapage par iodine pour silicium et silicides
US5268070A (en) * 1991-01-22 1993-12-07 Sony Corporation Dry etching method
DE4317623A1 (de) * 1993-05-27 1994-12-01 Bosch Gmbh Robert Verfahren und Vorrichtung zum anisotropen Plasmaätzen von Substraten

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3627311A1 (de) * 1985-08-23 1987-02-26 Intel Corp Verfahren zum aetzen von silizium
EP0565212A2 (fr) * 1986-12-19 1993-10-13 Applied Materials, Inc. Procédé de décapage par iodine pour silicium et silicides
US4968585A (en) * 1989-06-20 1990-11-06 The Board Of Trustees Of The Leland Stanford Jr. University Microfabricated cantilever stylus with integrated conical tip
EP0413040A1 (fr) * 1989-08-16 1991-02-20 International Business Machines Corporation Méthode de production de pointes ultrafines en silicium pour la profilométrie AFM/STM
US5201992A (en) * 1990-07-12 1993-04-13 Bell Communications Research, Inc. Method for making tapered microminiature silicon structures
US5268070A (en) * 1991-01-22 1993-12-07 Sony Corporation Dry etching method
EP0536968A2 (fr) * 1991-10-08 1993-04-14 Nec Corporation Procédé de formation de trous de contact pendant la fabrication de composants semi-conducteurs
US5198390A (en) * 1992-01-16 1993-03-30 Cornell Research Foundation, Inc. RIE process for fabricating submicron, silicon electromechanical structures
DE4317623A1 (de) * 1993-05-27 1994-12-01 Bosch Gmbh Robert Verfahren und Vorrichtung zum anisotropen Plasmaätzen von Substraten

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
DAVIS R J: "IMAGE POTENTIALS AND THE DRY ETCHING OF SUBMICRON TRENCHES WITH LOW -ENERGY IONS", APPLIED PHYSICS LETTERS, vol. 59, no. 14, 30 September 1991 (1991-09-30), pages 1717 - 1719, XP000250007 *
MASAYUKI SATO: "LOW DAMAGE MAGNETRON ENHANCED REACTIVE ION ETCHING", JAPANESE JOURNAL OF APPLIED PHYSICS, SUPPLEMENTS, 27 August 1991 (1991-08-27), pages 225 - 227, XP000279447 *
TSENGYOU SYAU ET AL: "REACTIVE ION ETCHING OF SILICON TRENCHES USING SF6/O2 GAS MIXTURES", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, vol. 138, no. 10, 1 October 1991 (1991-10-01), pages 3076 - 3081, XP000248018 *

Cited By (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6316796B1 (en) 1995-05-24 2001-11-13 Lucas Novasensor Single crystal silicon sensor with high aspect ratio and curvilinear structures
US6084257A (en) * 1995-05-24 2000-07-04 Lucas Novasensor Single crystal silicon sensor with high aspect ratio and curvilinear structures
NL1006118C2 (nl) * 1997-05-24 1998-11-25 Koninkl Grolsch N V Inrichting voor het filtreren van een gefermenteerde vloeistof.
EP0879635A1 (fr) * 1997-05-24 1998-11-25 Koninklijke Grolsch N.V. Dispositif pour filtrer un liquide fermenté
EP0964456A3 (fr) * 1998-06-09 2000-08-09 Siemens Aktiengesellschaft Condensateur à sillon profond
US6103585A (en) * 1998-06-09 2000-08-15 Siemens Aktiengesellschaft Method of forming deep trench capacitors
WO2000016041A3 (fr) * 1998-09-12 2000-09-28 Secr Defence Formation de barreaux suspendus au moyen de substrats soi et application a la fabrication d'un gyrometre vibrant
US6276205B1 (en) 1998-09-12 2001-08-21 The Secretary Of State For Defence In Her Britanic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Micro-machining
EP1808672A3 (fr) * 1998-09-12 2009-06-17 Qinetiq Limited Améliorations concernant le micro-usinage
WO2000017095A1 (fr) * 1998-09-24 2000-03-30 Infineon Technologies Ag Structure de controle pour la fabrication d'espaces creux ou de zones de gravure sous-jacente dans des composants micromecaniques et/ou microelectroniques
DE19847455A1 (de) * 1998-10-15 2000-04-27 Bosch Gmbh Robert Verfahren zur Bearbeitung von Silizium mittels Ätzprozessen
US6469361B2 (en) 1999-08-11 2002-10-22 Adc Telecommunications, Inc. Semiconductor wafer
US6316282B1 (en) 1999-08-11 2001-11-13 Adc Telecommunications, Inc. Method of etching a wafer layer using multiple layers of the same photoresistant material
WO2001011666A3 (fr) * 1999-08-11 2001-08-16 Adc Telecommunications Inc Procede d'attaque de couche de tranche au moyen des couches multiples du meme materiau photoresistant et structure ainsi formee
WO2002029858A3 (fr) * 2000-09-29 2003-02-13 Infineon Technologies Corp Procede de gravure de tranchees profondes destine a reduire ou eliminer la formation de silicium noir
EP1220010A3 (fr) * 2000-12-29 2004-10-27 Texas Instruments Incorporated Méthodes de revêtement des dispositifs microméchaniques
US7651734B2 (en) 2000-12-29 2010-01-26 Texas Instruments Incorporated Micromechanical device fabrication
WO2002062698A3 (fr) * 2001-02-06 2003-07-17 Bosch Gmbh Robert Procede de realisation de structures superficielles micromecaniques, et capteur
US6867061B2 (en) 2001-02-06 2005-03-15 Robert Bosch Gmbh Method for producing surface micromechanical structures, and sensor
EP1316993A1 (fr) * 2001-11-29 2003-06-04 Denselight Semiconductors Pte Ltd. Gravure de semi-conducteurs
EP1325884B1 (fr) * 2001-12-18 2010-02-17 Samsung Electronics Co., Ltd. Structure MEMS ayant un support/ancre fixe dans la couche sacrificielle, et sa méthode de fabrication
RU2211504C1 (ru) * 2002-07-25 2003-08-27 Государственное образовательное учреждение высшего и послевузовского образования Нижегородский государственный технический университет Способ изготовления упругих элементов из монокристаллического кремния
WO2004016547A1 (fr) * 2002-08-02 2004-02-26 Robert Bosch Gmbh Procede pour fabriquer un dispositif micromecanique, notamment un miroir oscillant micromecanique
US7261825B2 (en) 2002-08-02 2007-08-28 Robert Bosch Gmbh Method for the production of a micromechanical device, particularly a micromechanical oscillating mirror device
US6946362B2 (en) 2002-09-06 2005-09-20 Hewlett-Packard Development Company, L.P. Method and apparatus for forming high surface area material films and membranes
US7709285B2 (en) 2003-10-31 2010-05-04 Epcos Ag Method of manufacturing a MEMS device and MEMS device
EP1827871A4 (fr) * 2004-12-23 2009-09-16 Lam Res Corp Procedes destines a eliminer du silicium noir et du carbure de silicium noir de surfaces d'electrodes de silicium et de carbure de silicium pour des appareils de traitement au plasma
US8058086B2 (en) 2005-10-10 2011-11-15 X-Fab Semiconductor Foundries Ag Self-organized pin-type nanostructures, and production thereof on silicon
WO2007042521A3 (fr) * 2005-10-10 2008-06-12 X Fab Semiconductor Foundries Production de nanostructures en aiguilles auto-organisees et utilisations diverses de ces nanostructures
US8350209B2 (en) 2005-10-10 2013-01-08 X-Fab Semiconductor Foundries Ag Production of self-organized pin-type nanostructures, and the rather extensive applications thereof
WO2007051313A1 (fr) * 2005-11-07 2007-05-10 Fibics Incorporated Procedes de montage de circuits au moyen de faisceaux electroniques a faible energie d'impact
US8466415B2 (en) 2005-11-07 2013-06-18 Fibics Incorporated Methods for performing circuit edit operations with low landing energy electron beams
EP1786027A3 (fr) * 2005-11-14 2009-03-04 Schott AG Gravure au plasma de structures coniques
RU2648287C1 (ru) * 2016-12-27 2018-03-23 Акционерное общество "Научно-исследовательский институт физических измерений" Способ изготовления упругих элементов микромеханических датчиков
RU2662499C1 (ru) * 2017-09-01 2018-07-26 Общество ограниченной ответственности "Игла" Способ изготовления микромеханических элементов из пластин монокристаллического кремния
RU2695771C1 (ru) * 2018-12-29 2019-07-25 Общество с ограниченной ответственностью "Игла" Способ изготовления микроиглы в интегральном исполнении с внутренними каналами
WO2021064070A1 (fr) * 2019-10-04 2021-04-08 Photonik-Zentrum Kaiserslautern e.V. Structuration d'une surface d'un matériau optique actif
CN112768348A (zh) * 2021-01-18 2021-05-07 复旦大学 一种铌酸锂材料刻蚀及提高侧壁角度的优化方法
CN112768348B (zh) * 2021-01-18 2022-05-20 复旦大学 一种铌酸锂材料刻蚀及提高侧壁角度的优化方法
CN114879458A (zh) * 2022-05-31 2022-08-09 上海稷以科技有限公司 一种改善谐振腔牺牲层释放效率的方法

Also Published As

Publication number Publication date
AU2683995A (en) 1996-03-27

Similar Documents

Publication Publication Date Title
WO1996008036A1 (fr) Procede de fabrication de structures micromecaniques au moyen d'une technique d'attaque par ions reactifs
Jansen et al. The black silicon method: a universal method for determining the parameter setting of a fluorine-based reactive ion etcher in deep silicon trench etching with profile control
US6808953B2 (en) Gap tuning for surface micromachined structures in an epitaxial reactor
US7618548B2 (en) Silicon-containing structure with deep etched features, and method of manufacture
Elwenspoek et al. Silicon micromachining
Rangelow Dry etching-based silicon micro-machining for MEMS
Lee et al. Thermal annealing in hydrogen for 3-D profile transformation on silicon-on-insulator and sidewall roughness reduction
US6355181B1 (en) Method and apparatus for manufacturing a micromechanical device
US20180065844A1 (en) Material Structure and Method for Deep Silicon Carbide Etching
Guckel et al. Advances in processing techniques for silicon micromechanical devices with smooth surfaces
WO2006138126A2 (fr) Substrat antifrottement statique pour systeme micro-electromecanique et procede de fabrication
US6998059B2 (en) Method for manufacturing a silicon sensor and a silicon sensor
Easter et al. Characterization of High-Pressure $\hbox {XeF} _ {2} $ Vapor-Phase Silicon Etching for MEMS Processing
WO2005071721A1 (fr) Procede de gravure au plasma
US10570010B1 (en) Fabrication of multilayered carbon MEMS devices
Subasinghe et al. High aspect ratio plasma etching of bulk lead zirconate titanate
Ganji et al. Deep trenches in silicon structure using DRIE method with aluminum as an etching mask
O'Brien et al. Submicron high-aspect-ratio silicon beam etch
US20140322918A1 (en) Micro-posts having improved uniformity and a method of manufacture thereof
EP1241703B1 (fr) Procédé de masquage de silicium pour la gravure anisotrope par voie humide
Bogue Developments in advanced silicon etching techniques by STS Systems
O’Brien et al. Deep Reactive Ion Etched Submicron Beam/Trench Characterization
Vrtacnik et al. Thin FC film for sidewall passivation in SCREAM process for MEMS
Paul et al. Plasma etching processes for the realization of micromechanical structures for MEMS.(MoO3) x thin films.
Sasaki Silicon etching for multiple-height microstructures

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AM AT AU BB BG BR BY CA CH CN CZ DE DK EE ES FI GB GE HU IS JP KE KG KP KR KZ LK LR LT LU LV MD MG MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TT UA UG US UZ VN

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): KE MW SD SZ UG AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

NENP Non-entry into the national phase

Ref country code: CA

122 Ep: pct application non-entry in european phase