WO1994000877A1 - Process for producing a storage capacitor - Google Patents

Abstract

The process of the invention makes it possible for capacitors for storage cells with a capacitor arranged above the transistor to be produced. A dish or can-shaped cross-section endows the capacitor with a high capacitance. The process is distinguished especially by its reliability. A layer of polysilicon (31) is used as an etch stop for the self-aligning etching of the storage capacitor contact. The open sides are oxidised (31') or covered by side spacers (39).

Description

 Manufacturing method for a memory ondensator

The invention relates to a manufacturing method for a capacitor of a one-transistor memory cell on a semiconductor substrate, which is arranged above the transistor, and wherein the transistor has a source, drain and gate as well as a source connection and a drain connection and the drain connection with a bit line is connected.

DRAM semiconductor memories consist of a number of memory cells in or on a semiconductor substrate consisting, for example, of silicon, which are each composed of a capacitor for storing the information and a transistor for selecting the specific capacitor. In order to achieve a short access time and the required space in the case of a memory offer, the integration of the arrangement must be discussed. the space requirement of a cell must be minimized. At the same time, the electrical reliability must remain guaranteed, in particular the capacitance of the capacitor must not fall below a certain value. In memory cells with a stacked capacitor (so-called stacked capacitor cell), the capacitor consists of two polysilicon plates separated by a dielectric, which are arranged above the transistor.

In order to achieve a none capacitance in such a capacitor, it is known from the article by T. Kaga et al., IEE Transaction on Electron Devices, Volume 38, February 1991, pages 255 to 261, that the capacitor (or the capacitor plates ) is arranged above the bit line and has a key-shaped cross section. A capacitor with a comb-shaped cross section is proposed for further capacity increase. The manufacturing process However, this capacitor has the following difficulties: First of all, a nitride scan is required to planarize the surfaces under the lower capacitor plate. Since a nitride cannot flow, a planarizing cut-off process for the nitride must be used, which is difficult to carry out and in particular results in relatively thick nitride layers (approximately 100 nm) at some points on the surface. In such thick nitride scarcities there are no tolerable voltages. Furthermore, selective etching processes for silicon oxide relative to nitrite and for nitride relative to oxide are required.

It is therefore an object of the present invention to provide a production method for a capacitor of a one-transistor memory cell of the type mentioned which does not have the explained parts.

This object is achieved by a method according to claim 1 or 2. Further training is the subject of subclaims.

An essential advantage of the inventive method is the non-procedural certainty of the individual procedural steps. For example, in the case of oxide etching, a polysilicon device is used as the etching stop device, against which higher etching selectivities than with respect to nitride are achieved. Furthermore, only nitride chips of approximately 20 nm in thickness are used which are uncritical with regard to voltages. The method can be used particularly advantageously in the case of memory cells with a bit line running on a planarized background, as described in the DE patent application "Semiconductor memory arrangement and method for its manufacture" by the same inventors dated June 30, 1992, the entire content of which is also included . The invention is described below with reference to the embodiments shown in the drawings. Show it:

FIGS. 1 to 8 show a cross section through a semiconductor substrate in the area of memory cells in a schematic representation, on which the steps of the method are illustrated.

FIG. 1 shows a semiconductor substrate 1, consisting of p-doped silicon, in which isolation regions 2 have already been produced between active regions of the semiconductor memory arrangement and n-doped conductive regions of a MOS transistor designated as source 4 and drain 5. A gate 6 (word line) is arranged on the surface 3 of the semiconductor substrate 1 and is insulated by a gate oxide (not shown) from the underlying semiconductor substrate 1 and on its other surfaces, for example by an oxide encapsulation 7. Source 4 and drain 5 are with a source connection 8 or. a drain terminal 9, which are preferably produced by filling with doped polysilicon. The drain connection 9 connects the drain to an overlying bit line 10, which is covered on its free surfaces with an insulation layer 11. The inventive method is explained using a memory cell, for example, in which the capacitor is arranged above the bit line.

According to the invention, an approximately 20 nm thick silicon nitride layer 30 and an approximately 40 nm thick polysilicon layer 31 are then deposited on the surface of the structure, if present, as an etching stop layer, for example in a CVD method. Outside the cell field, ie in the periphery, the polysilicon layer is 31 with the aid of a corresponding structured photoresist mask and a suitable one Etching process removed again, however, it remains in the cell field. (In the following, the application, exposure and development of a lacquer mask, partly including the subsequent removal of the structured lacquer layer, is referred to as photo technology.) A planarization layer 32 is then applied (after removal of the photo technology lacquer layer), For this purpose, preferably a boron-phosphorus-silicate glass (BPSG) or a BPSG / TEOS layer 32 (TEOS = tetraethylorthosilicate) is flowed and etched back, particularly moist, so that a largely leveled surface is present. The thickness of the planarization layer 32 above the bit line 10 is approximately 400 nm.

Figure 2: With the help of a photo technique, the source connection 8 is now exposed. First, the planarization layer 32 is etched selectively anisotropically to the polysilicon layer 31, then the polysilicon layer 31 is selectively removed to the nitride 30 wet or dry. Due to the different layer thickness of the planarization layer

32, a high selectivity of approximately 20: 1 to 40: 1 is particularly advantageous for the first etching process; such etching processes are known. On account of the phototechnics used, only a narrow web of the layers mentioned remains above the bit line 10 and - outside the plane of the drawing - above the insulation region 2, so that the source connection 8 is enclosed with these webs. The web can be narrowed further by a wet TEOS etching directly after the anisotropic TEOS etching. The resist mask of the photographic technology is removed and the lateral edge region 31 'of the polysilicon layer 31 is oxidized in an oxidation step. The polysilicon layer 31 does not have to completely oxidize from the sides. Finally, the nitride layer 30 is selectively horizontal oxide and polysilicon etched. The source connection 8 is thus exposed in a self-aligned manner to the bit line or to its lateral insulation 11. The photo technology defines the area available for the lower capacitor plate.

FIG. 3: The full-area deposition follows of a first electrode layer 33 ', preferably an in-situ doped polysilicon layer of approximately 100 nm thickness, in a CVD process. A lacquer stopper 34 is introduced into the depression which has arisen between the webs by known methods, for example by coating the entire surface with lacquer and then etching back. The upper edge of the lacquer stopper 34 is at most at the same level with, but preferably below the upper edge of the planarizing layer 32. Since the height differences of the surface are generally much smaller in the periphery, especially if the above-mentioned webs are missing there there is no paint on the polysilicon layer 33 '.

FIG. 4: The first electrode layer 33 'is then removed at the exposed locations by an etching process, in particular above the TEOS layer 32 in the cell field and in the periphery. This creates a lower capacitor plate 33. The now exposed oxide structures, namely the TEOS layer 32 and the oxidized edge regions 31 'are preferably wet-etched, the lacquer stopper 34 is removed. In a variant, however, the entire periphery can also be covered with varnish after the polysilicon (33 ') etching in a phototechnology process, while the cell field remains free of varnish. The exposed oxide, that is to say the TEOS layer 32 and the oxidized edge regions 31 'of the polysilicon layer 31, is then preferably removed by wet etching TEOS layer 32 in the periphery and is used there for planning.

In a further variant, the lacquer plug 34 can also be produced and the periphery can be covered with the same lacquer layer, in that after the polysilicon layer 33 'has been deposited (see FIG. 3), the lacquer layer is applied and by a subsequent corresponding layer The exposure and development in the periphery remains, but, as already explained, remains in the cell field only in the depressions as a lacquer stopper 34. For this purpose, a simple photo mask can be used during the exposure, which covers the periphery and fully exposes the cell field. Thereafter, the polysilicon 33 'is first etched, then the TEOS 32 and polysilicon oxide 31' and finally the lacquer is removed. In this second variant, however, the polysilicon layer 33 'in the periphery must be removed later, for example using the photographic technique that structures the cell plate.

FIG. 5: A dielectric 35 is now applied to at least the surface of the lower capacitor plate 33. An ONO-3 layer 35 is preferably produced over the entire surface; the second electrode layer 36 ', which generally consists of doped polysilicon and is approximately 100 nm thick, is then produced. Before structuring the second electrode layer 36 'to form a cell plate, it is advantageous to partially level the surface in the cell field with a further planarizing layer 37, for example by depositing, closing and etching back a TEOS / BPSG layer 37. The second electrode layer 36 'is then structured with the aid of a photo technique to the cell plate 36 by performing a polysilicon etching and then removing the resist mask. (In the above second variant explained, the second electrode layer, the dielectric and the first electrode layer must be removed using suitable etching processes.)

Finally, the entire surface is covered with an approximately 100 nm insulation layer 38, e.g. TEOS covered; if the leveling was not carried out using the TEOS / BPSG layer 37, a correspondingly thicker intermediate oxide must be used for covering.

Figure 6: In a second embodiment of the method, the lower capacitor plates can also be separated from one another by an oxide spacer instead of the oxidized edge regions 31 '. Proceeding from FIG. 1, one can proceed as follows:

As described in FIG. 2, the TEOS layer 32 is first etched into narrow webs with the aid of a photographic technique, then the polysilicon layer 31, and finally the resist mask is removed. An oxide spacer 39 is then produced by depositing the entire surface of a layer preferably consisting of 30 nm thick TEOS with subsequent anisotropic etching back. For safe later insulation, it is advantageous to first carry out a short isotropic polysilicon etching (in particular wet etching) before the TEOS layer is deposited, as a result of which the edge region of the polysilicon layer 31 is not removed; the resulting gap is filled during the deposition of the TEOS layer 39. After the TEOS spacer etching, the underlying nitride 30 is anisotropically etched, then the further process steps follow as described in FIG. 3.

According to a third embodiment of the method, a capacitor with a further increased capacitance is formed by the capacitor electrodes 33, 40, 42 being one have a comb-shaped cross section. For this purpose (see FIG. 3), first the first electrode layer 33 'is shaped like a weft, as in the manufacture of the lower capacitor plate of the first exemplary embodiment, and is completed to form a comb-shaped lower capacitor plate 33, 40 in that the "bowl" of their sides are successively alternately filled with auxiliary spacers 43 and conductive spacers 40. An auxiliary layer, preferably consisting of silicon oxide, is first deposited over the entire surface and removed in an anisotropic recess process except for a spacer 43 on the bowl walls. A conductive spacer 40, in particular consisting of doped polysilicon, is then produced in the same way so that it laterally covers the auxiliary spacer 43. These two processes are repeated until the bowl is filled with

Spacers is filled up to the middle, the thickness of the individual spacers is about 50nm to 200nm. Since the conductive spacers 40 are conductively connected to the bottom of the bowl, the lower capacitor plate 33, 40 is thus formed with a comb-shaped cross section.

FIG. 8: The auxiliary spacers 43 are now removed, for example by wet oxide etching, then a dielectric 41 covering at least the lower capacitor plate 40 is applied. Finally, a second electrode layer is deposited and structured into cell plate 42 using a photo technique.

Finally, the cell plate 42 is covered with a preferably planarizing insulation layer 44 (e.g. TEOS).

Claims

Claims 1. Manufacturing method for a capacitor of a one-transistor memory cell on a semiconductor substrate which is arranged above the transistor, the transistor having a source (4), drain (5), and gate (6) and a source Has connection (8) and a drain connection (9) and the drain connection (9) is connected to a bit line (10), with the following steps: a) Deposition of a nitride layer (30), an etch stop layer (31 ) and a planarization layer (32), b) anisotropic etching of the planarization layer (32) and the etch stop layer (31) with the aid of a photo technique such that the layers are completely removed at least above the source connection (8) and webs of the layer sequence stop, which surround the source connection (8), c) oxidize the exposed edge regions (31 ') of the etching stop layer (31), d) remove the exposed parts of the nitride bars (30), e) deposit a first surface over the entire surface Electrode layer (33 ') and filling of the depressions between the webs with a lacquer stopper (34), which extends at most to the upper edge of the planarization layer (32), f) etching away the exposed parts of the first electrode layer (33 ¹ ), whereby a lower capacitor plate (33) is formed, and the parts of the web (32, 31 ') consisting of oxide are etched away, g) application of a dielectric (35) at least on the lower capacitor plate (33), h) full-surface deposition of a second one Electrode layer (36 ¹ ) and structuring to the cell plate (36) using a photo technique and an etching process. 2. Manufacturing process for a capacitor of a one-transistor memory cell on a semiconductor substrate which is arranged above the transistor, the transistor having a source (4), drain (5) and gate (6) and a source connection (8) and a drain connection (9) and the drain connection (9) is connected to a bit line (10), with the following method steps: a) deposition of a nitride bar (30), an etch stop layer (31) over the entire surface and a planarization bar (32), b) anisotropic etching of the planarization layer (32) and the polysilicon layer (31) with the aid of a photo technique such that the layers are completely removed at least above the source connection (8) and webs of the layer sequence remain , which enclose the source connection (8), c) depositing an oxide layer and anisotropically etching back to an oxide spacer (39) covering the web walls, d) removing the exposed parts of the nitride layer (30), e) entirely Flat deposition of a first electrode layer (33 ¹ ) and filling of the depressions between the webs with a lacquer stopper (34) which at most extends to the upper edge of the planarization layer (32), f) etching away the exposed parts of the first electrode layer (33 ¹ ), whereby a lower capacitor plate (33) is formed, and etching away the parts of the web (32, 31 ') consisting of oxide, and the oxide spacer (39), g) applying a dielectric (35) at least on the lower capacitor plate , n) depositing the entire surface of a second electrode layer (36 ¹ ) and structuring to form the cell plate (36) with the aid of a photo technique and an etching process. 3. The method according to any one of claims 1 or 2, d a ¬ d u r c h g e k e n n z e i c h n e t that the procedural step f) is carried out as follows: Etching away the exposed parts of the first electrode bar (33 ¹ ), so that the first electrode layer is structured into a bowl, Producing an auxiliary spacer (43) covering the bowl walls by depositing and etching back an auxiliary layer over the entire surface, producing a conductive spacer (40) covering the side of the auxiliary spacer (43) by completely flattening and etching back a conductive layer, which does not consist of the material of the first electrode, Filling the bowl by alternately producing auxiliary spacers (43) and conductive spacers (40) so that the structured first electrode layer (33) and the conductive spacers (40) together form a lower capacitor plate with a comb-shaped cross-section, - Removing the auxiliary spacer (43) and etching away the parts of the web (32, 31 ') consisting of oxide and, if appropriate, the oxide spacer (39); and that during the deposition of a second electrode layer over the entire surface, the gaps between the conductive spacers are filled. 4. The method according to any one of claims 1 to 3, so that a polysilicon layer of approximately 50 nm to 300 nm thickness is not deposited as the first and / or second electrodes. 5. The method according to any one of claims 1 to 4, since ¬ characterized in that after Ab¬ deposition of the second electrode not (36 ', 42) the surface with a planarizing insulating layer (37, 44) is largely leveled. 6. The method according to any one of claims 1 to 5, d a ¬ d u r c h g e k e n n z e i c h n e t that the planarization layer (32) contains TEOS. 7. The method according to any one of claims 2 to 6, so that the side edge regions of the polysilicon layer (31) are removed before carrying out process step c).