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WO1993008597A1 - Dispositif a semi-conducteurs, tranche semi-conductrice pour la fabrication d'un dispositif a semi-conducteurs et procede de fabrication d'une telle tranche semi-conductrice - Google Patents

Dispositif a semi-conducteurs, tranche semi-conductrice pour la fabrication d'un dispositif a semi-conducteurs et procede de fabrication d'une telle tranche semi-conductrice Download PDF

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Publication number
WO1993008597A1
WO1993008597A1 PCT/SE1992/000707 SE9200707W WO9308597A1 WO 1993008597 A1 WO1993008597 A1 WO 1993008597A1 SE 9200707 W SE9200707 W SE 9200707W WO 9308597 A1 WO9308597 A1 WO 9308597A1
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WO
WIPO (PCT)
Prior art keywords
layer
wafer
semiconductor
glass
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/SE1992/000707
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English (en)
Inventor
Kjell Bohlin
Jonas Tiren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB AB
Original Assignee
Asea Brown Boveri AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asea Brown Boveri AB filed Critical Asea Brown Boveri AB
Publication of WO1993008597A1 publication Critical patent/WO1993008597A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Definitions

  • the present invention relates to a semiconductor device comprising a carrier material in the form of a silicon wafer, at least one active layer of a semiconductor material, in which semiconductor circuits are produced, as well as electrically insulating layers between the carrier material and the active layers.
  • the invention also relates to a semiconductor wafer for the manufacture of semiconductor devices and comprising a carrier material in the form of a silicon wafer, an active layer of a semiconductor material for the production of semiconductor circuits, as well as electrically insulating layers between the carrier material and the active layer.
  • the invention relates to a method for the manufac ⁇ ture of a semiconductor wafer which is intended for the manufacture of semiconductor devices and which comprises a carrier material in the form of a silicon wafer, an active layer of a semiconductor material for the production of semiconductor circuits, as well as an electrically insula ⁇ ting layer between the carrier material and the active layer.
  • Certain semiconductor devices contain a plurality of semi ⁇ conductor circuits, applied to one and the same carrier (substrate) , in the form of separate layers of semiconductor material, usually silicon.
  • Each one of the semiconductor circuits may consist of one single device, for example a transistor, or of a more or less complicated integrated
  • circuit with a plurality of devices For the circuits applied to the carrier to be able to work at different electrical potentials r it is desirable that they are electrically insulated from the carrier and hence from each other.
  • SOI Silicon On Insulator
  • SOS Silicon On Sapphire
  • the carrier consists of a silicon wafer.
  • a silicon dioxide layer is formed at a certain depth below the substrate surface.
  • the semiconductor circuits are then produced.
  • this technique only a very thin oxide layer can be obtained, and this layer will therefore have a low dielectric strength.
  • the thin oxide layer entails a conside ⁇ rable risk that the semiconductor circuits of the device may influence each other in an undesirable way - parasitic effects.
  • a third previously known method of producing a semiconductor device of the kind referred to is by bonding two silicon wafers to each other. On the surface of one of the wafers, or of both wafers, silicon dioxide layers are formed, whereupon the wafers are bonded to each other with the oxide layer of each wafer facing the other wafer.
  • the bonding is performed by heating to a relatively high temperature, for example to about 1100°C. After the bonding, one of the silicon wafers is ground or etched down to the desired thickness, whereafter the desired semiconductor circuits are produced in the layer which constitutes the remaining part of this wafer.
  • a relatively high temperature for example to about 1100°C.
  • the present invention aims to provide a semiconductor device with a considerably thicker insulating layer than what has previously been possible and which can be manufactured at lower process temperatures and hence with reduced risk of defects in the active semiconductor layer.
  • the invention also relates to a semiconductor wafer for the manufacture of such semiconductor devices and to a method for manufacturing such a semiconductor wafer.
  • Figure 1 shows an example of successive process steps in the manufacture of a semiconductor wafer according to the invention.
  • Figure 2 schematically shows a semiconductor device according to the invention.
  • Figure 3 shows an example of a finished semicon ⁇ ductor device according to the invention.
  • Figure 1 shows an example of successive steps in the manufacture of a semiconductor wafer according to the invention.
  • the starting material are two silicon wafers 1 and 2. They have a diameter of, for example, 50-100 mm and a thickness of, for example, about 0.5 mm.
  • Wafer 2 is intended to serve as carrier (substrate) for the finished semicon ⁇ ductor devices, and the material in wafer 1 is intended to serve as the active layer of the finished devices.
  • each wafer is first provided, as shown in Figure la, with thermal oxide by heating in the presence of oxygen.
  • the oxide layers 11 and 21, respectively, thus formed substantially consist of silicon dioxide and have a thickness of about 50 n (typically, the thickness of this layer may be within the interval 10-100 nm) .
  • the wafer 1 is provided with a layer 12 of silicon nitride .
  • This layer is produced by LPCVD (Low Pressure Chemical Vapour Deposition) from dichlorosilane (SiH 2 Cl 2 ) and has a thickness of 0.15 ⁇ m.
  • the silicon nitride has a good diffusion barrier effect and prevents dopants from the subsequently applied doped glass layers from diffusing into the silicon wafer 1 and distur ⁇ bing the function of the circuits formed therein.
  • the two wafers are heated to the yielding tempe ⁇ rature of the glass, which typically is 800-900°C, whereby the glass layers will float out and very even surfaces of the glass layers be attained.
  • the wafers After cooling, the wafers are put together with the glass layers facing each other in the manner shown in Figure Id, and a certain adhesion is obtained between the wafers. Then, the wafers thus joined together are heated to such a high temperature, typically 800-900°C, that a complete bonding is obtained between the wafers, which means that they will stick together like one single body.
  • a high temperature typically 800-900°C
  • the material in wafer 1 is removed down to the dashed line A-A in Figure Id. This can be done by grinding and polishing or by etching.
  • the remaining part of wafer 1, namely, the layer designated 14 in Figure Id constitutes the active layer, in which the semiconductor circuits of the finished semiconductor devices are to be formed.
  • the thick ⁇ ness of the layer 14 must be adapted to a suitable value for the circuits for which the wafer is intended, and in typical cases the thickness is within the interval 0.1-30 ⁇ m.
  • the wafer shown in Figure Id thus constitutes the starting material for the manufacture of semiconductor devices.
  • the thickness of the wafer is greatly exaggerated in Figure 1.
  • its diameter is typically 50-100 mm and its thickness about 0.5 mm.
  • semiconductor devices are manufactured from the above- described wafer by selectively etching away the active layer 14 such that a number of separate silicon islands are formed.
  • Figure 2 which shows the carrier 2 , an insulating layer 3 consisting of the layers 11, 12, 13 r 23, 21 shown in Figure 1, and a number of separate silicon islands 40, 41, ..., 48.
  • the latter may, for example, have the dimensions 10x10 ⁇ m.
  • semiconductor circuits for example in the form of MOS transistor circuits, are formed in the islands in a known manner by selective doping and contacting.
  • the wafer is divided in a check pattern (along the dashed lines B-B and C-C shown as example in Figure 2) into the semiconductor devices I, II, III etc.
  • Each device consists of a carrier with a number of silicon islands with circuits formed therein. After division of the wafer, there are formed, for example, the devices I, II and III, where , for example, device II consists of the part of the wafer 2 located between lines B-B and C-C and the corre ⁇ sponding part of the insulating layer 3, and the silicon islands 41-45.
  • Figure 3 schematically shows a picture of the device II with the silicon islands 41-50 prior to enclosing the device.
  • the semiconductor device according to the invention descri ⁇ bed above has a high dielectric insulation between the sub- strate and each semiconductor circuit, and hence also between the individual semiconductor circuits. This is achieved since the doped glass, which according to the invention is used as insulation between the carrier and the silicon islands, can be applied in thick layers.
  • the glass layers 13 and 23 have a thickness of about 1 ⁇ m.
  • the glass layers may without difficulty be given thicknesses of 2 ⁇ m or more. Together with the oxide layers 11 and 21, a total thickness of the insulation layers of 5 ⁇ m or more may thus be obtained. In typical cases, an insulation strength of several kv may be attained.
  • the manu ⁇ facturing process according to the invention makes it possible to attain this high insulation in an advantageous manner from the point of view of manufacturing and therefore provides considerable advantages compared with prior art methods.
  • the bonding of the wafers can be performed at a low temperature ( ⁇ 900°C) . In this way, the risk of defects being generated in the active semiconductor layers is greatly reduced, and better electrical properties may be obtained in the finished devices.
  • the oxide layers 11 and 21 provide a good and controlled adhesion of the other layers to the silicon wafers.
  • the carrier wafer 2 only has the function of serving as a carrier for the active semiconductor circuits.
  • the method and the semiconductor wafer according to the inven ⁇ tion can be used also in other applications, for example for the manufacture of semiconductor devices in which the carrier wafer consists of a silicon wafer in which a power component, for example a thyristor, is formed.
  • the semicon ⁇ ductor circuits arranged on the carrier wafer may then, for example, consist of control electronics for the power com ⁇ ponent.
  • both of the joined semiconductor wafers consist of silicon wafers.
  • this wafer may consist of germanium or a germanium-silicon mixture, or or another semiconductor material, such as gallium arsenide (Ga As) or indium phosphide (InP) .
  • the oxide layers 11 and 21 consist of thermal oxide.
  • these layers may be generated in some other known way, for example by a CVD process.
  • a thickness of the oxide layers of about 50 nm have been mentioned above.
  • these layers may be made considerably thicker, without any problem up to about 1 ⁇ m.
  • the oxide layers consist of an oxide of the semiconductor material (silicon) .
  • these layers may consist of another material, for example zirconium oxide or aluminium oxide.
  • the diffusion barrier layer 12 of silicon nitride described above layers of other materials with a correspon ⁇ ding function may be used, for example titanium nitride or zirconium nitride.
  • the oxide layer 21 may consist of an oxide generated in some other way, for example of undoped CVD- oxide. A layer of the latter kind has good diffusion- preventing properties, and the special barrier layer 12 can then be eliminated.
  • barrier layer 12 and the glass layers 13 and 23 are deposited with the aid of an LPCVD process.
  • a plasma-CVD process or so- called atmospheric CVD may be used.
  • the glass layers 13 and 23 consist of boron-phosphorus-doped glass containing about 4 per cent by weight boron and 4 per cent by weight phos- phorus.
  • boron-phosphorus-doped glass containing about 4 per cent by weight boron and 4 per cent by weight phos- phorus.
  • boron or only phosphorus may be used as dopant, and, of course, other dopants than boron and phosphorus (both single dopants and combinations of dopants) may be used, as well as other doping concentrations than those described above.
  • both wafers are provided with glass layers before the bon ⁇ ding of the wafers to each other.
  • only one of the wafers is provided with a glass layer.
  • this glass layer is then bonded to the other wafer. It has been found that a good bonding is obtained between the glass layer and that material in the other wafer which is nearest the glass layer, for example silicon, nitride or silicon oxide, and, in principle, the same advantages can be obtained with this embodiment as with the previously descri- bed one with two glass layers.
  • the device described above is only an example and can be formed in a large number of other ways.
  • the number of semi ⁇ conductor circuits which are applied to the carrier may be both lower and higher than that described above. In certain cases, several thousand semiconductor circuits may be applied to the carrier. Also other semiconductor circuits than purely electrical ones can be produced in the active layers, for example optoelectronic devices or circuits.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

L'invention se rapporte à une tranche semi-conductrice pour la fabrication de dispositifs à semi-conducteurs, qui comporte une tranche de silicium servant de support (2), ainsi qu'une couche active (14) servant à produire un certain nombre de circuits semi-conducteurs qui sont électriquement isolés l'un de l'autre et du support. Une couche isolante est disposée entre la tranche servant de support et la couche active et comprend deux couches (12, 23) de verre dopé au phosphore et au bore, qui sont collées l'une à l'autre.
PCT/SE1992/000707 1991-10-15 1992-10-08 Dispositif a semi-conducteurs, tranche semi-conductrice pour la fabrication d'un dispositif a semi-conducteurs et procede de fabrication d'une telle tranche semi-conductrice Ceased WO1993008597A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9102984-3 1991-10-15
SE9102984A SE469863B (sv) 1991-10-15 1991-10-15 Halvledarkomponent, halvledarskiva för framställning av halvledarkomponent samt förfarande för framställning av sådan halvledarskiva

Publications (1)

Publication Number Publication Date
WO1993008597A1 true WO1993008597A1 (fr) 1993-04-29

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Application Number Title Priority Date Filing Date
PCT/SE1992/000707 Ceased WO1993008597A1 (fr) 1991-10-15 1992-10-08 Dispositif a semi-conducteurs, tranche semi-conductrice pour la fabrication d'un dispositif a semi-conducteurs et procede de fabrication d'une telle tranche semi-conductrice

Country Status (2)

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SE (1) SE469863B (fr)
WO (1) WO1993008597A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107004639A (zh) * 2014-07-08 2017-08-01 麻省理工学院 衬底制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0209173A1 (fr) * 1985-06-20 1987-01-21 Koninklijke Philips Electronics N.V. Procédé pour la fabrication de dispositifs semi-conducteurs comportant la liaison mécanique entre deux corps
US4826787A (en) * 1986-03-18 1989-05-02 Fujitsu Limited Method for adhesion of silicon or silicon dioxide plate
EP0418737A1 (fr) * 1989-09-13 1991-03-27 Kabushiki Kaisha Toshiba Procédé de fabrication d'un substrat semi-conducteur comportant une structure diélectrique
US5028558A (en) * 1988-04-13 1991-07-02 U.S. Philips Corporation Method of manufacturing a silicon on insulator semiconductor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0209173A1 (fr) * 1985-06-20 1987-01-21 Koninklijke Philips Electronics N.V. Procédé pour la fabrication de dispositifs semi-conducteurs comportant la liaison mécanique entre deux corps
US4826787A (en) * 1986-03-18 1989-05-02 Fujitsu Limited Method for adhesion of silicon or silicon dioxide plate
US5028558A (en) * 1988-04-13 1991-07-02 U.S. Philips Corporation Method of manufacturing a silicon on insulator semiconductor
EP0418737A1 (fr) * 1989-09-13 1991-03-27 Kabushiki Kaisha Toshiba Procédé de fabrication d'un substrat semi-conducteur comportant une structure diélectrique

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107004639A (zh) * 2014-07-08 2017-08-01 麻省理工学院 衬底制造方法
CN107004639B (zh) * 2014-07-08 2021-02-05 麻省理工学院 衬底制造方法

Also Published As

Publication number Publication date
SE9102984L (sv) 1993-04-16
SE469863B (sv) 1993-09-27
SE9102984D0 (sv) 1991-10-15

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