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WO1987006060A1 - Procede permettant d'unir deux ou plusieurs tranches de semi-conducteurs et structure resultante - Google Patents

Procede permettant d'unir deux ou plusieurs tranches de semi-conducteurs et structure resultante Download PDF

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Publication number
WO1987006060A1
WO1987006060A1 PCT/US1987/000694 US8700694W WO8706060A1 WO 1987006060 A1 WO1987006060 A1 WO 1987006060A1 US 8700694 W US8700694 W US 8700694W WO 8706060 A1 WO8706060 A1 WO 8706060A1
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WIPO (PCT)
Prior art keywords
semiconductor
semiconductor wafer
bonding means
epitaxial
substrate
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Ceased
Application number
PCT/US1987/000694
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English (en)
Inventor
William I. Lehrer
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of WO1987006060A1 publication Critical patent/WO1987006060A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Definitions

  • This invention relates to semiconductor devices and in particular to a semiconductor structure comprising at least one semiconductor wafer joined to another semiconductor wafer or to an appropriate substrate of a selected material such as insulation, by a material which withstands the temperatures to which the wafer is subjected during the processing of the wafer to form integrated circuits and which has a temperature coefficient of expansion and contraction which substantially matches that of the at least one semiconductor wafer.
  • Peltzer in U.S. Patent No. 3,648,125 forms isolated pockets of semi- conductor material by forming an epitaxial layer of one conductivity type on a substrate of another conductivity type to create a laterally extending PN junction, forming grooves part way through the epitaxial layer in the pattern desired for the isolation and then thermally oxidizing the grooves through to the underlying laterally extending PN junction to thereby form a plurality of electrically isolated pockets of epitaxial semiconductor material.
  • Another technique of increasing the packing density (Frescura et al. , U.S. Patent No.
  • 3.489,961 forms grooves in epitaxial semiconductor material of one conductivity type through to an underlying semiconductor substrate of opposite conductivity type.
  • the grooves laterally surround and isolate islands of semiconductor material.
  • a third approach (Tucker and Barry, U.S. Patend No. 3,736,193) involves the formation of a grid of oxide (either doped or undoped) on a semiconductor substrate in the pattern desired for the isolation regions of the resulting integrated circuit, and then depositing silicon on the substrate from, for example, the decomposition of silane in a carrier gas. Epitaxial silicon forms over the exposed portions of the substrate while polycrystalline silicon forms over the oxide grid.
  • the polycrystalline silicon is either doped simultaneously from dopant contained in the underlying oxide with an impurity selected to change the conductivity type of the polycrystalline silicon to be opposite to the conductivity type of the epitaxial silicon, or is subsequently doped with such an impurity.
  • One of the disadvantages of the above structures is that while the circuitry extends in two dimensions over the wafer surface and includes active and passive regions forming diodes, transistors, resistors and/or capacitors in the underlying semiconductor material, only one layer of circuitry is formed.
  • the combination of two semiconductor wafers to form an electrical circuit is disclosed in Wallia, U. S. Patent 3,764,950. Wallia forms an analog circuit on one semi- conductor wafer and forms cavities in an adjacent semicon- ductor wafer.
  • the two wafers are then joined using a glass (disclosed in Wallia as a low-expansion, low-melting zinc phosphovanadate glass composition) to place the active circuitry on one wafer adjacent the cavities in the other wafer such that the resulting structure will function as a pressure transducer containing internal to the transducer the electrical circuits necessary to amplify the signals generated by changes in the pressure on the cavity.
  • a glass disclosed in Wallia as a low-expansion, low-melting zinc phosphovanadate glass composition
  • This invention overcomes the disadvantages of the prior 5 art and provides a structure which achieves both increased 5 packing density of electrical components through the ability 7 to form electrical components on more than one layer of the 8 resulting structure and which provides a material for the 9 joining of two or more wafers into a composite structure 0 which material has substantially the same thermal expansion i and contraction coefficient of the silicon wafers being * 2 joined and is able to withstand diffusion temperatures.
  • the present invention resulted from experimental research which demonstrated that various binary combinations 5 atop one another do not mix, or show little diffusion even 5 when one of the layers is melted.
  • the present invention 7 represents the ideal graded junction structure which can be a conveniently fabricated by various processes.
  • a special glass 0 which I denote as PVX/II but which comprises essentially a mixture of germanium oxide and silicon oxide (i.e. Ge ⁇ 2 and Si0 2 ) is provided which has a thermal expansion and contraction coefficient substantially equal to the 3 corresponding coefficient for silicon.
  • This material 4 comprises a semiconductor oxide binary system which is well 5 suited for elevated temperature cycling with no apparent 6 breakdown with proper processing in a neutral (i.e. non- 7 reactive) atmosphere.
  • two or more wafers are capable of being joined using my unique glass material wherein each of the two or more wafers has formed in it selectively doped regions of semiconductor materials such that when these regions are interconnected a composite three dimensional electrically functioning structure is obtained.
  • isolated pockets of epitaxial silicon material are formed on an underlying substrate of selected conductivity.
  • an epitaxial layer is grown on an underlying substrate of a selected conductivity and then covered with selected layers of glass or other materials.
  • the other materials can comprise a conductive plane of selectively doped polycrystalline silicon or of conductive ceramic.
  • a bonding glass in accordance with this invention is then placed over the conductive plane or the epitaxial layer and the structure is bonded by means of this glass to another substrate, such as a wafer of semiconductor material of selected conductivity type.
  • the structure is then etched to remove. the particular substrate on which the epitaxial layer was initially grown and the epitaxial layer is selectively masked and etched to leave isolated islands of epitaxial material formed over either the bonding glass or the con- ductive plane.
  • the conductive plane can be selectively patterned to allow electrical contact to be made through openings in the conductive plane to the semiconduc- tor material joined to the conductive plane by the bonding glass of this invention.
  • at least one wafer is bonded to an appropriate substrate of another material such as insula- tion by the bonding glass of this invention.
  • Figures 1a through 1f illustrate a structure manufactured in accordance with this invention using the -_ bonding glass of this invention.
  • FIG. 1a through 1f illustrate a process for the 2 manufacture of a semiconductor substrate utilizing the 3 bonding glass or "glue” of this invention. While several 4 different structures utilizing the bonding glass of this 5 invention will be described, it should be understood that 5 these structures are illustrative only and are not meant to 7 limit the applications of the invention.
  • germanium oxide (GeOg) - silicon oxide 9 (Si0 2 ) system of the present invention a range of expansion 0 coefficients exist that can be sequentially deposited i forming a "graded junction".
  • the gradient range extends 2 from approximately 0.5 x 10 " ° (Si0 2 ) to approximately 3 8 x 10 " ° (Ge0 2 ). Therefore, it would be feasible to 4 consider bonding silicon to any material within that 5 range. Accordingly, the materials listed in Table 1 are 5 suitable for bonding to silicon. 7 8 TABLE 1 9 Materials Expansion Coefficient 0 Diamond 1.18 10 • 6
  • one process utilizing the bonding glass of this invention begins with a substrate 11 shown as N+ type semiconductor material. While substrate 11 and the subsequent layers of materials to be formed on substrate 11 to comprise wafer 10 will be described as having specific conductivity types, it should be recognized that other conductivity types than those illustrated can also be used, if desired and appropriate.
  • An N type epitaxial layer 12 is then formed on N+ substrate 11 using standard well known techniques for the formation of epitaxial layers.
  • a layer of oxide 13 ( Figure 1b) is formed on the surface of epitaxial layer 12 typically by thermal oxidation methods. Then in accordance with this invention a layer of bonding glass 1 a is placed over oxide 13-
  • bonding glass 14a comprises a 45/55$ (percent by weight) mixture of Ge0 2 and Si0 2 .
  • bending beam method showed no substantial difference in the temperature coefficient of expansion of this glass (denoted by me as PVX/II) to that of silicon.
  • the temperature coefficient of expansion of this glass nominally matched that of silicon within experimental error. That is, by the "bending beam method" no difference could be found in the thermal coefficient of expansion of the glass and the underlying silicon wafer.
  • glass layer 1 a is formed to a selected thickness, in one embodiment 10 microns.
  • Glass layer 14a can also be doped if desired with phosphorus (typically - % P2°5 Dy weight). Coating was carried out by melting standard phosphovapox glass 14a formed in a manner well known in the art at 1000°C atop oxide layer 13 on wafer 10.
  • a wafer 15 (not shown in Figure 1b but shown in Figure 1c after being joined to wafer 10) has formed on it the bonding glass of this invention, PVX/II similarly doped with a nominally ⁇ % ⁇ ⁇ ⁇ 5 to a thickness of 10 microns.
  • the bonding glass of this invention comprising the 45/55 mole percent Ge0 2 /Si0 2 is formed at about 750-850°C.
  • the present invention utilizes a chemical vapor deposition (CVD) coating method.
  • the coating can be accomplished by atmospheric chemical vapor deposition (ACVD) , plasma assisted chemical vapor deposition (PACVD), and possibly by low pressure chemical vapor deposition (LPCVD) for certain compositions.
  • Other feasible coating methods include spin- ⁇ on or dip coating glass solutions or the sedimentation of glass powders. Both the CVD and the spin-on coating methods are useful to form submicron thicknesses, while the sedimentation method would be principally applicable at mil (thousandths of an inch) thicknesses.
  • the wafers 10 and 15 are joined (Figure 1c) in air by facing the coating layers 14a and 1 b and remelting these layers at 1000°C in air for 30 minutes.
  • the resulting structure appears as shown in Figure 1c.
  • the N+ substrate 11 is removed by use of a selective etch.
  • the method of etching has been described in Muraoka et al., "Controlled Preferential Etching Technology" Semiconductor Silicon 1973, ECS, Princeton, New Jersey, pp. 327, 338.
  • the etchant solution employed consists of one part HF, three parts HNO3, and eight parts CH3COOH. The result is to leave exposed the back side of N type epitaxial layer 12 (i.e.
  • the structure comprises an epitaxial layer 12 formed on an oxide layer 13 overlying the glass 14 of this invention and supported by a substrate 15 of selected material.
  • substrate 15 comprises selectively doped or intrinsic silicon, a ceramic substrate or any other appropriate material possessing the desired thermal expansion and contraction coefficient and electrical properties.
  • the silicon layer 12 is selectively etched to form isolated islands 12a, 12b and 12c ( Figure 1e) of isolated epitaxial silicon material.
  • the epitaxial layer is etched using a standard hydrazine or catechol-type anisotropic solution. This etch stops on oxide and thus the oxide layer 13 serves as an automatic etch stop and allows the etch to be continued slightly longer than otherwise necessary to ensure clean removal of all epitaxial silicon in the areas being etched. Thus isolated pockets of epitaxial silicon such as pockets or islands 12a, 12b and 12c (sometimes called "cells") are formed. These cells can be reoxidized before further processing.
  • Figure 1f illustrates the structure of Figure 1e with each of the cells 12a, 12b and 12c thermally oxidized to form oxide layers 13a, 13b and 13c over the exposed surfaces of these cells.
  • each of the cells 12a, 12b and 12c of Figure 1e is laterally surrounded on all lateral sides by a groove or a moat 16a, 16b formed by the removal of all epitaxial silicon in the moat area. Since the bonding glass 14 or "glue" of this invention is capable of withstanding semiconductor processing temperatures, complete dielectrically isolated structures are formed. Thus the cells 12a, 12b and 12c of epitaxial material illustrated in Figure 1f can be further processed to form active devices in each of the cells.
  • the moats 16a, 16b between the cells can be left unfilled and electrical interconnections (not shown) deposited over the oxide 13 to interconnect through vias (not shown) formed in oxides 13a, 13b and 13c, electrical connections to the electrical devices formed in the cells 13 a » 1 3b and 13c.
  • the moat areas 16a, 16b between the cells 13a, 13b and 13c can be filled with a selected material such as a polycrystalline silicon or a glass such as phosphovapox. Processing the binary glass of the invention in an oxidizing ambient will, under some circumstances cause formation of a volatile germanium monoxide (GeO) which will reduce the percentage concentration of germanium in the binary glass system.
  • GeO germanium monoxide
  • a second embodiment makes use of the moats 25 between cells 212a and 212b formed on bonding glass 216 to an underlying silicon substrate 211 to form an electrical connection from the top surface of a particular cell such as cells 212a and 212b to an underlying region 216 (typically diffused or ion implanted) in semiconductor material 211.
  • the diffused region 216 can represent a portion of an active device such as a transistor or a diode or alternatively a diffused conductive or resistive region in semiconductor material 211.
  • Metal interconnect layer 215 is then formed to interconnect region 214a formed in cell 212a by means of electrical contact 215a formed in a window in oxide 213a to electrical contact 215c formed in a window formed in bonding glass 216. Moreover, electrical contact 215b to diffused region 214b in cell 212b is also connected by means of interconnect 215 to electrical contact 215c. Thus regions 214a, 216 and 214b are electrically interconnected by electrical contacts 215a, 215c and 215b respectively and electrical interconnect 215.
  • the structure shown in Figure 2 makes use of the anisotropic etching of an epitaxial layer which yields a 60° angle a (alpha) as shown between the sloped sides of cells 212a and 212b and the top surface of semiconductor material 211. Because of this 60° angle, the deposition of contact interconnect material 215 (typically aluminum but any other appropriate conductive material including a conductive metal silicide or selectively doped polycrystalline silicon can be used) is without the shadowing effects which result in shorts or weaknesses in the interconnect structure. Step coverage is thus not a problem in accordance with this invention. Another advantage is the fact that a three dimensional geometry has now been achieved which saves valuable silicon space allowing a higher packing density.
  • region 216 can be part of an active device formed in semiconductor substrate 211 which is then joined by bonding glass 216 to the cell regions 212a and 212b of a different semiconductor wafer.
  • bonding glass 216 of this invention illustrates an alternative embodiment of this invention which prevents the physical drift of discrete epitaxial cells 312a, 312b, 312c and 312d atop the bonding glass 313 of this invention when the structure is heated.
  • One of the problems associated with this technology is the possibility that one or more of cells 312a through 312d could undergo thermal deformation and drift during subsequent heating of the device to elevated temperatures such as are necessary for oxidation and annealing.
  • a lower temperature formulation process could be employed, using a phosphorus doping of the bonding glass and joining the wafers at a temperature of approximately 800-850°C.
  • phosphorus, antimony, arsenic or boron could be used to dope the bonding glass.
  • Discrete cell drift could also be mitigated by the deposition of a higher temperature melting film such as Si0 2 (Vapox) that would fix all the cells in proper alignment for photomasking purposes.
  • a plurality of cells of epitaxial silicon 312a, 312b, 312c and 312d have been formed on bonding glass 313 which is in turn formed on the semiconductor substrate of base wafer 311.
  • wafer 311 could, if desired, be some other appropriate material such as aluminum oxide (Al 2 0g) or beryllium ceramic.
  • islands 312a through 312d are then covered with a layer 314 of a chemical vapor deposited oxide typically Si0 2 .
  • the melting point of Si0 2 is about 1600°C.
  • germanium oxide, Ge0 2 (melting point 1100°C) or titanium oxide Ti0 2 , (melting point 1640°C) or aluminum oxide, A1 2 0,, (melting point 2050°C) could be used as well as other appropriate glasses.
  • the underlying silicon islands 312a through 312d are either thermally oxidized through a chemical vapor deposited oxide or windows are etched in the chemical vapor deposited oxide to expose the silicon cells 312a through 312d to the oxidizing ambient.
  • Figure 3c where glass 314 has been partly removed to expose the top surfaces of cells 312a through 312d.
  • Example 1 Four inch wafers were "marker grooved", that is a small rectangular pattern was etched in each wafer to a depth of 4 microns. This was done to enclose all four sides using an 1 ISO/KOH etch so that the groove would signal the thickness
  • BOE a standard oxide etch

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)

Abstract

Structure composite tridimensionnelle à semi-conducteurs pour circuit intégré à fonctionnement électrique permettant d'augmenter la densité des composants électriques par l'établissement de circuits électriques sur au moins deux niveaux. Une telle structure est réalisée en soudant entre elles au moins deux tranches à semi-conducteurs (211 et 212a ou 212b) à l'aide d'un moyen de liaison (216) possédant un coefficient de dilatation thermique essentiellement égal au coefficient de dilatation thermique des tranches à semi-conducteurs destinées à être unies. L'égalité entre les coefficients de dilatation et de retrait thermiques du moyen de liaison et des tranches à semi-conducteurs permet à la structure composite à semi-conducteurs de supporter des températures élevées de traitement et protège les cellules épitaxiales formées dans les tranches à semi-conducteurs de la déformation thermique et de la dérive pendant le chauffage de la structure composite aux températures élevées nécessaires pour l'oxydation et le recuit.
PCT/US1987/000694 1986-03-28 1987-03-27 Procede permettant d'unir deux ou plusieurs tranches de semi-conducteurs et structure resultante Ceased WO1987006060A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US84568086A 1986-03-28 1986-03-28
US845,680 1986-03-28

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Publication Number Publication Date
WO1987006060A1 true WO1987006060A1 (fr) 1987-10-08

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0372412A1 (fr) * 1988-12-06 1990-06-13 Fujitsu Limited Méthode de fabrication d'un film semiconducteur électriquement isolé du substrat
WO1994027317A1 (fr) * 1993-05-06 1994-11-24 Siemens Aktiengesellschaft Procede permettant de realiser des composants sur un substrat de silicium sur isolant (soi)
WO1996013062A1 (fr) * 1994-10-19 1996-05-02 Ceram Incorporated Dispositif et procede de fabrication d'empilements de series de plaquettes
EP0570321A3 (en) * 1992-05-15 1997-03-12 Ibm Bonded wafer structure having a buried insulator layer
EP0661735B1 (fr) * 1993-12-29 2001-03-07 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Procédé pour fabriquer des circuits intégrés, en particulier des dispositifs semi-conducteurs intelligents de puissance
WO2001093310A3 (fr) * 2000-05-26 2002-03-14 Commissariat Energie Atomique Dispositif semiconducteur a injection electronique verticale et son procede de fabrication
EP1973857A4 (fr) * 2006-01-06 2012-07-04 Volodymyr Petrovich Maslov Métallisation céramique des unités vitreuses cristallines

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3332137A (en) * 1964-09-28 1967-07-25 Rca Corp Method of isolating chips of a wafer of semiconductor material
US4142925A (en) * 1978-04-13 1979-03-06 The United States Of America As Represented By The Secretary Of The Army Method of making silicon-insulator-polysilicon infrared image device utilizing epitaxial deposition and selective etching
US4515898A (en) * 1981-09-01 1985-05-07 Motorola, Inc. Glass bonding means and method
US4601779A (en) * 1985-06-24 1986-07-22 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
US4649627A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation Method of fabricating silicon-on-insulator transistors with a shared element

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3332137A (en) * 1964-09-28 1967-07-25 Rca Corp Method of isolating chips of a wafer of semiconductor material
US4142925A (en) * 1978-04-13 1979-03-06 The United States Of America As Represented By The Secretary Of The Army Method of making silicon-insulator-polysilicon infrared image device utilizing epitaxial deposition and selective etching
US4515898A (en) * 1981-09-01 1985-05-07 Motorola, Inc. Glass bonding means and method
US4649627A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation Method of fabricating silicon-on-insulator transistors with a shared element
US4601779A (en) * 1985-06-24 1986-07-22 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Applied Physics Letters, Volume 43, No. 3, 01 August 1983, Knoxville, Tennessee, M. KIMURA, "Epitaxial Film Transfer Technique for Producing a Single Crystal Si Film on an Insulating Substrate", pages 263-265, see page 263 and column 1, page 264. *
I. SKEIST, "Handbook of Adhesives", published 1962 by Robert E. Krieger (New York), pages 523-533 and pages 460-463, see page 461, column 2, lines 33-43, page 462, column 1, lines 7-19. *
IBM Technical Disclosure Bulletin, Volume 19, No. 9, February 1987, New York, G.E. BROCK, "Fusion of Silicon Wafers", pages 3405-3406, see page 3405. *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0372412A1 (fr) * 1988-12-06 1990-06-13 Fujitsu Limited Méthode de fabrication d'un film semiconducteur électriquement isolé du substrat
EP0570321A3 (en) * 1992-05-15 1997-03-12 Ibm Bonded wafer structure having a buried insulator layer
WO1994027317A1 (fr) * 1993-05-06 1994-11-24 Siemens Aktiengesellschaft Procede permettant de realiser des composants sur un substrat de silicium sur isolant (soi)
EP0661735B1 (fr) * 1993-12-29 2001-03-07 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Procédé pour fabriquer des circuits intégrés, en particulier des dispositifs semi-conducteurs intelligents de puissance
WO1996013062A1 (fr) * 1994-10-19 1996-05-02 Ceram Incorporated Dispositif et procede de fabrication d'empilements de series de plaquettes
WO2001093310A3 (fr) * 2000-05-26 2002-03-14 Commissariat Energie Atomique Dispositif semiconducteur a injection electronique verticale et son procede de fabrication
US7820461B2 (en) 2000-05-26 2010-10-26 Commissariat A L'energie Atomique Semiconductor device with vertical electron injection and its manufacturing method
EP1973857A4 (fr) * 2006-01-06 2012-07-04 Volodymyr Petrovich Maslov Métallisation céramique des unités vitreuses cristallines

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