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WO1992012539A1 - Memoire a semiconducteurs du type dynamique - Google Patents

Memoire a semiconducteurs du type dynamique Download PDF

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Publication number
WO1992012539A1
WO1992012539A1 PCT/JP1991/001800 JP9101800W WO9212539A1 WO 1992012539 A1 WO1992012539 A1 WO 1992012539A1 JP 9101800 W JP9101800 W JP 9101800W WO 9212539 A1 WO9212539 A1 WO 9212539A1
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WIPO (PCT)
Prior art keywords
film
insulator
electrode
capacitor
dielectric constant
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Application number
PCT/JP1991/001800
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English (en)
Japanese (ja)
Inventor
Tadahiro Ohmi
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Individual
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Publication of WO1992012539A1 publication Critical patent/WO1992012539A1/fr
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present invention relates to a dynamic semiconductor memory.
  • the capacitor 40 is composed of an insulating film sandwiched between two electrodes 41 and 42, and the switch 43 is composed of a MOS transistor.
  • the accumulated charge Q at the capacitor 40 is expressed by the following equation.
  • the mounted memory has a more or less fixed amount of leak. If a certain amount of leak is allowed, the larger the accumulated charge Q is, the better.
  • equation (2) force, et apparent, the dielectric constant £ lambda size or Kusuru, increase the counter area S, to reduce the insulating film thickness d I just need to do it.
  • equation (2) force, et apparent, the dielectric constant £ lambda size or Kusuru, increase the counter area S, to reduce the insulating film thickness d I just need to do it.
  • equation (2) force, et apparent, the dielectric constant £ lambda size or Kusuru, increase the counter area S, to reduce the insulating film thickness d I just need to do it.
  • the value of the facing area S decreases, and As is clear from the above equation, the smaller the capacitance, the smaller the capacitance C of the capacitor. Therefore, various measures have been taken to increase e Q or increase C by increasing S.
  • Figure 27 shows the trench capacitor type
  • Figure 28 shows the fin structure type
  • the capacitor type has the structure shown in FIG.
  • the trench capacitor type is based on filling the metal film 12 and the insulating film 23 in the trench.
  • the opposing area S is increased to increase the capacitance C of the capacitor.
  • the trench capacitor type has a deeper groove and an aspect ratio of 20 to 30
  • the fin structure type increases the facing area by making the metal film 12 three-dimensional,
  • the fin structure type is also fine
  • the cleaning behind the structure is difficult, and insulation withstand voltage failure easily occurs at the edge.
  • the stacked capacitor type is a trench capacitor type or fin structure
  • the conductive film 12 is formed by deposition, and then resist coating and photolithography are performed.
  • the resist 15 by lithography (Fig. 30 (a)), and use RIE
  • the first electrode 12d is formed (FIG. 30 (b)).
  • the polysilicon surface is oxidized by heating in an oxidizing atmosphere to form an insulating film 13 made of polysilicon oxide on the surface of the lower electrode 12d (FIG. 31 (a)).
  • Silicon is deposited by a CVD method to form the upper electrode 14 (FIG. 31B).
  • the insulating film 13 is constituted by S i 0 2, since the dielectric constant of S i 0 2 is as low as 3.9, it is impossible to obtain a large D RAM memory cell capacitance of the capacitor. Therefore, from the state of (FIG.
  • An object of the present invention is to provide a DRAM memory which is easy to manufacture, has excellent withstand voltage, and has a large capacitor capacity. Disclosure of the invention
  • the gist of the present invention for solving the above-mentioned problem is composed of two electrodes having substantially the same area facing each other with an insulator interposed therebetween, and another insulator formed adjacent to the electrode.
  • the first electrode 12 and the second electrode 14 having substantially the same area facing each other with the insulator 13 interposed therebetween are formed adjacent to the first electrode 12 and the second electrode 14.
  • the capacitor composed of the other insulator 17 is used as a signal charge storage capacitor, and the dielectric constant ⁇ j of the insulator 13 is set to be larger than the dielectric constant e 2 of the other insulator 17. I have.
  • the present inventors have found that the insulating properties can be enhanced by setting the first electrode and the second electrode to have substantially the same area, and by setting ⁇ 1 / ⁇ 2 ⁇ 1. It was made.
  • FIG. 20 (c) or FIG. 21 (c) when the areas of the first electrode 12 and the second electrode 14 are different, the insulation characteristics are shown in FIG. 19 (a). Lower than the case where In particular, in the case of the structure shown in FIG. 20 (c), as ⁇ / becomes larger, the insulation characteristics are significantly reduced.
  • the effect of the present invention is that the lines of electric force are concentrated on the higher dielectric constant, and if Sj / Sg, the lines of electric force are unlikely to expand in the lateral direction, and the concentration of the lines of electric force on the side surface of the electrode Is presumed to be reduced.
  • the first electrode is preferably, for example, Ti, Ta, A1, Ba, Sr, Hf, or the like.
  • the first electrode may have a single-layer structure, or may have a multilayer structure of two or more layers. In the case of a multilayer structure having two or more layers, it is preferable to form the lower layer with Cr in order to enhance the adhesion between the metal thin film and the insulating film covering the substrate surface.
  • the material of the conductive thin film for example, Ta, Ti, polysilicon, silicide, or any other conductive material can be used.
  • the metal thin film L is not particularly limited as a means for forming a conductive thin film.
  • a DC—RF sputtering is performed by applying a bias voltage to a substrate from the outside to form a film.
  • apparatus JP 62- 287071 discloses
  • the frequency of the shown to RF power 23 made different in the substrate side f 2 and the target-side two-frequency excitation sputtering apparatus for forming a film JP 63- No. 50025 Gazette
  • other methods such as a CVD method may be used.
  • the insulator is preferably formed by directly oxidizing the surface of the first electrode from the viewpoint of further improving the withstand voltage characteristics.
  • Examples of the direct oxidation method include a method of heating a substrate in an atmosphere of an oxidizing gas (for example, a mixed gas of O 2 gas or O 2 + N 2 gas).
  • an oxidizing gas for example, a mixed gas of O 2 gas or O 2 + N 2 gas.
  • the method of oxidizing the substrate while keeping it at a low temperature is to supply oxygen gas molecules to the surface of the metal film and irradiate the surface with inert gas ions having a kinetic energy of 90 eV or less. There is.
  • This method can activate the atomic layer on the surface without causing defects, for example, by striking the metal surface with Arion. 25 eV ions remain in the atomic layer of the surface and therefore only give energy to the surface. Then, the temperature of the metal surface can be effectively raised.
  • oxygen gas is introduced into the deposition chamber, oxygen molecules and oxygen radicals generated by the discharge are adsorbed on the metal surface, and react with the metal on the metal surface heated by Ar ion irradiation. Thereby, oxidation of the metal proceeds.
  • an apparatus for irradiating ions of 90 eV or less for example, an apparatus as shown in FIG. 22 or FIG. 23 is used. Gas and Ar gas are introduced into the device, and the substrate side frequency is 5 OMHz, the target side frequency is 20 OMHz, RF power is 10 to 50 W, and 1 mTorr to several 1 You can generate plasma in an atmosphere of 0 mT orr.
  • a natural oxide film is formed on the surface of the first electrode by performing the first electrode forming step and the insulating film forming step continuously in the same vacuum apparatus without breaking vacuum. Is preferably avoided as much as possible.
  • the transfer of the substrate from the first electrode forming apparatus to the insulating film forming apparatus is performed. It is preferable to carry out the reaction in an inert gas atmosphere or a high-purity air atmosphere having a water concentration of 10 ppb or less. Among these, especially high-purity air atmosphere with a water concentration of 1 O ppb or less It is preferable to convey it inside.
  • various devices 302 to 305 are connected by a tunnel 301, and the tunnel 301 is cut off from the atmosphere, while the tunnel 301 is closed.
  • a structure having a structure in which a gas having a water concentration of 1 O ppb or less flows therein can be used.
  • a gas is ejected into the tunnel 301 so as to hit the lower surface of the substrate, and the gas is used to carry the substrate while floating.
  • FIG. 25 a box 306 structure in which a gas having a water concentration of 10 ppb or less is filled.
  • FIG. 1 is a process cross-sectional view according to the first embodiment.
  • FIG. 2 is a process cross-sectional view according to the first embodiment.
  • FIG. 3 is a process cross-sectional view according to the first embodiment.
  • FIG. 4 is a process cross-sectional view according to the first embodiment.
  • FIG. 5 is a process cross-sectional view according to the first embodiment.
  • FIG. 6 is a process cross-sectional view according to the first embodiment.
  • FIG. 7 is a process cross-sectional view according to the first embodiment.
  • FIG. 8 is a process cross-sectional view according to the first embodiment.
  • FIG. 9 is a process cross-sectional view according to the first embodiment.
  • FIG. 10 is a process plan view according to the first embodiment.
  • FIG. 11 is a process sectional view according to the first embodiment.
  • FIG. 12 is a process cross-sectional view according to the first embodiment.
  • FIG. 13 is a process cross-sectional view according to the first embodiment.
  • FIG. I4 is a process cross-sectional view according to the first embodiment.
  • FIG. 15 is a process cross-sectional view according to the first embodiment.
  • FIG. 16 is a process cross-sectional view according to the first embodiment.
  • Fig. 17 shows a diagram according to the first embodiment.
  • FIG. FIG. 18 is a process cross-sectional view according to the first embodiment.
  • FIG. 19 is a sectional view of a charge storage capacitor illustrating the concept of the present invention.
  • FIG. 20 is a process cross-sectional view according to Comparative Example 1.
  • FIG. 20 is a process cross-sectional view according to Comparative Example 1.
  • FIG. 21 is a process cross-sectional view according to Comparative Example 2.
  • FIG. 22 is a conceptual diagram of an example of an apparatus used for forming a film or the like in the present invention.
  • FIG. 23 is a conceptual diagram of an example of an apparatus used for forming a film in the present invention.
  • FIG. 24 is a conceptual diagram showing an example of the transport means.
  • FIG. 25 is a conceptual diagram showing an example of the transport means.
  • FIG. 26 is an equivalent circuit diagram of the DRAM memory cell.
  • FIG. 27 is a sectional view showing the structure of a conventional DRAM memory cell.
  • FIG. 28 is a sectional view showing the structure of a conventional DRAM memory cell.
  • FIG. 29 is a sectional view showing the structure of a conventional DRAM memory cell.
  • FIG. 30 is a process sectional view showing a conventional method of manufacturing a DRAM memory cell.
  • FIG. 31 is a process cross-sectional view showing a conventional DRAM memory cell manufacturing method.
  • FIG. 1 shows the manufacturing process of the first embodiment.
  • a P-type Si substrate 1 was used as a semiconductor substrate.
  • the substrate 1 was heated in a dry oxygen atmosphere at 900 ° C. for 30 minutes to form a gate oxide film 3 of 1 Onm on the surface of the substrate 1 (FIG. 2).
  • N + polysilicon 4 serving as a lower electrode was deposited on the entire surface by LPCVD, a resist was applied thereon, and the resist 5 was patterned by photolithography (Fig. 3).
  • the polysilicon 4 was removed by RIE using the resist 5 as a mask, and a gate electrode (word line) 6 was formed (FIG. 4).
  • ion implantation was performed on the entire surface at a density of 5 ⁇ 10 15 / cm 2 at 50 kV As using the gate electrode 6 as a mask. Then 900. By annealing at Cx for 30 minutes in an N 2 atmosphere, defects caused by ion implantation are recovered and N + Regions 7 and 8 were formed (Fig. 5).
  • a resist was applied on the SiO 2 film 9, and a resist pattern was formed by photolithography (FIG. 7). Then, using the resist 10 as a mask, the SiO 2 film 9 and a part of the gate oxide film 3 were etched by RIE to expose a part of the surface of the N + region 7 to form a contact hole 11 (FIG. 8).
  • a first electrode forming step was performed as follows.
  • the substrate is placed in the DC-RF coupled sputtering apparatus shown in Fig. 22 and the degree of vacuum in the background of the film forming chamber is set to an ultra-high vacuum of 10 to 11 G T 0 rr or less. Then, Ar gas is introduced and sputtering is performed. A Ta film 12 was deposited to a thickness of 300 nm. At this time, the film was formed while irradiating the surface with low-energy Ar ions of several tens of eV at the initial stage and during the film formation. By such irradiation, a Ta film 12 with extremely good crystallinity was obtained (FIG. 9).
  • an insulating film forming step was performed as follows.
  • the first electrode forming step and the formation of the insulating film were performed by the same apparatus. That is, after the first electrode forming step was completed, an oxidizing gas was introduced into the apparatus to oxidize the Ta film 12. Of course, no RF power was applied and no sputtering was performed. Oxidation of T a film 1 2 heats the substrate temperature of 40 0 ° C, the water concentration is performed by introducing 1 Oppb less oxygen gas to form a Ta 2 0 5 film 13 of 5 nm (FIG. 10 ).
  • a second electrode was formed as follows.
  • the Ta film 14 was formed as a conductive thin film in the same manner as in the formation of the first electrode, using the same apparatus as that for forming the first electrode and the insulating film (FIG. 11). .
  • an interlayer insulating film and a multilayer wiring were formed as follows.
  • the resist 15 was patterned so that the resist remained only above the N + region 7 (FIG. 12).
  • resist 15 as a mask and using CF 4 gas
  • S i 0 2 film (PSG film) 17 containing S i 0 2 film or P on the entire surface using an atmospheric pressure CVD process was then deposited S i 0 2 film (PSG film) 17 containing S i 0 2 film or P on the entire surface using an atmospheric pressure CVD process.
  • PSG film instead of the PSG film, a BPSG film may be deposited, and S Zeo 1 may be formed by using a material having a dielectric constant ⁇ smaller than the dielectric constant ⁇ j of the insulating film 13.
  • the surface was planarized in order to perform the subsequent lithography with high precision (Fig. 14).
  • This flattening may be performed by using, for example, a bias sputtering method and an etch back method. Of course, another method may be used.
  • a first AI wiring 18 was formed by opening a contact hole (FIG. 1 ⁇ ).
  • a PSG film 20 is again formed as an interlayer insulating film using a sputtering method, etched by an RI ⁇ method, a contact hole is opened, and A1 leading to the ⁇ + region 8 is deposited, and a bit line 21 is formed.
  • a bit line 21 is formed.
  • the PSG film 20 may be formed by using a plasma CVD method or a spin-on-glass method.
  • the A1 wiring 18 ′ may be formed. Also, as shown in FIG. 18, an A1 wiring 18 "for making contact with the Ta film 14 and an A1 line 21" for making contact with the N + region 8 are simultaneously formed, and finally a bit line 22 is formed. May be.
  • the dynamic semiconductor memory manufactured by the above-described steps exhibited excellent insulating properties.
  • the substrate was carried into the oxidation treatment chamber via the tunnel having the structure shown in FIG. 24, and the oxidation treatment was performed in the oxidation treatment chamber.
  • the inside of the tunnel was kept in a high-purity air atmosphere having a water concentration of 10 ppb or less.
  • This example is the same as Example 1 up to the step shown in FIG. 12, but from the state of FIG.
  • RIE etching only etching of the Ta film 14 is performed, and after etching of the Ta film 14 is completed (FIG. 20 (a)), a resist pattern 33 is formed again by photolithography and resist coating (FIG. 20 (a)).
  • RIE etching was performed, and the edge portion was configured as shown in Fig. 20 (c).
  • Comparative Example 1 only the Ta film 14 was etched from the state shown in FIG. 12, but in this example, the Ta film 14 and the Ta 2 Oc film 13 were etched. Unlike Comparative Example 1, the Ta film 12 was left (FIG. 2I (a)).
  • the resist was patterned as shown by the dotted line in FIG. 21 (b), and the edge portion was formed into the structure shown in FIG. 21 (c).
  • the lower layer is preferably a Cr layer as in this example. Cr is preferable because good adhesion between the S i 0 2.
  • the upper electrode was formed with Ti, and the subsequent steps were performed at a temperature of 500 ° C or lower and at a temperature of 500 or lower.
  • oxidation of the surface of the Ta film constituting the lower electrode 12 is performed as follows.

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Abstract

Cellule de mémoire RAM dynamique à fabrication facile et à tension de claquage et capacitance élevées. La mémoire à semiconducteurs du type dynamique possède des condensateurs accumulant des charges de signal, chaque condensateur comportant deux électrodes dont les superficies sont presque égales, disposées en regard l'une de l'autre et dotées d'un premier isolant intercalé entre elles et d'un second isolant contigu aux électrodes. La constante diélectrique du premier isolant est supérieure à celle du second.
PCT/JP1991/001800 1991-01-01 1991-12-27 Memoire a semiconducteurs du type dynamique Ceased WO1992012539A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3010009A JPH04242971A (ja) 1991-01-01 1991-01-01 ダイナミック型半導体メモリ
JP3/10009 1991-01-01

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WO1992012539A1 true WO1992012539A1 (fr) 1992-07-23

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PCT/JP1991/001800 Ceased WO1992012539A1 (fr) 1991-01-01 1991-12-27 Memoire a semiconducteurs du type dynamique

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7077002B2 (en) 1999-12-17 2006-07-18 Per Sejrsen Method and an apparatus for measuring flow rates

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2982855B2 (ja) * 1994-09-20 1999-11-29 日本電気株式会社 半導体装置とその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730358A (en) * 1980-07-30 1982-02-18 Fujitsu Ltd Manufacture of semiconductor device
JPS62120072A (ja) * 1985-11-20 1987-06-01 Fujitsu Ltd 半導体記憶装置
JPH02226754A (ja) * 1989-02-28 1990-09-10 Toshiba Corp 半導体集積回路用キャパシタ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730358A (en) * 1980-07-30 1982-02-18 Fujitsu Ltd Manufacture of semiconductor device
JPS62120072A (ja) * 1985-11-20 1987-06-01 Fujitsu Ltd 半導体記憶装置
JPH02226754A (ja) * 1989-02-28 1990-09-10 Toshiba Corp 半導体集積回路用キャパシタ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7077002B2 (en) 1999-12-17 2006-07-18 Per Sejrsen Method and an apparatus for measuring flow rates

Also Published As

Publication number Publication date
JPH04242971A (ja) 1992-08-31

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