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WO1992000196A9 - Imprimante a reseau de del - Google Patents

Imprimante a reseau de del

Info

Publication number
WO1992000196A9
WO1992000196A9 PCT/US1991/004488 US9104488W WO9200196A9 WO 1992000196 A9 WO1992000196 A9 WO 1992000196A9 US 9104488 W US9104488 W US 9104488W WO 9200196 A9 WO9200196 A9 WO 9200196A9
Authority
WO
WIPO (PCT)
Prior art keywords
current
recording
image data
driver
printer apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1991/004488
Other languages
English (en)
Other versions
WO1992000196A1 (fr
Filing date
Publication date
Priority claimed from US07/543,929 external-priority patent/US5253934A/en
Priority claimed from US07/543,930 external-priority patent/US5126759A/en
Application filed filed Critical
Priority to EP91912735A priority Critical patent/EP0487715B1/fr
Priority to DE69122718T priority patent/DE69122718T2/de
Publication of WO1992000196A1 publication Critical patent/WO1992000196A1/fr
Anticipated expiration legal-status Critical
Publication of WO1992000196A9 publication Critical patent/WO1992000196A9/fr
Ceased legal-status Critical Current

Links

Definitions

  • the present invention relates to non-impact printer apparatus for recording, and more
  • circuitry thereon for controlling current uniformity to the recording elements specifically, to circuitry thereon for controlling current uniformity to the recording elements.
  • an L.E.D. (light emitting diode) printhead wherein control of current to the LED's during recording is provided by a current mirror circuit.
  • This circuit features an adjustable resistor and voltage supply to allow the respective currents to the LED's to be. controlled so that adjustments may be provided to have the outputs of the LED's be more uniform.
  • each driver chip is separately adjustable so that LED's driven from this driver chip receive sufficient current so that their respective
  • intensities are similar to that of LED's driven by other driver chips on this printhead.
  • Another aspect of adjustability requires the LED's to put out sufficient light to expose the recording medium such as a photoconductor.
  • temperature of the LED's is accommodated to ensure that the intensity from the LED's is consistent over time.
  • current to the LED's is regulated using digitally addressable current mirrors associated with each driver chip.
  • the multi-bit digital current regulation signals used must be communicated to the driver chips and adjustments in intensities of the LED's made accordingly. A problem therefore arises regarding the effect of temperature upon LED output and how to more accurately correct for temperature during use of the printhead.
  • V LED or V cc may occur as well as under conditions where LED's are being turned on and off at different times .
  • a non-impact printer apparatus that includes a recording head having a plurality of recording elements for recording on a recording medium; driving means including a plurality of current driving channels for selectively driving said plurality of recording elements in accordance with respective image data signals; the driving means further including an extra current driving channel not associated with a recording element for
  • a non-impact printer apparatus that includes a recording head having a plurality of recording elements for recording on a recording medium;
  • driving means for selectively driving said plurality of recording elements in accordance with respective image data signals
  • data bus means for carrying on said data bus means multibit image data signals determining a recording duration for a recording element and for carrying on one line of said data bus means also used for carrying image data signals, a multibit digital signal used for regulating a level of current to said recording element.
  • a non-impact printer apparatus comprising:
  • a recording head having a plurality of recording elements for recording on a recording medium
  • driving means for selectively driving said plurality of recording elements in accordance with respective image data signals
  • said driving means including a plurality of data register means with respective data register means associated with each recording element for storing said image data signals;
  • data bus means for carrying image data signals; means for commonly connecting said data bus means to said plurality of data register means;
  • a multistage shift register means for outputting sequentially at respective stages the token bit signal for sequentially selecting a respective data register means for accepting image data signals
  • said driving means further including current regulating means for regulating a level of electrical current to each recording element, the current regulating means being characterized by
  • the current regulating means further includes first register means including a plurality of registers for storing digital signals related to a level of current control, second register means for storing and shifting a token bit signal, and means responsive to a token bit signal in said second register means for latching in an appropriate
  • register of said first register means the multibit digital signal.
  • a non-impact printer apparatus used for recording comprising:
  • first digitally addressable current-conducting means for selectively establishing a first bias voltage in response to a first multibit digital signal
  • current-conducting means responsive to the first bias voltage and to a second multibit digital signal for generating a bias current and establishing a second bias voltage
  • a non-impact printer apparatus comprising: a series of point-like energizable radiation sources arranged in a row;
  • logic means responsive to the data signals for determining which of the point-llike radiation sources are to be selected for energization
  • the current driver means including a master circuit including a first transistor for generating a
  • reference current through said first transistor and a plurality of slave circuits for providing respective slave driver currents to the radiation sources selected for energization, means including (a) a plurality of individually selectively addressable current-conducting devices coupled to the master circuit, (b) first control means for selectively determining which of said plurality of devices are to be current conducting, and characterized by
  • bias responsive means responsive to an adjustment in voltage bias for increasing the reference current in response to the increase in the temperature of the printhead.
  • the invention also provides a non-impact printer apparatus, comprising:
  • driving means for energizing said recording elements, said driving means including current mirror means having a master circuit means for generating a reference current and a plurality of slave circuit means for providing respective driver currents to the recording elements selected for energization;
  • each slave circuit means including:
  • transistor switching means in series with a respective recording lement and switchable from one state to another in response to a signal and having a control electrode for controlling driver current to its respective recording element in response to the signal;
  • each of said slave circuit means further including its own additional slave circuit means for providing a current path for facilitating changing of the signal at the control electrode from one voltage level to another.
  • FIG. 1 is a perspective view illustrating the general arrangement of a prior art non-impact printer
  • FIG. 2 is a block diagram of a circuit for
  • FIG. 3 is a block diagram of a printhead
  • the printhead including a plurality of driver chips for driving the LED's formed on chip arrays;
  • FIG. 4 is a block diagram of a driver chip made according to one embodiment of the invention and used on the printhead of FIG. 3;
  • FIG. 5 is a circuit diagram of one circuit
  • FIGS. 6A, 6B, 6C, and 6D comprise a schematic of a current driving circuit incorporated on the driver chip of FIG. 4.
  • FIG. 7 is a block diagram of another embodiment of a printhead made according to the invention.
  • FIG. 8 is a block diagram of a driver chip for use on the printhead of FIG. 7;
  • FIG. 9 is a block diagram of an extra driver channel or current monitor channel for the driver chip of FIG. 8;
  • FIG. 10 is a schematic of a token bit register incorporated on the driver chip of FIG. 8;
  • FIG. 11 is a schematic of a token bit register incorporated on another embodiment of a driver chip that is a modification of that of FIG. 8;
  • FIG. 12 is a time line illustrating the
  • FIG. 13 is a truth table illustrating operation of the modified driver chip of FIG. 11.
  • the apparatus for the herein disclosed invention is typified by the diagram of FIG. 1; a linear array 10 of say 3584 triggerable recording elements; e.g. LED's, is disposed to expose selectively a
  • photosensitive image-receiver medium 12 that is movable relative to the array by suitable
  • Optical means for focusing the LED's onto the medium may also be provided.
  • gradient index optical fiber devices such as Selfoc (trademark of Nippon Sheet Glass Co., Ltd.) arrays are highly suited.
  • the LED's of the array are triggered into operation by means of image processing electronics 14 that are responsive to image signal information. Depending on the duration for which any given LED is turned on, the exposure effected by such LED is more or less made.
  • the medium 12 is, say, photographic film the latent image formed line by line by selective exposure of said LED's may be subsequently developed by conventional means to form a visible image.
  • the LED's may be used to form an electrostatic image on a uniformly electrostatically charged photoconductor and this image developed using opaque toner particles and perhaps transferred to a copy sheet, see U.S. Patent 3,850,517 and 4,831,395.
  • a data source 15 such as a computer, word processor, image scanner or other source of digitized image data, provides image data signals to a data processor 16 which may comprise a raster image processor.
  • the data processor under control of clock pulses from a logic and control device (LCU) 13 provides a
  • Data for each pixel may be represented by a multibit signal of say 4 bits representing a grey level for exposure for recording that pixel.
  • a programmable ROM (PROM) 16a may be provided either on or off the printhead to modify the data to provide for uniformity correction from LED to LED.
  • PROM programmable ROM
  • the PROM transforms the 4-bit signal into a 6-bit grey level signal that is adjusted or corrected for the light-emitting characteristics of the respective LED. This balance in light output from LED to LED can be corrected by modifying the data bit signals in accordance with empirical
  • the PROM has stored therein
  • this PROM may be modified in
  • the LCU provides exposure clock pulses to a down/up counter 18 (FIG. 4) which, when enabled by a signal from the LCU, counts such clock pulses and provides at an output having a plurality of lines a digital signal representation of the state of the counter.
  • a down/up counter 18 (FIG. 4) which, when enabled by a signal from the LCU, counts such clock pulses and provides at an output having a plurality of lines a digital signal representation of the state of the counter.
  • a counter has one line representing a least significant bit of such count and other lines representing other more significant bits.
  • the output of counter 18 is provided to a first set of input terminals to a comparator 19 associated with each recording element 30, i.e., LED in this embodiment.
  • a plurality of data lines from each of a plurality of corresponding data registers 24 is also provided to a second set of input
  • each comparator 19 all compare the output of the counter 18 with the value of the respective data.
  • the image data signals provided to each comparator relates to a desired ON time or period of enablement for a respective LED 30 for the recording of a particular pixel.
  • the LED's are alternately divided into odd and even-numbered LED's so that respective integrated circuit driver chips 40 therefor are located on opposite sides of the line of LED's.
  • the image data signals provided to each comparator 19 during the printing of a single line of dots by the row of LED's is related to the desired pixel or dot size to be exposed onto the image receiver medium by that LED for that particular line of dots.
  • six independent lines of data DI0 through DI5 provide a six bit digital image data signal that allows for grey- scale variation of the output of each LED during each cycle of operation.
  • the data to each comparator may comprise six binary bits representing an amount from decimal 0 to decimal 63.
  • the data lines DIO through DI5 are shown passing through the data registers 24 in FIG. 4, it will be appreciated that this is for the convenience of this illustration and that actually such lines comprise a plurality of data lines that are
  • T MIN represents a
  • the counter 18 In response to a start pulse on line LLATCHN, the counter 18 is enabled and commences to count exposure clock pulses from line 17 from decimal 63 to 0. Note that the clock pulses may be generated to have a variable programmable period.
  • the six bit output of counter 18 is coupled to one set of inputs at terminal X of each of the comparators. This count is now compared with the data input at another set of inputs at terminal Y of this comparator which represents in binary form decimal ten.
  • a pulse is provided at the output terminal of comparator 19 to cause latch or toggle flip-flop 22 to enable the constant current driver 23 to commence and maintain current to LED 1 .
  • the counter may be inhibited from counting additional clock pulses for a period T MIN that is either programmed into the counter or provided by other suitable means.
  • T MIN a period of time period
  • the counter is set to count in its up mode and commences counting clock pulses again.
  • the flip-flop 22 is reset and current to the LED ceases.
  • the other LED's, etc. operate in similar fashion but their data may require different count values to turn on and off. What these LED's will thus have in common is that all will have their respective current pulses centered, i.e., the midpoints of the respective current pulses will occur at the same time.
  • the pulse duration for each LED during each line of print is varied, however, in accordance with their respective image data signals.
  • correction for unequal light output from LED to LED may be provided by adjustment of the data in
  • a programmable read only memory device or PROM or other programmable device may store the
  • the PROM would modify data bits for that LED to reduce the count that otherwise would be provided at terminal Y based solely on the data.
  • the description of the circuitry forming a part of the driving circuitry for distributing the image data signals to the appropriate comparator and to current driving circuits will now be described.
  • the driving circuitry for the LED's are provided on opposite sides of the line of LED's 20. This is a known desirable arrangement for permitting LED's to be packed closer together to provide greater image resolution capabilities for the printer. As may be noted the circuit arrangement is an
  • the image data signals are output by the data processor 16 in accordance with image data signals for the odd-numbered LED's and image data signals for the even-numbered LED's. Discussion will now be made with regard to the image data signals for the odd-numbered LED's, since operation and circuitry for driving the even-numbered LED's is identical. With reference to FIG. 4, data lines DI0 - DI5 are
  • a token bit is used to enable a data register means associated with a particular LED to accept the data while other data register means associated with other LED's await their respective data.
  • the data register means 24 for each LED comprises a pair of latches 25, 26 or bi-stable multivibrators (msff - master-slave flip flops) for each of the six data lines.
  • the pair of latches are connected in a master- slave relationship wherein in response to a token bit signal at the enable input terminal of the master latch 25, an image data signal at the data input terminal of the master latch 25 will cause the output of the master latch to either change or remain the same depending upon the image data signal.
  • the six master latches 25 in the data register means of each LED are commonly
  • the token bit shift register 28 comprises a series of flip-flops 29 which have clock pulses
  • programmable control may be made of the direction for shifting the token bit along the token bit shift register 28.
  • the token bit is to be shifted from left to right in FIG. 4 for the
  • the signal line TDIR (token direction) is made at an appropriate logic level to allow the token bit on line LTOKEN to pass from left to right.
  • the token bit is passed from stage to stage (left to right in FIG. 4) of the token bit shift register 28 and accordingly outputted sequentially over respective lines 21 through OR gates 11 to lines 27 for enablement of all the master latches 25 of a respective data register 24.
  • the master latches 25 are now free to receive the image data signals for the next line of dots to be recorded.
  • the comparators 19 each have at an output an AND gate 19' and a D type flip-flop 19" in order to prevent the propagation of extraneous logic glitches from the comparator outputs to the toggle flip-flop inputs.
  • each driver chip 40 the current driving circuit 23 portion of each driver chip 40 is shown.
  • the respective outputs of the toggle flip-flops 22 are fed over respective lines 45 1 , 45 3 , and the following lines not shown
  • each of these lines is actually a double line one of which carries an enable signal to turn the respective LED on and the other carries a complement of this
  • the lines 45 1 are input to respective control electrodes of transistors Q 426 , Q 4 2 7 .
  • transistors act as switches and form a part of a current mirror driving circuit that includes a master circuit formed by transistors Q 424 , Q 425 and a series of digitally controlled transistors. More details concerning the digitally controlled transistors will be found below with reference to the discussion of FIGS. 6A and 6B. Briefly, these digitally controlled transistors may be selectively turned on to establish a signal I (CHIP BIAS) to thereby regulate a desired current level for the LED's driven by this driver chip. As may be noted in Figure 6C, circuitry for driving two LED's, i.e., LED 1 and LED 3 are illustrated; it being
  • Transistor Q 428 is biased to be always
  • transistor Q 429 is switched on and off and thus is the transistor controlling whether or not current is driven to LED 1 .
  • the gate or control electrode of transistor Q 429 is coupled to the drain-source connection of transistors Q 426 ,
  • transistor Q 427 When LED, is to be turned on, transistor
  • transistor Q 427 is made conductive and when LED, is to be turned off, transistor Q 426 is made conductive.
  • the gate of transistor Q 426 receives a logic signal that is the inverse of that to gate Q 4 2 7 from a data driven enabling means 22 that is the circuitry of FIG. 4 which controls whether or not an LED is to be turned on and for how long. As noted above in a grey level printhead, the LED is to be turned on for a duration determined by the grey level data signals input to the printhead.
  • an additional current mirror that includes two slave circuits.
  • One slave circuit comprises transistors Q 420 , Q 421 and Q 430 .
  • the other slave circuit comprises transistors Q 420 , Q 421 and Q 430 .
  • slave circuit comprises transistors Q 422 , Q 423 and Q 431 .
  • Transistors Q 430 , Q 431 are N-charmel
  • MOSFETS while the other transistors noted above are P-channel MOSFETS.
  • ILED 1 4 ma to LED 1 , the current through
  • transistor Q 421 might be 1/80 ILED, and the
  • transistor Q 423 might be 1/800 x ILED 1 .
  • the currents through these slave circuits establishes a voltage level V G2 on line 114, which is the potential of the drain electrode of transistor
  • transistor Q 426 In operation with transistor Q 429 turned off, transistor Q 426 is on and impresses approximately the voltage V cc at the gate of transistor Q 429 .
  • transistor Q 427 turns on, the capacitive load or change existing between its gate and substrate must be removed.
  • transistor Q 427 turns on, the charge on the gate terminal of transistor Q 429 discharges through transistors (Q 427 and Q 430 . This path for
  • transistor Q 429 Has its own respective path for discharge of its respective capacitive load. While the illustrated embodiment shows use of the illustrated embodiment
  • transistor Q 430 for use in discharging the control electrode of the driving transistor, it will be understood that in some circuit arrangements,
  • Q 431 is proportional to, i.e. mirrors, that through the master circuit because of the identical gate to source terminal biasing (V GS1 ) of transistors
  • transistor Q 422 remains constant.
  • the current through the circuit comprised of transistors Q 422 , Q 423 and Q 431 is mirrored by that through the
  • Transistor Q 429 acting as a cascode transistor and having its source terminal connected to the drain terminal of transistor Q 428 , thereby establishes the drain potential of the transistor Q 428 as
  • transistor Q 429 conducts current to LED, for a time period controlled by the data bits for recording an appropriate pixel.
  • the level of current for recording this pixel is controlled by the current mirror which is responsive to the current level I(CHIP BIAS).
  • I(CHIP BIAS) The circuit for generating I(CHIP BIAS) will now be described.
  • transistor Q 425 is equal to I(CHIP
  • this current, I(CHIP BIAS) in turn is controlled by three factors comprising a temperature compensated current source 172, a first group of eight digitally
  • non-digitally controlled NMOSFET transistor Q 33 non-digitally controlled NMOSFET transistor Q 33 .
  • non-digitally controlled NMOSFET transistor Q 13 non-digitally controlled NMOSFET transistor Q 13 .
  • Q 25 Q 32 are parallel connected transistors whose respective gate width to gate length ratios are scaled so that their respective currents are scaled or weighted in powers of two. For example, where eight digitally controlled transistors are provided for this first group (Q 25 -Q 32 ), respective gate
  • width to gate length ratios may be
  • Each digitally controlled device or transistor is controlled by a logic signal applied to a respective two-transistor switch circuit associated with the transistor.
  • the circuit defined by NMOSFET transistors Q 250 and Q 251 cause current to flov through transistor Q 25 when a high level logic signal is applied to the gate of transistor Q 250 and a complementary low logic signal is
  • the logic signals for controlling which of the current-carrying transistors are to be turned on are controlled by a register R 2 which stores an 8-bit digital word and its 8-bit complement representing a desired current control signal to turn on respective ones of the eight current conducting transistors Q 25 ,...Q 32 .
  • this group of transistors is used for "localized" control of LED current.
  • the digital word stored in register R 2 is specific for this driver chip and will be
  • This digital word may be input to the register R2 from memory in the LCU or from a separate memory such as a ROM provided on the printhead. This digital word may also be changed in response to the temperature of the driver chip as will be described below. Briefly, the level of current from an extra current mirror channel (#65) on each driver chip is used as a measure of temperature. A voltage generated by this current is digitized and compared by the LCU with a value based on the digital words in register Rl and R2. In response thereto, the LCU "writes" a new digital word into register R2, if a change in current level is required according to an algorithm stored in memory.
  • the LCU is programmed to provide or default to a particular set of digital words for placement into registers R 1 and R 2 .
  • the LCU may be programmed to maintain a count of prior activations of each LED and adjust a control voltage according to a program based on the aging characteristics of the printhead.
  • the affects due to aging vill generally be similar to all LED's and are corrected for by adjustment of an 8-bit digital word and its 8-bit complement stored in register R 1 .
  • This digital word controls 8 current-carrying NMOSFET transistors Q 5 ,..., Q 13 . Associated with this group of transistors is a continuously
  • register R 1 is the same as that stored in identical registers R 1 on the other driver chips. As the printhead ages, a new 8-bit digital vord and its 8-bit complement is calculated by the LCU and input into the registers R 1 . The calculation of this
  • 8-bit word for aging may be based on empirical determinations made using similar printheads or based upon a calibration of this printhead using an optical sensor that senses the output from each or selected LSD's or by sensing patches recorded on the
  • This current source includes a
  • V ⁇ thermo voltage
  • an output current, I o is provided that increases with an increase in temperature of the driver chip.
  • the operation of the circuit cf FIGS. 6A, B, C, and D will now be described.
  • the temperature adjusted current I o is conducted to ground via NMOSFET transistor Q 33 and some or all or none of the transistors Q 32 , Q 31 ,... and Q 25 depending upon the digital 8-bit signal and its 8-bit complement stored in register R 2 .
  • the voltage level at the source terminal of Q 33 is determined. Note that switching transistors are associated with each of these digially controlled transistors. For example, transistor Q 25 is controlled by switching
  • transistors Q 250 and Q 251 in response to a signal causing Q 250 to conduct and Q 251 to turn off.
  • V TC This voltage level
  • transistor Q 13 and thereby controls the current conducted by transistor Q 13 .
  • transistor Q 15 is the non-digitally controlled transistor associated with the digitally controlled transistor group Q 5 , ..., Q 11 , Q 12 .
  • transistors also have scaled or weighted
  • TMOSFET transistor Q 425 is equal to the current conducted by the master circuit comprised of
  • transistor Q 424 which current is replicated or sealed by current mirrors of PKOSFET slave
  • transistors Q 429 and Q 429 , ,...etc. i.e., the current controlling transistors to LED 1 ,
  • Transistor Q 429 is caused to conduct when its respective logic transistors Q 426 , Q 427 are
  • transistor Q 427 turns on and biases the gate of transistors Q 429 to the level V 42 . Since transistors Q 424 and Q 428
  • the current through transistor Q 429 will mirror cr be scaled to that of transistor Q 424 for the time period for exposing a pixel as controlled by the duration of the logic low signal on line 45' (AN).
  • the current through Q 429 is fed to LED 1 , for the recording of a pixel.
  • Identical current levels will be developed in the other channels directly providing current to respective other LED's.
  • all LED's driven by this driver chip receive the same current for periods determined by their respective enablement signals and the currents thereto are appropriately adjusted to maintain constant the intensity of the LED's.
  • lines SEL1 and SEL2 establish a two-bit selection of four possible operating modes of the token system.
  • the options for these modes include a normal mode; i.e., one where the token is used for
  • the fourth mode is referred to as a bias monitor mode and is used to check on the level of current sent to the LED's by sequentially operating channel 65 of each driver chip.
  • the logic set may be in the form of interconnected logic AND gates. With a "00" signal, this serial interface is disabled. Data over lines DI0-DI5 is then appropriately latched by the master image data flip-flops 25 in registers 24 as described above during shifting of the token bit over the token line LTOKEN and token registers 29. Data is then transferred in accordance vith the techniques
  • criterion may be a count of printing activations or time.
  • reference may be made to U.S. Patent 4,799,071.
  • the LCU provides a signal "01" to lines SEL2, SEL1 during a
  • latches 90-97 This enables latches 90-97 to be responsive to the token clock through AND gate 82.
  • the token bit carried on line LTOKEN is input via direction control gate 87 to latch register 90 and then shifted through associated latches 91-97 in response to the token clock signal TCLK.
  • the respective outputs of latches 90-97 are Input to the clock inputs of registers R 2 storing the R R E F ( 0 . 7 ) signals.
  • the data on line DI5 is latched by the token bit in latches 90-97, into the respective flip-flops 98a-h that comprise registers R 2 .
  • the current control data from the LCU for register R 2 is specific or local to each driver chip even though this data is carried on a data line of an image data bus that is commonly connected to all the R 2 registers of the driver chips located on one side of the rov of LED's.
  • bias monitor In this mode, current from an extra or 65th current driver channel on each driver chip is monitored by the LCU. In this mode, monitoring is done to
  • vhether or not the paver to the printhead should be effectively shut down or adjusted to avoid damage cr to better control output of the LSD's.
  • the monitoring of current serves to provide an indication of LED temperature and is useful to provide for a
  • V RE F and R REF adjustments are used to control the level of current to the LED's driven by a particular driver chip, finer control can also be provided by control also of the pulsevidfch duration of the LSD's through correction of image data.
  • vhere a cooling fas. for the printhead fails and the temperature of the printhead rises during printing.
  • the current level detected serves as a measure of temperature and when compared vith the digital words stored in registers R 1 and R 2 indicates that & problem exists; i.e., the current level being generated is not within an expected range based on the control signals stored in registers R 1 and R 2 ,
  • the LCU In the bia ⁇ monitor mode, the LCU provides a signal "11" to lines SEL1 and SEL2. This causes the token clock to be clocked through AND gate 99 to enable a bias monitor register 100 which receives at its "D” input an output from a logic AND gate 101 which has as its inputs the token bit and a single bit "data" signal on data line DI5, representing whether or not the LCU is calling for monitoring of the current on this driver chip. Recall that line DI5 is available to all driver chips (of the
  • FIG. 3 that is commonly connected to the respective transistors (Q T1 , Q T3 , Q T55 of all driver chips located on one side of the row of LED's.
  • the voltage level across the resistor R, 88, is related to the current on line 217 provided by transistor Q T1 , and this voltage level is sensed and converted by an analog to digital converter 89, A digital
  • the LCD may be to remove pover to the printhead by opening a suitable svitch to the power supply supplying the printhead such as removing voltages V cc and V DD to the current source 172
  • the LCU is
  • this mode is programmed to enter this calibration mode after such changes and on any pover-up operation or during an interframe. Assuming that sufficient time exists during recording this mode can also be entered during recording or during an interline time period.
  • the LCU may be programmed to provide current regulation data to the printhead to lover the current level until a safe level of current is detected. If none is detected, then the shutdown signal is generated to remove pover to the
  • the LCU in this mode may count the token clock pulses and is thus able to determine vhich of the driver chips has the unsafe level of current. Since the voltage signal sensed by the A/D converter is also related to the temperature of the LED's driven by that driver chip such signal may also be used by the LCU to provide fine adjustment of current to the LED's by changing the 8-bit local current regulating signal R REF stored in registers R 2 in response to an algorithm relating temperature
  • the signal relative to temperature may also be used to adjust the data signals to regulate or correct the on-time of the LED's using pulsewidth modulation.
  • the LCU may calculate a new correction program based on the fall off of intensity with temperature for the LED's. This new program is then input to the PROM 16a to adjust the corrected data sent to the
  • the 65th channels on the even driver chips are also commonly connected to the input of the A/D converter 89 (FIG. 3).
  • a reading of the voltage generated by a respective 65th driver channel on say an even-numbered driver chip is determined by having a logic high signal on the DI5 line on the even side with a corresponding low level signal on the DI5 line on the odd side since logic AND gate 101 (FIG. 5) on each driver chip passes the token bit only when the respective (odd or even) DI5 line is logic high.
  • the token bit is shifted down the 64-bit bidirectional token bit shift register 28 and image data on lines D 0 -D 7 is latched in a respective latch register 24.
  • the token bit then exits the shift register and is shifted into the shift register of the next driver chip.
  • Current monitoring is also activated during a portion of the period that the token bit is present in the driver chip's token bit shift register.
  • a signal from the LCU is used to generate current in the 65th driver channel. The means for activation of the 65th driver channel will now be described further with reference also to FIG. 9.
  • a latch 111 coupled with the extra, or in this example the 65th, driver channel has its output enabled or say placed logic high in response to the location of the token bit in a specific stage (N) of the token bit shift register 28.
  • the output of token bit register stage N is coupled via the logic gates 186, 190 and 187, 191, respectively, to the preset and clear inputs of latch 111.
  • Current to the 65th driver channel terminates when the token bit has moved a fixed number of stages (say M stages) down the token bit shift register 28 in this same driver chip 40.
  • the latch (111) output is disabled or cleared.
  • the output of token bit register stage N + M is coupled via the logic gates 188, 190 and 189, 191, respectively, to the preset and clear inputs of latch 111.
  • the outputs of all the current monitors or 65th channels of all the odd-numbered driver chips are connected in parallel to a current to voltage converter which may be similar to that described above. These outputs are multiplexed by multiplexer 106 with the similar outputs of the current monitors to the even-numbered driver chips.
  • An A/D converter 89 converts the analog signal which is also related to the
  • the LCU by keeping track of the counts of the token clock for use in shifting image data, knows which driver chip the token bit is located in and thus which driver chip's 65th channel is being activated at this time. Note that while data for recording the next line of pixels is being sent over bus lines D 0 -D 7 and latched in appropriate master registers in response to the token bit, the previous line of pixels, whose data is stored in the slave registers of latches 24, is being printed by the LED's while the 65th channel driver channel is also activated. Note, too, that even though the token bit is shifted simultaneously down even and odd-numbered driver chips 40, for example, driver chips #1 and #2 , or #3 and #4 or #55 and
  • the LCU recognizes that for a certain part of the period for which a token bit is resident within a driver chip (and for which the 65th channel
  • the monitored current input to the multiplexer 106 must be odd.
  • the LCU is programmed to consider the current
  • the LCU recognizes that when the token has moved 33 clock pulses into a token shift register of a driver chip (but less than 64 clock pulses) the signals generated by the A/D converter to the LCU represent current to the LED's in a driver chip that is the even-numbered driver chip of the pair of driver chips having the token bit. Additionally, a select signal is provided by the LCU to multiplexer 106, which controls which of the current signals, odd or even, is to be sent to the LCU. The overall clock token count determines which odd and even pair of driver chips the token is in. If desired, the extra current to voltage
  • converter and analog multiplexer may be omitted as in the printhead of FIG. 3.
  • a token direction signal biases line 220 at one logic level and through inverter 221, biases line 222 at an opposite logic level.
  • Tdir biases line 220 for transmission of the token bit that travels from left to right (Lbit) in FIG. 10.
  • the tristate inverters 31 used for transmission of the right to left going token bit are disabled.
  • the token bit is synchronized with pulses of the token clock (TCLK) and upon entering the driver chip, triggers the D input of the first token register of the token bit shift register to switch its outputs so that the Q output of the register is changed to enable the eight-bit latch 24 (FIG. 8) to latch the image data signals upon data bus lines D 0 -D 7 .
  • the first token register is reset and the token bit is shifted via a tristate inverter 31 from the Q output of the first token register to the D input of the second token register.
  • the second token register now has its Q output such that image data signals on the image data bus will be latched by the appropriate latch register associated with LED 3 .
  • the change of the Q output of the second token register simultaneously sets latch 111 (FIG. 9) which triggers the 65th current channel (FIG. 6D) to enable transistor Q ⁇ 1 to
  • a current IQ T1 which is identical to that simultaneously being driven through the LED's that are enabled for recording the prior line of pixels.
  • the current is monitored by the LCU via A/D converter 89 and in accordance with a program in the LCU the current is related to the temperature of the driver chip. This current is monitored until the token bit reaches the 32nd token register upon which event the Q output of this register resets latch 111. With movement of the token bit into the 33rd token
  • driver chip #1 the LCU commences' to monitor the current in the 65 driver channel of driver chip #2 as described above. As noted above, monitoring of the current is done first in driver chip #1 and then driver chip #2. The token bit then passes into driver chips #3 and #4 for monitoring the current in these chips as well as for latching of image data for these chips on lines D 0 -D 7 .
  • FIGS. 11-13 an improvement over the circuit of FIG. 10 is illustrated wherein in addition to use of the token bit for simultaneously controlling distribution of image data and use in monitoring current on driver chip temperature, there is also provided the use of the token bit for controlling the change of digital current regulation data in the driver chip just prior to recording each line of pixel data.
  • R REP or V REF digital current regulation data was provided during interframe or other non-production periods when no printing was occurring.
  • the digital current regulation data is provided during printing. This allows current not only to be monitored in real time but also to be changed more promptly as required.
  • a logic circuit 246 is provided in each driver chip to allow the circuit to discriminate between image data signals that control the pulsewidth time duration exposures used for recording the next row of image pixels or current regulation data signals which control the level of current to each LED activated during recording of the next row of pixels.
  • Data for adjusting R RE F is provided by the LCU based upon the temperature-related current signals generated by each of the respective current drivers for the 65th current channel of each driver chip. In response to these current signals, the LCU calculates a new 8-bit digital word for each driver chip to control the respective level of current in that driver chip. Simultaneously, a token bit is also generated on line Lbit and a control line labelled LD/Run is adjusted to a logic low level.
  • the line T dir is made a logic high level so that the logic circuit 246 has the four output lines thereof at suitable logic levels to disable the tristate inverters 31 associated with the image data token registers as well as disable the register 111 for disenabling the 65th current driver circuit.
  • the Q output of this register changes to provide a load signal to the latch register 113
  • the LCU changes the LD/Run line to a logic high level and a new token bit is sent by the LCU to the first driver chips (odd and even) on the printhead for latching the image data signals on data bus lines D 0 -D 7 .
  • a new token bit is sent by the LCU to the first driver chips (odd and even) on the printhead for latching the image data signals on data bus lines D 0 -D 7 .
  • register 111 will be set by the token bit to commence operation of the 65th channel current driver as described for the embodiment of FIGS. 7-9.
  • Another difference in the embodiment of FIG. 11 is the use of the first token register (rather than the second token register) to commence drive to the 65th channel current driver.
  • Other token registers may be
  • the LCU designed for determining when the 65th channel is to be operated. It may be desirable for the LCU to have a small programmed delay as to when the LCU actually reviews the current data from the A/D converter 89 (FIG. 7). This delay will allow the driver current in the 65th current channel to stabilize.
  • An improved printer apparatus has been described which provides for fine control over adjustments of current to the recording elements as well as for correction of pulsewidth durations as required for temperature compensation. There is also ensured that destructive current levels will not be generated when current to the recording elements are adjusted.
  • Image data from RIP 16 (FIG. 2) is a multibit digital signal indicating the level of grey of a pixel to be recorded by a particular LED.
  • this multibit data signal may be adjusted to correct for say the decrease in light output by the LED's driven by this driver chip due to the higher temperatures of the LED array chip driven by this driver chip.
  • the odd and even data from RIP 16 may be first modified by a correction PROM 16a before this data is sent to the printhead.
  • the correction PROM stores correction information so that an 8-bit word from RIP 16 is converted to a new 8-bit word that is corrected based on the temperature of the printhead to adjust pulsewidth duration.
  • the LCU signals the PROM as to the correction factor based on the temperature related data provided in reading the 65th driver current channels.
  • V REF and/or R REF by using an image data bus
  • the driver chip may also receive a global bias signal V REF that is received commonly by all driver chips. This signal V REF may be analog or digital.
  • FIGS. 11-13 demonstrating that data for providing further fine tune adjustment of current can be provided during each line of recording.
  • the described driver circuit retains the
  • a temperature compensated current source 172 advantageously and promptly increases current on a real-time basis by altering current to a series of digitally addressable
  • Multibit image data is effectively latched into appropriate registers in accordance with a token bit.
  • Current regulation is effectively controlled using digitally addressed current
  • an LED printhead having an improved driving circuit for generating driving current to the recording elements that provides for turn-on times that are relatively independent of the number of recording elements turned on and further provides for constancy in light output by making the driving current insulated from changes in the driver voltage.
  • Modifications to the circuit may, of course, be made.
  • transistors Q425 and Q423 are used effectively as resistors and may be also eliminated.
  • the current may be sensed in the driver channels of the recording elements.

Abstract

Imprimante sans impact comprenant une tête d'enregistrement dotée d'une pluralité d'éléments d'enregistrement (30) tels que des DEL permettant un enregistrement sur un support d'enregistrement (12). Une pluralité de puces de commande (40) est disposée sur la tête et elles comprennent chacune une pluralité de canaux conducteurs de courant destinés à commander une pluralité d'éléments d'enregistrement en fonction de signaux de données d'image respectifs. Les puces de commande (40) comprennent également chacune un canal conducteur de courant supplémentaire non associé à un élément d'enregistrement (30) afin de produire un courant apparenté à celui transmis auxdits éléments d'enregistrement. Le contrôle du courant dans le canal supplémentaire est assuré afin de permettre à des changements de courant transmis aux éléments d'enregistrement (30) et/ou à des données d'image corrigées de procédér à un réglage fin de l'uniformité des éléments d'enregistrement. Un miroir de courant à réglage numérique commande le niveau de courant transmis à chaque DEL pendant l'enregistrement. Des signaux de données de courant numérique destinés à commander ce niveau de courant sont également transmis par une des lignes du bus de données. On utilise des signaux binaires de jeton afin de réguler le verrouillage à la fois des signaux de données de courant et des signaux de données d'image dans des registres respectifs stockant les données numériques utilisées dans la régulation du courant et les données d'image utilisées dans la régulation des temps d'alimentation. Chaque puce de commande (40) comprend deux ensembles de transistors à adressage numérique. Cet agencement permet la régulation par puces individuelles de courant transmis aux DEL respectives afin de corriger la non-uniformité de la sortie de lumière de puce à puce due à des gradients de température, ainsi que la régulation de la sortie de lumière due au vieillisement de la tête d'impression. Le miroir de courant comporte un circuit pilote destiné à générer un courant de référence ainsi qu'une pluralité de circuits asservis destinés à fournir des courants de commande respectifs aux éléments d'enregistrement (30) sélectionnés pour recevoir une alimentation. Un commutateur à transistor est en série avec un élément d'enregistrement respectif (30) et peut être commuté d'un état à un autre en réponse à un signal au niveau de son électrode de commande. Chacun des circuits asservis comprend un circuit asservi supplémentaire formant un chemin de courant facilitant le changement du signal au niveau de l'électrode de commande d'un niveau de tension à un autre, par exemple en permettant à une charge capacitive au niveau de l'électrode de commande de se dissiper.
PCT/US1991/004488 1990-06-26 1991-06-25 Imprimante a reseau de del Ceased WO1992000196A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP91912735A EP0487715B1 (fr) 1990-06-26 1991-06-25 Imprimante a reseau de del
DE69122718T DE69122718T2 (de) 1990-06-26 1991-06-25 Drucker mit leuchtdiodenanordnung

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US54350790A 1990-06-26 1990-06-26
US54389290A 1990-06-26 1990-06-26
US543,930 1990-06-26
US07/543,929 US5253934A (en) 1990-06-26 1990-06-26 L.E.D. array printer with extra driver channel
US543,507 1990-06-26
US543,892 1990-06-26
US07/543,930 US5126759A (en) 1990-06-26 1990-06-26 Non-impact printer with token bit control of data and current regulation signals
US543,929 1990-06-26

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WO1992000196A1 WO1992000196A1 (fr) 1992-01-09
WO1992000196A9 true WO1992000196A9 (fr) 1995-04-13

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JP (1) JP3256225B2 (fr)
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US5859657A (en) * 1995-12-28 1999-01-12 Eastman Kodak Company Led printhead and driver chip for use therewith having boundary scan test architecture
JPH11126186A (ja) 1997-10-22 1999-05-11 Sony Corp コンピュータシステム、及び記録媒体
JP3906535B2 (ja) 1997-11-07 2007-04-18 ソニー株式会社 ダウンロードシステム、及び記録媒体
JP3732345B2 (ja) 1998-02-10 2006-01-05 株式会社沖データ 駆動回路、ｌｅｄヘッド及びプリンタ
ATE300065T1 (de) * 1998-05-01 2005-08-15 Zbe Inc Verfahren und gerät zum aufnehmen von digitalen bildern auf fotosensitivem material
JP4081858B2 (ja) 1998-06-04 2008-04-30 ソニー株式会社 コンピュータシステム、コンピュータ端末装置、及び記録媒体
JP3968875B2 (ja) 1998-06-24 2007-08-29 ソニー株式会社 ダウンロード装置、及び記録媒体
AU2573300A (en) * 1999-02-17 2000-09-04 Array Printers Ab Image forming device
JP4194580B2 (ja) 2004-06-02 2008-12-10 キヤノン株式会社 ヘッド基板、記録ヘッド、ヘッドカートリッジ、及び記録装置
JP4137088B2 (ja) * 2004-06-02 2008-08-20 キヤノン株式会社 ヘッド基板、記録ヘッド、ヘッドカートリッジ、記録装置、及び情報入出力方法
US9781800B2 (en) 2015-05-21 2017-10-03 Infineon Technologies Ag Driving several light sources
US9974130B2 (en) 2015-05-21 2018-05-15 Infineon Technologies Ag Driving several light sources
US9918367B1 (en) 2016-11-18 2018-03-13 Infineon Technologies Ag Current source regulation
CN120315266A (zh) * 2019-08-23 2025-07-15 佳能株式会社 具有顶部发射发光设备的图像形成装置

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