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WO1991008590A1 - Dispositif de detection d'images a charge couplee (ccd) du type a transfert interlignes, avec lecture non entrelacee, et avec structure d'electrode simplifiee pour chaque pixel - Google Patents

Dispositif de detection d'images a charge couplee (ccd) du type a transfert interlignes, avec lecture non entrelacee, et avec structure d'electrode simplifiee pour chaque pixel Download PDF

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Publication number
WO1991008590A1
WO1991008590A1 PCT/US1990/006819 US9006819W WO9108590A1 WO 1991008590 A1 WO1991008590 A1 WO 1991008590A1 US 9006819 W US9006819 W US 9006819W WO 9108590 A1 WO9108590 A1 WO 9108590A1
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WO
WIPO (PCT)
Prior art keywords
charge
electrodes
image sensor
shift register
sensor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1990/006819
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English (en)
Inventor
Eric G. Stevens
David L. Losee
Edward T. Nelson
Timothy John Tredwell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastman Kodak Co
Original Assignee
Eastman Kodak Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Co filed Critical Eastman Kodak Co
Priority to JP03501510A priority Critical patent/JP3100624B2/ja
Publication of WO1991008590A1 publication Critical patent/WO1991008590A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/15—Charge-coupled device [CCD] image sensors
    • H10F39/153—Two-dimensional or three-dimensional array CCD image sensors

Definitions

  • This invention relates to image sensing devices and, more particularly, to interline transfer type charge coupled imagers with non-interlaced read—out.
  • interline transfer type imaging devices photogenerated charge is collected on a photo charge collection site or photoreceptor, such as in a photodiode pn junction or under the gate of a photocapacitor, for a period of time and then transferred into a charge coupled register to be detected by an output circuit.
  • a photo charge collection site or photoreceptor such as in a photodiode pn junction or under the gate of a photocapacitor, for a period of time and then transferred into a charge coupled register to be detected by an output circuit.
  • a charge coupled register In an area array of such photocharge collection sites it is necessary to transfer the collected photocharge, first into a vertical shift register and then to a horizontal shift register, finally, reaching a charge sensitive detector or amplifier.
  • FIGS. 1 and 2 alternate rows of photoreceptors are read out in sequence, odd numbered rows being associated with one, so called, field, and even numbered rows associated with a second field.
  • a given row of pixels 10 is addressed by application of a voltage to electrodes 20 and 30 which are both connected to the same vertical clock, ⁇ , .
  • photocharge is transferred to the buried channel 40 of a vertical CCD shift register.
  • This vertical shift register is composed of buried channel 40, electrodes 20 and 30, which are connected to vertical clock ,, and electrodes 50 and 60 which are connected to vertical clock ⁇ 2 - These electrodes are separated from the substrate semiconductor 70 by an insulating layer 80.
  • the regions 65 beneath electrodes 30 and 60 are ion implanted to provide a potential energy difference between regions 25 and 26, controlled by the ⁇ -, clock, and between regions 55 and 56, controlled by the ⁇ 2 clock.
  • Such a non-interlaced read—out is desirable if the device is to be used in an electronically shuttered mode for still photography.
  • a complete vertical CCD shift register cell is required for each row of photodiodes since photocharge from all photodiodes must be transferred into the vertical shift register simultaneously and maintained as separate charge packets throughout transfer to the output amplifier.
  • each pixel would need to contain at least four separate CCD electrodes if a similar manufacturing process is to be used and the same number of clocking voltages maintained.
  • an interline transfer type area image sensor having an array of columns and rows of separate pixels and wherein charge collected in the pixels of each column is transferred into a vertical two-phase CCD, such CCD shift register comprising a series of overlapping electrodes, with each electrode being formed from a single level of conductor, separate voltage clocks connected to alternate electrodes, adjacent pairs of said electrodes constituting one complete stage of a CCD shift register, each column pixel being associated with one pair of a vertical CCD's electrodes, an ion implanted barrier region being formed under an edge of each electrode, and means for transferring charge from each pixel into a region under one of the corresponding electrodes .
  • the present invention employs a two-phase
  • CCD shift register which utilizes only one electrode for each clock phase, thus realizing a simplified non-interlaced read—out type device with improved ratio of photosensitive area to total pixel area.
  • This is accomplished by providing a vertical CCD shift register with ion implanted transfer barrier regions such that only one layer of gate electrode is required by each phase of the vertical shift register.
  • the design requires only two electrodes for each row of imaging sites and such a structure is not as subject to yield limitations due to intralevel short circuits, such as those caused by photomasking imperfections.
  • the self-alignment of the transfer barrier region implants assure excellent transfer efficiency in the CCD shift register.
  • FIG. 1 is a plan view of a typical prior art interlaced read—out type imaging device
  • FIG. 2 is a fragmentary, partially schematic vertical section view through a semiconductor device, taken along the lines A-A of FIG. 1, illustrating a prior art construction
  • FIG. 3a through FIG. 3c are partial plan views of various stages during the making of an interline transfer type area image sensor in accordance with the present invention
  • FIG. 4a, FIG. 4b and FIG. 4c are fragmentary, partially schematic cross-sectional views taken along the lines A 1 —A 1 , B—B and C—C of FIG. 3c, respectively
  • FIG. 5 is a fragmentary, partially schematic cross-section view of an alternative embodiment of the present invention.
  • an interline transfer type area image sensor has semiconductor substrate 100 provided with channel stop regions 110 and buried channel regions 120 as shown in plan view in FIG. 3a and in cross-sectional views in FIG. 4.
  • the substrate 100 may be a p—well diffused into an n-type silicon wafer.
  • An insulating oxide 125 is grown over the semiconductor surface and a single level layer of polysilicon conductor 130 is deposited. Barrier regions are provided in regions 140 by methods such as described by Losee et al in u.S. Patent 4,613,402, and illustrated in FIG. 3b.
  • an insulating layer of oxide 135 is grown over the polysilicon conductor 130 and a second barrier region 160 is provided by ion implantation of appropriate dopant atoms.
  • a second single level layer of polysilicon conductor is deposited and patterned to form CCD electrodes 170 (see FIG. 4b). Regions 180, which are not covered with the polysilicon conductors, are then implanted with appropriate impurities to form rows and columns of charge collection sites photoreceptors for collection of photogenerated charge.
  • FIG. 4a shows a cross section of a row of the interline area image sensor having pixels 180.
  • FIG. 4c shows in cross section a column of the interline area image sensor having pixels 180. In this position the layers 170 are directly above layers 130.
  • FIG. 4b is a cross section of one of the two-phase vertical CCD shift registers. Separate voltage clocks ⁇ , and 2 are respectively connected to alternating electrodes 130 and 170. As shown, the electrodes 170 overlap electrodes 130. To operate this device a positive going voltage pulse is applied to electrodes 130 which permits photogenerated charge from pixels 180 to transfer to the buried channel 120 beneath electrode 130 via the surface channel gap 191 (see FIG. 3a and FIG. 3b).
  • clock voltages ⁇ , and ⁇ are applied to transfer the photocharges to an appropriate charge detection circuit in a well known manner. In this way a non-interlaced read-out of the photogenerated charges is accomplished and each row of pixels 180 is associated with one pair of electrodes 170 and 130.
  • a voltage pulse is applied to simultaneously deplete all of the photoreceptor sites of any accumulated signal charge.
  • substrate 100 is a p-well diffused into an n—type wafer
  • a voltage pulse applied beweeen the p—well and the n—type wafer may be used to deplete the photoreceptor sites.
  • photocharges are generated by absorption of incident light.
  • all accumulated photoreceptor photocharges are transferred simultaneously into the vertical CCD shift register and read out as described above.
  • FIG. 5 An alternative embodiment of this invention is shown schematically in FIG. 5.
  • the charge collection regions of the device, 180 are connected to capacitor plates 200 through a conducting pillar 210.
  • a conducting pillar may be fabricated as described by -1- Raley et al, J. Electrochemical Soc. 135. 2640 (1988).
  • the capacitor plates are covered with a photoconducting layer 220 and top electrode layer 230. Photogenerated charge is transferred across the photoconductive layer and transferred to the charge collecting regions 180. This photocharge is then further transferred from regions 180 to the vertical shift register and read out as described in the preceeding paragraph.
  • a third embodiment of the present invention is one where the conductive electrodes 130 and 170 of the figures are composed of composite layers of polysilicon and one or more material selected from the group consisting of WSi , MoSi , TaSi , TiSi , W, Mo, or Ta.
  • n—type semiconductor doped to approximately 30 ohm-cm resistivity was provided with a p-type region by implantation of boron atoms with a dose of 1.0E+12 cm*''-2 and diffused to a depth of thickness of approximately 3.5 ⁇ m.
  • Channel stop barrier regions are formed by implantation of boron with a dose of 1.0E+13 cm**-2, and subsequently growing an oxide of thickness approximately 4000 A. An additional oxidation and subsequent etch—back reduces this oxide to a thickness of approximately 2500 A.
  • a buried channel region is formed by ion implantation of arsenic atoms, with a total dose 6.0E+12 cm**-2, and transfer gate oxide approximately 500 A thick, is grown in the charge transfer region and over the photodiode regions.
  • Polysilicon electrodes and edge aligned boron implanted barrier regions were then formed according to procedures described by Losee et al, U.S. Patent 4,613,402, and phosphorus was implanted into the photodiode region with a dose of 4.0E+12 cm**—2.
  • a thin oxide layer was grown at a temperature of 950 ⁇ C, in a wet ambient, for approximately 8 minutes.
  • An insulating layer was deposited by chemical vapor deposition, consisting of approximately 1000 A undoped oxide covered by 5000 A of oxide doped with approximately 4 wt% boron and 4 wt% phosphorus.
  • the device was subsequently annealed in an inert ambient for 30 minutes at a temperature of 900°C, contact openings were etched and an aluminum interconnect pattern was fabricated.
  • the pixel dimensions of this device were 9.0 ⁇ m, horizontally, by 9.0 ⁇ m vertically.
  • image sensors of the interline transfer type with non-interlaced read-out sequence may be required.
  • interline transfer type image sensing devices photogenerated charge is transferred from a pixel into a vertical CCD shift register.
  • interlaced read—out sequence alternate rows of pixels comprising one field are read out, one row at a time. Then, the second field, consisting of the remaining alternate rows of pixels, is read out.
  • the vertical shift CCD register structure in such a device is composed of two or more overlapping levels of polysilicon electrodes associated with each row of pixels.
  • this interlaced read-out is frequently not desirable and a non-interlaced read-out, wherein photogenerated charge from each row is transferred in sequence, is preferred.
  • a non-interlaced interline transfer imaging device with simplified structure, and, hence improved manufacturability is described.
  • the device utilizes two— hase vertical CCD shift registers with ion implanted barrier regions, which may be self—aligned, such as described by Losee et al U.S. Patent 4,613,402, to produce a device with the minimum number of two polysilicon electrodes associated with each pixel.
  • the device also provides improved topography for application of integral color filter arrays and maximizes the photosensitive area.

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  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

L'invention concerne un capteur d'images du type à transfert d'interlignes, qui fonctionne en mode non entrelacé et possède un réseau de colonnes et de rangées de photorécepteurs dans lesquelles la charge provenant de chaque pixel est transférée vers un étage d'un registre vertical CCD à décalage à deux phases, constitué par des électrodes adjacentes du dispositif CCD. Chaque électrode d'un étage possède une horloge de tension individuelle. Une zone barrière d'implantation ionique est prévue sous un des rebords de chaque électrode.
PCT/US1990/006819 1989-11-29 1990-11-28 Dispositif de detection d'images a charge couplee (ccd) du type a transfert interlignes, avec lecture non entrelacee, et avec structure d'electrode simplifiee pour chaque pixel Ceased WO1991008590A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03501510A JP3100624B2 (ja) 1989-11-29 1990-11-28 各ピクセルに対して簡易電極構造を備えた非インターレースインターライン転送型ｃｃｄイメージセンサ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US44353689A 1989-11-29 1989-11-29
US443,536 1989-11-29

Publications (1)

Publication Number Publication Date
WO1991008590A1 true WO1991008590A1 (fr) 1991-06-13

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Country Status (3)

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EP (1) EP0455803A1 (fr)
JP (1) JP3100624B2 (fr)
WO (1) WO1991008590A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992014265A3 (fr) * 1991-02-08 1992-10-29 Eastman Kodak Co Detecteur d'image comportant un dispositif a couplage de charge (ccd)
CN100578800C (zh) * 2006-12-19 2010-01-06 力晶半导体股份有限公司 图像传感器及其制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322753A (en) * 1979-06-08 1982-03-30 Nippon Electric Co., Ltd. Smear and/or blooming in a solid state charge transfer image pickup device
GB2103875A (en) * 1981-07-20 1983-02-23 Sony Corp Solid state image sensors
DE3600253A1 (de) * 1985-01-14 1986-07-17 Kabushiki Kaisha Toshiba, Kawasaki, Kanagawa Festkoerper-bildsensor
EP0265271A2 (fr) * 1986-10-23 1988-04-27 Sony Corporation Obturateur électronique pour une caméra électronique et méthode pour utiliser un capteur d'image CCD comme obturateur électronique pour une telle caméra
US4908518A (en) * 1989-02-10 1990-03-13 Eastman Kodak Company Interline transfer CCD image sensing device with electrode structure for each pixel

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322753A (en) * 1979-06-08 1982-03-30 Nippon Electric Co., Ltd. Smear and/or blooming in a solid state charge transfer image pickup device
GB2103875A (en) * 1981-07-20 1983-02-23 Sony Corp Solid state image sensors
DE3600253A1 (de) * 1985-01-14 1986-07-17 Kabushiki Kaisha Toshiba, Kawasaki, Kanagawa Festkoerper-bildsensor
EP0265271A2 (fr) * 1986-10-23 1988-04-27 Sony Corporation Obturateur électronique pour une caméra électronique et méthode pour utiliser un capteur d'image CCD comme obturateur électronique pour une telle caméra
US4908518A (en) * 1989-02-10 1990-03-13 Eastman Kodak Company Interline transfer CCD image sensing device with electrode structure for each pixel

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Extended Abstracts of The 16th Conference on Solid State Devices and Materials, 1984, (Kobe, JP), Shinji Uya et al.: "A high resolution CCD image sensor overlaid with an a-Si:H photoconductive layer", pages 325-328 *
Patent Abstracts of Japan, volume 12, no. 425 (E-681)(3272), 10 November 1988; & JP-A-63164360 (FUJI PHOTO FILM CO., LTD.), 22 November 1988 *
Patent Abstracts of Japan, volume 13, no. 114 (E-730)(3462), 20 March 1989; & JP-A-63285969 (NEC KYUSHU LTD), 22 November 1988 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992014265A3 (fr) * 1991-02-08 1992-10-29 Eastman Kodak Co Detecteur d'image comportant un dispositif a couplage de charge (ccd)
CN100578800C (zh) * 2006-12-19 2010-01-06 力晶半导体股份有限公司 图像传感器及其制作方法

Also Published As

Publication number Publication date
JP3100624B2 (ja) 2000-10-16
EP0455803A1 (fr) 1991-11-13
JPH05502757A (ja) 1993-05-13

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