WO1988007766A1

WO1988007766A1 - Ccd electrometer architecture

Info

Publication number: WO1988007766A1
Application number: PCT/US1988/000787
Authority: WO
Inventors: Edward T Nelson
Original assignee: Eastman Kodak Co
Current assignee: Eastman Kodak Co
Priority date: 1987-03-23
Filing date: 1988-03-14
Publication date: 1988-10-06
Anticipated expiration: 1989-09-23

Abstract

An electrometer for sensing the output signal charge of a CCD shift register employs a bipolar static induction transistor (BSIT) to sense signal charge. The BSIT operates in an emitter follower configuration so that the magnitude of the signal charge is reflected as a change in the BSIT emitter (36) potential. The BSIT may be made extremely small resulting in a very small floating diffusion capacitance, high responsivity and low noise characteristics.

Description

CCD ELECTROMETER ARCHITECTURE Technical Field

This invention relates to solid—state image sensors employing CCD shift registers to carry signal charges from photoelectric elements to an electrometer. In particular, the invention relates to a solid—state electrometer having low electrical noise characteristics, for converting the output signal charge from a CCD shift register into a voltage. Background Art

The resolution of image sensors is increased by increasing the number of photoelements of such sensors. Charge is collected by these photoelements and transferred to an output circuit which includes a floating diffusion (FD). This output circuit is adapted to convert charge into an output voltage. As the size of sensor elements decreases, the number of signal charge carrying particles (electrons) they collect also decreases. Unfortunately, as the number of electrons decreases, that portion of the output signal also decreases, and noise therefore becomes an increasingly significant component of any output signal. Improvements in image sensor technology have produced photoelements having near unit quantum efficiencies. Further improvements in device sensitivity must therefore concentrate on the reduction of intrinsic noise generated by the image sensor.

To date, the lowest noise performance has been achieved by devices that employ CCD shift registers to carry signal charges from the photoelectric elements to a remote electrometer. Current state of the art electrometers have intrinsic noise levels of about 50 electrons RMS. As shown in Fig. 2a, these electrometers typically employ a two-stage source follower having FET's Q and Q- to sense the change in potential of a "floating" junction diode when signal charge is moved onto the diode. The potential developed across first stage resistor R-, is applied to the gate of FET Q.. The 5 output voltage is produced across resistor R„. The ' dominant noise source in a two—stage source follower electrometers is usually the first stage. The electrometer includes a discrete floating diffusion junction diode, and two source follower stages.

1° In present electrometers, there are two dominant noise sources. These are thermal and 1/f noise current sources within the first stage MOSFET. .The thermal noise is proportional to 1/gm for MOSFET (and bipolar) devices. For a given input (gate to

I⁵ substrate, source and drain) capacitance, the MOSFET gm is typically lower than bipolar devices; and thus the thermal noise is higher. The 1/f noise is found only in MOSFET's.

Significant improvements in device

20 sensitivity would result if the noise generated by the electrometer were substantially reduced. Disclosure of the Invention

The object of the present invention is to reduce the noise introduced by an electrometer

25 employed to convert the output signal charge of a CCD shift register into a voltage.

This object is achieved by an electrometer for receiving charge from a CCD shi t register in an image sensor, such electrometer including a floating

30 base bipolar static induction transistor (BSIT) having base emitter and- collector electrodes, means for causing signal charge to be moved sequentially from the CCD shift register onto the transistor base, and the BSIT operating in a configuration so that the

³⁵ magnitude of the pixel charge is reflected as a change in the BSIT emitter potential. A BSIT is a bipolar transistor in which the base is depleted; and the emitter current is controlled¹by capacitive coupling to the external (un— epleted) base region.

The BSIT replaces the discrete floating 5 diffusion junction diode, source follower MOSFET transistor and the interconnection between the two devices typically found in prior art two stage sourpe follower electrometer architectures shown in Fig. 2a. Since a BSIT can be made extremely small, it can 10 provide a very small floating diffusion capacitance, high responsivity and low noise characteristics. Brief Description of the Drawings

Fig. 1 is an overall schematic view of a conventional frame transfer CCD area image sensor in ⁱ⁵ which the present invention may be embodied;

Fig. 2a is a schematic diagram of a prior art two stage source follower electrometer;

Fig. 2b is a schematic diagram of an electrometer employing a floating base bipolar static 0 induction transistor; and

Fig. 3 is a cross—sectional view taken along the lines 3-3 of Fig. 1 showing the output register and electrometer in accordance with this invention. Modes of Carrying out the Invention 5 The overall configuration of a conventional

CCD area image sensor 10 which can embody the present invention is shown in Fig. 1. The image sensor 10 includes four-phase (voltage lines Φ,—Φ₄) buried channel CCD area image sensor. Sensing ⁰ elements 12 define a two—dimensional array A which, for illustrative purposes only, is shown having 740 columns and 485 rows of photoelectric sensing elements 12. The sensing elements 12 are located in transfer channels 14 and a transparent electrode 16 overlies -- each row of sensing elements 12. Each transparent electrode 16 is connected to one line or phase of a our—phase clock signal. After exposure of the sensing elements 12 to an image, four clock signals on the voltage lines are sequentially applied in a well known manner to the transparent electrodes to move the charge pattern formed by the image in the sensing elements 12, one row at a time, to an output CCD register 18. Channel stops 20 are provided between adjacent transfer channels 14. Channel stops 20 may be provided by a thick field oxide,, by diffusion or implants.

The output CCD register 18 shown schematically in block form is a conventional four-phase CCD shift register positioned between a transfer gate 22 and a horizontal channel stop 24. Each cell of the output register 18 has four electrodes aligned with a transfer channel 14. These electrodes are actuated by signals on voltage lines φ.-φ, in a conventional manner. The transfer gate 22 is actuated by a transfer electrode T. and transfers a row of photocharges to the output register 18. Once the transfer of photocharges to the output register 18 has been completed, the register 18 is operated in a four—phase manner to transfer the photocharge to the electrometer 26. A cross—sectional view of the output register

18 and electrometer 26 taken along the lines 3—3 is shown in Fig. 3. The output register includes an n—type layer (arsenic) implanted into a p—type substrate 32. Charge can only be transferred in the right hand direction by means of conventional barrier implants not shown. Charge in the channel 18 under an electrode 17 is formed between an output gate 28 and a reset gate 30 of the CCD output register 18. The p—type substrate 32 of the output register 18 serves as the collector of a BSIT. An insulating layer 33 (SiO_) is formed on the substrate 32. The output gate 28 has a positive potential continuously applied to it. If we assume electrons are held under the last electrode of the CCD 18, and its potential is lowered, a potential hill is formed and electrons will flow into the base 34 of the BSIT. After the charge is converted to ah output voltage, a positive potential is applied (via Φ_RG) to the reset gate

33 which causes the charge to be delivered from base

34 to reset diffusion 38. Conventional solid state fabrication techniques are utilized to form a base 34 of an N-type material and the emitter 36 of a p—type material. In order to insure good BSIT electrical characteristics it is important to establish the correct channel aspect ratio (w/L as shown in Fig. 3). This requires that the depth of the emitter metallurgical junction 36 be shallow when compared to the depth of the base metallurgical junction. There are several alternative methods for making a shallow emitter, including BF₂ ion implantation with rapid thermal annealing or doping out of a polysilicon plug. Turning to Fig. 2b, we see in schematic form the circuit shown in Fig. 3. The BSIT is in the first stage of the output circuit and an FET Q₃ is in the second stage. When the charge is delivered to the base 34, a change in the BSIT emitter potential (which is also the voltage drop across R-) is seen at the gate electrode of the second stage FET Q.,. The emitter follower configuration is preferred because of its high input and low output impedence. The output voltage V is produced across the second stage resistor R_? in the conventional manner. The resistor R. is connected in series with the source and drain of FET Q_. Signal charge is moved sequentially onto the BSIT base 34, pixel-by-pixel, as the output register 18 is clocked in a conventional manner. The BSIT operates in a emitter follower configuration so that the magnitude of the signal charge is reflected as a change in the BSIT emitter potential. Signal charge is removed from the BSIT base through the operation of the reset gate 30 and reset diffusion 38 which resets the base potential prior to the arrival of the next pixel signal charge.

The BSIT may be made extremely small, on the order of 2μm by 2μm which results in a very small floating diffusion capacitance. The dominant capacitance in the BSIT is the emitter—base sidewall capacitance which is a fraction of the floating . diffusion node capacitance found in prior art electrometers. The reduction of this capacitance^* is a significant factor in reducing Johnson (thermal) noise. Industrial Applicability and Advantages

The transconductance of a BSIT is typical of a punched—through bipolar device and is approximately five times larger than that of a conventional MOSFET source follower of the same input capacitance. This will result in less thermal noise and lower emitter follower output impedance. The lower output impedance permits higher clocking rates. While the invention w.as described as incorporated in a solid state imaging device, it is readily apparent that the invention could be incorporated in any device requiring the detection of signal charge from a CCD shift register such as a memory device.

Claims

1. An electrometer for receiving charge from a CCD' shift register in an image sensor or the like, such electrometer being characterized by: a

5. floating base bipolar static induction transistor (BSIT) having base, collector and emitter electrodes, means for causing signal charge to be moved sequentially from the CCD shift register onto the transistor base, the BSIT operating in a ° con iguration so that the magnitude of the pixel charge is reflected as a change in the BSIT emitter potential.

2. An output device for an image sensor having an output CCD comprising the electrometer of 5 claim 1; and an output FET responsive to the change in emitter potential to produce an output voltage.

3. The device as set forth in claim 2, wherein the BSIT is a pnp transistor.