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WO1987004566A1 - Interconnexion pour un ensemble integre a l'echelle d'une tranche - Google Patents

Interconnexion pour un ensemble integre a l'echelle d'une tranche Download PDF

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Publication number
WO1987004566A1
WO1987004566A1 PCT/US1986/002805 US8602805W WO8704566A1 WO 1987004566 A1 WO1987004566 A1 WO 1987004566A1 US 8602805 W US8602805 W US 8602805W WO 8704566 A1 WO8704566 A1 WO 8704566A1
Authority
WO
WIPO (PCT)
Prior art keywords
assembly
wafers
wafer
emitting
optical signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1986/002805
Other languages
English (en)
Inventor
Lawrence Anthony Hornak
Stuart Keene Tewksbury
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Priority to JP87502051A priority Critical patent/JPS63502315A/ja
Publication of WO1987004566A1 publication Critical patent/WO1987004566A1/fr
Priority to KR870700843A priority patent/KR880701024A/ko
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F55/00—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto
    • H10F55/20—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto wherein the electric light source controls the radiation-sensitive semiconductor devices, e.g. optocouplers
    • H10F55/25—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto wherein the electric light source controls the radiation-sensitive semiconductor devices, e.g. optocouplers wherein the radiation-sensitive devices and the electric light source are all semiconductor devices
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections

Definitions

  • This invention relates to integrated-circuit chips and, more particularly, to an assembly that comprises a stack of wafers each of which includes multiple interconnected chips.
  • the integrated-circuit art it is known to utilize a pattern of lithographically formed conductors on a semicon uctor wafer to interconnect a number of semiconductor chips and to connect the chips to input/output pads on the wafer.
  • the chips to be interconnected are mounted on the surface of the wafer or in recesses formed in the wafer surface.
  • the chips are fabricated in the wafer as integral parts thereof.
  • wafer-scale-integrated (WSI) assemblies wafer-scale-integrated
  • WSI assemblies are potentially faster than approaches based on individually packaged chips mounted and interconnected on a standard pr inted-circuit board.
  • the size of the chip package limits the density of circuits in a system.
  • circuits can be packed extremely close together on a single wafer, thus avoiding the major size limitations imposed by package size and thereby enabling faster performance due to substantial decreases in chip interconnection lengths.
  • the desire to achieve a high degree of parallelism in WSI architectures has led to the development of three-dimensional assemblies comprising stacks of wafers of the type described above. In such a stacked-wafer assembly, multiple vertical connections are provided between wafers.
  • WSI assembly Multiple wafers each including integrated- circuit chips are stacked to form a WSI assembly.
  • Connections are established between wafers in the assembly by sending optical signals from the surface of one wafer to the surface of another. In accordance with the invention, these signals are transmitted directly through the material of one or more wafers in the 5 assembly.
  • FIG. 1 i s a s impl ified schematic representation of a portion of a WSI assembl y compr is ing a chip-conta ining wafer and an assoc iated pl anar i zing 0 " member wh ich embody features o f the present invention ;
  • F IG . 2 shows two o f the FIG . 1 arrangements together wi th a cover pl ate ;
  • FIG . 3 represents the FIG . 2 components combined to form a stacked-wafer assembly; 5 and FIG. 4 ill ustrates in cross- section a portion of a spec i f ic il lustrative WSI assembly made in accordance with the pr inc iples o f the present invention .
  • each board illustrated is a modified version of a known board in which multiple integrated-circuit chips are attached by face-down solder bonding to microminiature interconnections formed on the surface of a silicon wafer.
  • Such known boards are described, for example, in "Wafer-Chip Assembly for Large-Scale
  • additional chips comprising optical emitters and detectors are also attached to the interconnections on the silicon wafers.
  • connections between boards are made by transmitting optical signals through the silicon material of the wafers between respective emitters and detectors.
  • the board (FIG. 1) comprises a silicon wafer 10 having multiple chips solder bonded thereto. Only six of these chips, respectively designated by reference numerals 12 through 16, are shown in FIG. 1. Some of these chips comprise very-large-scale-integrated (VLSI) chips and others comprise optical emitters and/or detectors.
  • VLSI very-large-scale-integrated
  • FIG. 1 also indicates, by dashed lines 18, that the chips 12 through 16 are interconnected.
  • the interconnections 18 comprise lithographically formed power and ground conductors and X- and Y-signal conductors respectively disposed in spa ⁇ ed-apart levels overlying the upper surface of the wafer 10.
  • the signal conductors comprise aluminum or copper lines each about 2 micrometers (ym) thick and approximately 10 ⁇ wide. In some cases, it is advantageous to form the ground plane on the lower surface of the wafer 10. Such a particular illustrative case will be specified below in connection with the description of FIG. 4.
  • the resulting single-wafer assembly has a nonplanar top exhibiting multiple protuberances.
  • planarizing member 20 of the type shown in FIG. 1.
  • the member 20 of FIG. 1 also comprises a silicon wafer.
  • the member 20 includes openings therethrough in exact registry with and slightly larger in size than the respective chips 12 through 16 on the wafer 10.
  • the thickness of the wafer 20 is slightly greater than the extent by which the most protruding one of the chips 12 through 16 extends above the surface of the assembly. In that way, when the assembly and the member 20 are brought together into intimate contact, a planar surface devoid of protuberances (but with openings therein) is achieved.
  • the planarizing member 20 of FIG. 1 includes only recesses in the bottom surface thereof. These recesses are formed in respective registry with the chips 12 through 16 and are appropriately sized to accommodate the full height of . the chips. In that case, a truly planar top surface is realized when the member 20 and the wafer 10 are combined to form a composite WSI assembly.
  • Various techniques are available for aligning the member 20 (FIG. 1) with respect to its associated chip-carrying wafer 10. One way of doing this is to include projections 22 through 24 on the wafer 10. These are designed to mate with corresponding openings (not shown in FIG. 1) formed in the bottom side of the member 20.
  • FIG. 2 shows two composite WSI assemblies, each of the type represented in FIG. 1, designed to be stacked together.
  • One assembly comprises planarizing member 26 and chip-carrying wafer 28.
  • the wafer 28 includes seven chips mounted thereon in alignment with respective openings ir. the member 26.
  • the other assembly which, for example, includes five chips, comprises planarizing member 30 and chip-carrying wafer 32.
  • projections 34 through 36 are included on the top surface of the member 30. These are intended to mate with correspon ing openings (not shown) formed in the bottom of the wafer 28.
  • a protective cover plate may be added.
  • Such a cover comprising a silicon wafer 38 is shown in FIG. 2.
  • FIG. 3 An assembled stack of wafers is depicted in FIG. 3. This particular illustrative stack includes the constituent elements described above and shown in FIG. 2.
  • FIG. 4 represents a portion of an illustrative WSI assembly made in accordance with the invention.
  • the depicted assembly comprises a silicon planarizing member 40 sandwiched between two chip-carrying silicon wafers 42 and 44.
  • each of the wafers 42 and 44 of FIG. 4 is shown as having two optical components mounted thereon.
  • the wafer 42 includes optical- signal emitter 46 and optical-signal detector 48
  • the wafer 44 includes optical-signal emitter 50 and optical-signal detector 52.
  • each wafer in the WSI assembly may include a multitude of optical emitters and detectors.
  • the emitters 46 and 50 comprise lasers or light-emitting diodes designed to provide optical output signals at a wavelength in the range of about 1.1-to- 10 ⁇ m.
  • silicon even if highly doped to render it conductive
  • signals propagated downward by the emitter 46 toward the detector 52 will be transmitted through the silicon wafer 42 and the silicon member 40 in a relatively low-absorption way.
  • signals from the emitter 50 will be propagated upward through the member 40 and the wafer 42 in a low-absorption manner to impinge upon the detector 48.
  • the emitters 46 and 50 of FIG. 4 may each comprise a laser unit designed to emit at 1.3 or 1.55 ⁇ m.
  • a unit may comprise, for example, an edge-emitting laser combined with a parabolic mirror in microminiature chip form.
  • the optical emitters 46 and 50 and the optical detectors 48 and 52 of FIG. 4 comprise standard discrete elements or monolithic arrays that are fabricated and tested as individual components and then mounted in place and interconnected (for example by face-down solder bonding) to associated circuitry on their respective wafers.
  • the emitters or detectors may be fabricated in place in the wafers 42 and 44 as integral parts thereof.
  • silicon photodetectors can be made in that manner directly in the silicon wafers.
  • optical emitters and detectors can then also be made in place as integral parts of the wafers.
  • Each of the wafers 42 and 44 also typically includes multiple VLSI chips.
  • these integrated-circuit chips are indicated by elements 54 and 56 which are representative of discrete individual chips that have been bonded and interconnected on their respective wafers.
  • all the integrated circuitry, except for interconnects, included on the wafers 42 and 44 of FIG. 4 are embodied in the form of discrete individual chips mounted thereon.
  • some or all "of the integrated circuitry is formed in surface portions of the wafers as integral parts thereof.
  • FIG. 4 exemplifies both approaches.
  • FIG. 4 schematically shows integrated-circuit portions 58 and 60 formed within the wafers 42 and 44, respectively. These portions constitute, for example, bipolar or metal-oxide- semiconductor driver circuitry respectively associated with and connected to the optical emitters 46 and 50.
  • Surface regions 62 and 64 (FIG. 4) on the wafers 42 and 44 respectively represent multi-layer interconnection circuitry of the depicted WSI assembly. Thus, these regions include interleaved layers of insulating and conducting materials such as polyimide and aluminum or copper, as is well known in the art.
  • the regions 62 and 64 or some parts thereof may include additional layers of materials such as silicon dioxide and/or silicon nitride.
  • wafers 42 and 44 of FIG. 4 include ground planes 66 and 68 on the bottom surfaces thereof. These planes on the wafers 42 and 44 comprise, for example, 2- ⁇ m-thick layers of a conductive material such as aluminum or copper. To effect electrical connections between these ground planes and conductors in the surface regions 62 and 64, it is necessary that the wafers 42 and 44 or at least portions thereof be highly doped to render them conductive.
  • the ground plane 66 is patterned to provide openings through which optical signals are propagated between the wafers 42 and 44 in the depicted WSI assembly. Such patterning typically enhances transmission by minimizing signal reflections and providing signal containment.
  • any highly absorptive or reflective layers in the surface region 62 underlying the components 46 and 48 are advantageously removed.
  • the region 62 includes layers of materials such as silicon dioxide and/or silicon nitride underlying the components 46 and 48, it is generally advantageous where possible to control the thicknesses of these layers to render them substantially antireflective.
  • the illustrative planarizing member 40 shown in FIG. 4 includes recesses 70 through 72 formed in the bottom surface thereof. These recesses are designed to completely encompass the respective components 56, 50 and 52 when the bottom surface of the member 40 is brought into intimate contact with the top surface of the eg ion .64.
  • an antireflective coating 74 is included on the bottom surface of the member 40 (FIG. 4) .
  • a portion 76 of this layer is preferrably patterned to form a zone-plate lens for focusing optical signals emanating from the emitter 50 and directed at the detector 48.
  • the zone-plate lens 76 may be formed at other levels in the path between optical components or, if optical signal levels are adequate, may be left out altogether.
  • an air gap will invariably exist between at least some portions of the bottom surface of the member 40 and the top surface of the wafer 44, and between the member 40 and the wafer 42.
  • any gaps that do exist are preferrably designed to be much greater than the wavelength of the propagating optical signals.
  • the top surface of the planarizing member 40 of FIG. 4 includes, for example, a layer 78 of a material such as silicon nitride and a metallic layer 80.
  • the layer 78 is proportioned to be antireflective, and the layer 80 is patterned to provide apertures that help to confine propagating optical beams.
  • a zone-plate lens 82 is formed in the layer 78 for the purpose of focusing optical signals emanating from the emitter 46 and directed at the detector 52.
  • the structure of FIG. 4 also includes protuberances 84 through 86 and mating holes 87 through 89 utilized for the purpose of aligning the member 40 and the wafers 42 and 44.
  • the depicted structure can be held together in any one of a number of standard ways.
  • a suitable mechanical clamp (not shown) may be employed for this purpose.
  • an adhesive disposed on peripheral portions of the member 40 and the wafers 42 and 44 may be utilized to maintain the assembly together.
  • the instrumentality used should allow for easy disassembly of the depicted structure. In that way, repair or modification of the WSI assembly is facilitated.
  • Other wafers and planarizing members can be added to the structure shown in FIG.
  • WSI assemblies can take many forms, many of which can incorporate the present invention.
  • the assemblies can be made of other optically transparent materials, such as gallium arsenide.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Un ensemble est obtenu en empilant plusieurs plaques en silicium intégrées à l'échelle d'une tranche. Des connexions entre des niveaux de l'ensemble sont réalisées par des signaux optiques transmis directement au travers des plaques de silicium.
PCT/US1986/002805 1986-01-21 1986-12-24 Interconnexion pour un ensemble integre a l'echelle d'une tranche Ceased WO1987004566A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP87502051A JPS63502315A (ja) 1986-01-21 1986-12-24 ウエハサイズで集積化されたアセンブリの相互接続
KR870700843A KR880701024A (ko) 1986-01-21 1987-09-18 웨이퍼 조립체

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US820,624 1977-08-01
US82062486A 1986-01-21 1986-01-21

Publications (1)

Publication Number Publication Date
WO1987004566A1 true WO1987004566A1 (fr) 1987-07-30

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Application Number Title Priority Date Filing Date
PCT/US1986/002805 Ceased WO1987004566A1 (fr) 1986-01-21 1986-12-24 Interconnexion pour un ensemble integre a l'echelle d'une tranche

Country Status (4)

Country Link
EP (1) EP0253886A1 (fr)
JP (1) JPS63502315A (fr)
KR (1) KR880701024A (fr)
WO (1) WO1987004566A1 (fr)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2222720A (en) * 1988-09-12 1990-03-14 Stc Plc Opto-electronic devices
EP0335104A3 (fr) * 1988-03-31 1991-11-06 Siemens Aktiengesellschaft Dispositif pour relier optiquement un ou plusieurs émetteurs optiques d'un ou plusieurs circuits intégrés
US5150196A (en) * 1989-07-17 1992-09-22 Hughes Aircraft Company Hermetic sealing of wafer scale integrated wafer
EP0494514A3 (en) * 1991-01-10 1993-01-27 American Telephone And Telegraph Company Articles and systems comprising optically communicating logic elements
EP0526776A1 (fr) * 1991-08-06 1993-02-10 International Business Machines Corporation Dispositif d'interconnexion optique à grand vitesse
EP0532469A1 (fr) * 1991-09-10 1993-03-17 Centre Suisse D'electronique Et De Microtechnique S.A. Procédé pour positionner un premier substrat sur un second substrat et dispositif micromécanique de positionnement obtenu
DE4211899A1 (de) * 1992-04-09 1993-10-21 Deutsche Aerospace Verfahren zur Herstellung eines Mikrosystems und daraus Bildung eines Mikrosystemlasers
EP0599212A1 (fr) * 1992-11-25 1994-06-01 Robert Bosch Gmbh Dispositif de couplage d'un guide d'ondes lumineuses avec un élément émettant ou recevant de la lumière
EP0603549A1 (fr) * 1992-11-25 1994-06-29 Robert Bosch Gmbh Dispositif de connexion d'au moins un élément émittant de la lumière avec au moins un élément recevant de la lumière
EP0634676A1 (fr) * 1993-07-15 1995-01-18 Robert Bosch Gmbh Arrangement de couplage au moins une fibre optique avec au moins un élément émetteur-récepteur optique et procédé de sa fabrication
DE4005003C2 (de) * 1990-02-19 2001-09-13 Steve Cordell Verfahren zur Unterbindung des Kenntnisgewinnens derStruktur oder Funktion eines integrierten Schaltkreises
US20120013368A1 (en) * 2001-10-15 2012-01-19 Micron Technology, Inc. Method and system for electrically coupling a chip to chip package

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05251717A (ja) * 1992-03-04 1993-09-28 Hitachi Ltd 半導体パッケージおよび半導体モジュール

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3663194A (en) * 1970-05-25 1972-05-16 Ibm Method for making monolithic opto-electronic structure
US3748548A (en) * 1964-08-18 1973-07-24 Texas Instruments Inc Three-dimensional integrated circuits and method of making same
US4169001A (en) * 1976-10-18 1979-09-25 International Business Machines Corporation Method of making multilayer module having optical channels therein
WO1984000822A1 (fr) * 1982-08-19 1984-03-01 Western Electric Co Reseau de circuit integre couple optiquement
FR2537825A3 (fr) * 1982-12-10 1984-06-15 Thomson Csf Mat Tel Systeme d'interconnexion de cartes de circuit imprime

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3748548A (en) * 1964-08-18 1973-07-24 Texas Instruments Inc Three-dimensional integrated circuits and method of making same
US3663194A (en) * 1970-05-25 1972-05-16 Ibm Method for making monolithic opto-electronic structure
US4169001A (en) * 1976-10-18 1979-09-25 International Business Machines Corporation Method of making multilayer module having optical channels therein
WO1984000822A1 (fr) * 1982-08-19 1984-03-01 Western Electric Co Reseau de circuit integre couple optiquement
FR2537825A3 (fr) * 1982-12-10 1984-06-15 Thomson Csf Mat Tel Systeme d'interconnexion de cartes de circuit imprime

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, Vol. 7, No. 119, (E-177) (1264) 24 May 1983 & JP, A, 5837977 (Matsushita Denki Sangyo K.K.) *

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0335104A3 (fr) * 1988-03-31 1991-11-06 Siemens Aktiengesellschaft Dispositif pour relier optiquement un ou plusieurs émetteurs optiques d'un ou plusieurs circuits intégrés
GB2222720A (en) * 1988-09-12 1990-03-14 Stc Plc Opto-electronic devices
GB2222720B (en) * 1988-09-12 1992-03-25 Stc Plc Opto-electronic devices
US5150196A (en) * 1989-07-17 1992-09-22 Hughes Aircraft Company Hermetic sealing of wafer scale integrated wafer
DE4005003C2 (de) * 1990-02-19 2001-09-13 Steve Cordell Verfahren zur Unterbindung des Kenntnisgewinnens derStruktur oder Funktion eines integrierten Schaltkreises
EP0494514A3 (en) * 1991-01-10 1993-01-27 American Telephone And Telegraph Company Articles and systems comprising optically communicating logic elements
EP0526776A1 (fr) * 1991-08-06 1993-02-10 International Business Machines Corporation Dispositif d'interconnexion optique à grand vitesse
CH685522A5 (fr) * 1991-09-10 1995-07-31 Suisse Electronique Microtech Procédé pour positionner un premier substrat sur un second substrat et dispositif micromécanique de positionnement obtenu.
EP0532469A1 (fr) * 1991-09-10 1993-03-17 Centre Suisse D'electronique Et De Microtechnique S.A. Procédé pour positionner un premier substrat sur un second substrat et dispositif micromécanique de positionnement obtenu
WO1993021551A1 (fr) * 1992-04-09 1993-10-28 Deutsche Aerospace Ag Procede de fabrication de microsystemes et formation d'un laser a base d'un tel microsysteme
DE4211899A1 (de) * 1992-04-09 1993-10-21 Deutsche Aerospace Verfahren zur Herstellung eines Mikrosystems und daraus Bildung eines Mikrosystemlasers
DE4211899C2 (de) * 1992-04-09 1998-07-16 Daimler Benz Aerospace Ag Mikrosystem-Laseranordnung und Mikrosystem-Laser
EP0599212A1 (fr) * 1992-11-25 1994-06-01 Robert Bosch Gmbh Dispositif de couplage d'un guide d'ondes lumineuses avec un élément émettant ou recevant de la lumière
EP0603549A1 (fr) * 1992-11-25 1994-06-29 Robert Bosch Gmbh Dispositif de connexion d'au moins un élément émittant de la lumière avec au moins un élément recevant de la lumière
EP0634676A1 (fr) * 1993-07-15 1995-01-18 Robert Bosch Gmbh Arrangement de couplage au moins une fibre optique avec au moins un élément émetteur-récepteur optique et procédé de sa fabrication
US20120013368A1 (en) * 2001-10-15 2012-01-19 Micron Technology, Inc. Method and system for electrically coupling a chip to chip package
US9305861B2 (en) * 2001-10-15 2016-04-05 Micron Technology, Inc. Method and system for electrically coupling a chip to chip package

Also Published As

Publication number Publication date
KR880701024A (ko) 1988-04-13
JPS63502315A (ja) 1988-09-01
EP0253886A1 (fr) 1988-01-27

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