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WO1983001160A1 - Agencement de circuits semiconducteurs a multietages - Google Patents

Agencement de circuits semiconducteurs a multietages Download PDF

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Publication number
WO1983001160A1
WO1983001160A1 PCT/US1981/001253 US8101253W WO8301160A1 WO 1983001160 A1 WO1983001160 A1 WO 1983001160A1 US 8101253 W US8101253 W US 8101253W WO 8301160 A1 WO8301160 A1 WO 8301160A1
Authority
WO
WIPO (PCT)
Prior art keywords
stages
delay
circuit
devices
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1981/001253
Other languages
English (en)
Inventor
Inc. Western Electric Company
James Albert Cooper, Jr.
Robert Harold Krambeck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Priority to PCT/US1981/001253 priority Critical patent/WO1983001160A1/fr
Publication of WO1983001160A1 publication Critical patent/WO1983001160A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Definitions

  • This invention relates to integrated circuits and, although not limited thereto, particularly to those used for logic functions.
  • a typical logic circuit comprises a series of logic stages designed to operate in succession in response to various input signals. It is known to use a single clock pulse to activate each of the stages in proper sequence, delay circuits being used to appropriately delay the application of the clock pulse to the successive stages.
  • One problem with certain types of logic networks is that if later stages in the chain of stages are prematurely activated, by the early arrival of the clock pulse, erroneous logic signals can be generated.
  • different supposedly identical logic integrated circuit devices operate at different speeds, whereby delay times which are sufficient for the faster operating circuits are too short for the slower operating circuits.
  • delay circuits have heretofore been designed to provide at least a minimum delay based upon the requirements of the slowest acting device likely to be produced by the manufacturing process.
  • a shortcoming of this arrangement is that the speed of operation of otherwise faster operating devices is thus restricted by the minimum delay time provided by the delay circuits.
  • a semiconductor integrated circuit disposed on a single semiconductor chip, comprises a plurality of successive circuit stages and a corresponding plurality of delay circuits, each of the delay circuits being made up of components substantially identical, and in similar circuit configuration, to those used in each corresponding circuit stage. Because of the substantial similarities between the circuit stages and the associated delay circuits, variations in operating time of the circuit stages caused by processing variations during device manufacture are substantially exactly duplicated in the delay circuits disposed on the same semiconductor chip. Accordingly, the delay times generated by the various delay circuits on each semiconductor chip exactly track and are thus automatically custom selected to match the particular operating speed of the circuit stages on the same chip.
  • FIG. 1 is a circuit diagram of a multistage combinatorial logic arrangement in accordance with this invention
  • FIG. 2 is a circuit diagram of a portion of the arrangement of FIG. 1;
  • FIG. 3 is a pulse diagram for the circuit of FIG. 1;
  • FIG. 4 is a diagram of an alternative organization in accordance with this invention. Detailed Description
  • FIG. 1 shows an illustrative combinatorial logic integrated circuit defined in a semiconductor chip 10.
  • the circuit comprises a plurality of stages Si (viz: S 1 , S 2 , ...), each including an N-channel network 12 i and a 2channel active load element 13 i connected electrically in series between the drain of an N-channel device 15 i and a source of voltage V DD .
  • the network and load elements are designated 12 I and 13 I , respectively, for stage S I .
  • the source of each device 15 i is connected to ground and the gate is connected to a source of clock pulses 16.
  • Network 12 i is connected to the drain of device 15 i and is electrically in series with active load 13 i .
  • Load 13 2 like load 13 i , has its source connected to voltage source V DD .
  • the gates of load 13 1 and 13 2 are connected to the gates of devices 151 and 15 2 , respectively. In this manner, the edge of a single clock pulse from source 16 switches elements 13 1 and 13 2 in opposition to devices 15 1 and 15 2 .
  • FIG. 2 shows a portion of FIG. 1 illustrating the details of either of N-channel networks, 12 1 or 12 2 .
  • Each such network includes paths 42 i and 43 i arranged electrically in parallel between the drain of load device 13 1 (or 13 2 ) and the drain of device 15 1 (or 15 2 ).
  • Path 42 i includes two N-channel devices 47 i and 48 i , the source of the former being connected to the drain of the latter.
  • path 43 i includes devices 50 i and 51 i . Inputs are shown connected to the gate of each of the devices 47 i , 48 i , 50 i , and 51 i .
  • FIG. 1 also shows a delay circuit 20 connected between the gates of devices 15 1 and 15 2 .
  • Delay circuit 20 is incorporated on the chip 10 with the logic network and is manufactured simultaneously therewith.
  • the delay circuit 20 (one being disposed, in this embodiment of the invention, between each successive pair of network stages, S) is made up of components substantially identical, and in similar arrangement, to those used in each network stage, whereby substantially identical variations in operating characteristics are produced in both the delay circuits and the network stages associated therewith in response to the processing variations encountered during manufacture.
  • the delay circuit includes a sequence of N-channel devices 61 i , 62 i , 63 i , and 64 ⁇ , shown is 61 1 , 62 1 , 63 1 , and 64 1 for stage S 1 in
  • FIG. 1 The devices are connected electrically in series source to drain as shown with their gates connected electrically in parallel to the source of voltage V DD .
  • the sequence of devices 61 1 -64 1 is connected between the drains of N-channel device 13 D and N-channel device 15 D forming the equivalent of a stage in FIG. 1.
  • devices 13 D and 15 D are comparable to devices 13 1 and 15 1 of stage S 1 , and operate in an analogous manner.
  • the delay circuit 20 is inherently slower in operation than the otherwise comparable stages.
  • the node between device 61 1 and device 13 D is connected to the gate of device 15 2 via an inverter 70 1 .
  • Inverter 70 1 comprises a P-channel device 71 1 and an Nchannel device 72 1 , the drain of the latter being connected to the drain of the former.
  • the source of device 71 1 is connected to source of voltage V DD .
  • the source of device 72 1 is connected to a reference voltage, conveniently ground.
  • the gates of device 71 1 and 72 1 are connected to a node between devices 61 1 and 13 D .
  • the drains of devices 71 1 and 72 1 are connected to the gate of device 15 2 .
  • Input signals are applied to the inputs of the devices of the N-channel networks, some typically from external sources (not shown); others from prior stages, as is clear from the figure, during ordinary operation.
  • Device 15 1 is turned on at a time when the input signals are fixed and the devices of the N-channel networks are activated or not depending on the input signals. Either an electrical path to ground exists through the N-channel network 12 1 of stage S 1 or not. If not, node 90 remains high, and device 47 2 remains on. If device 48 2 is on at this time as a result of other inputs, node 93 of stage S 2 goes low. Conversely, if a path to ground exists in stage 1, node 90 goes low, device 47 2 turns off, and, for the aforestated logic condition, node 93 of stage S 2 stays high.
  • stage S 1 A finite response time for operation of stage S 1 is required after the clock signal reaches it before node 90 is able to go low. Therefore, it is necessary that an appropriate delay in the activation of stage S 2 be introduced to avoid premature (and possibly erroneous) discharge at state S 2 . This is accomplished by the delay circuit 20 which delays activation of stage S 2 (by control of the turning on of device 152) by the clock signal for a time sufficient for the completion of operation of stage s 1 .
  • Time TIF represents the response time (at mode 90 of FIG. 1) of stage 1 after receipt of a clock pulse from source signal 16.
  • Time T3F represents the response time (at mode 93 of FIG. 1) of stage S 2 after receipt of a clock signal from source 16, the signal being delayed, by delay circuit 20, by time T2F.
  • the delay element 20 is implemented on-chip and so designed, in comparison with the various network stages, so that its delay, T2F, tracks the response time, TIF, under variations in processing.
  • T2F delay
  • T2S delay in the slow chip
  • the ability of the delay 20 to track the operating speed of the network stages with which it is associated clearly reduces the overall response time of the fast chip compared to the time required if a fixed delay (set to tolerate the slowest chip in the distribution) were used.
  • the same on-chip delay circuit can be shared by several first stages operating in parallel as, for example, in the arithmetic logic unit of an 8-bit microprocessor, where eight first-stage units operate in parallel.
  • This organization is illustrated in FIG. 4 where a delay circuit 20 D is shown connected in parallel with circuits S 1A , S 1B , sic. and S 2A , S 2B' S 2C et cetera, each comprising a single stage as S i of FIG. 1.
  • the invention can be implemented with PMOS , NMOS, CNOS, bipolar or any other integrated circuit technology.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Pulse Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Dans un circuit intégré à semiconducteurs du type comportant plusieurs étages de réseaux (SN) conçus pour fonctionner suivant une relation synchronisée présélectionnés les uns par rapport aux autres, les moyens de synchronisation comprennent plusieurs circuits de temporisation (20) fabriqués directement sur la puce à semiconducteurs et comprenant des composants (p.ex. des transistors (61-64)) sensiblement identiques aux composants (p.ex. des transistors (47-48, 50-51)) des étages, et ayant une configuration de conception semblable. Il en résulte que les effets sur les caractéristiques des étages des réseaux dus aux variations de fabrication sont sensiblement reproduits dans les circuits de temporisation, permettant ainsi de régler et corriger automatiquement la vitesse de fonctionnement de chaque dispositif de circuit en fonction de ces variations.
PCT/US1981/001253 1981-09-17 1981-09-17 Agencement de circuits semiconducteurs a multietages Ceased WO1983001160A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US1981/001253 WO1983001160A1 (fr) 1981-09-17 1981-09-17 Agencement de circuits semiconducteurs a multietages

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1981/001253 WO1983001160A1 (fr) 1981-09-17 1981-09-17 Agencement de circuits semiconducteurs a multietages

Publications (1)

Publication Number Publication Date
WO1983001160A1 true WO1983001160A1 (fr) 1983-03-31

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1981/001253 Ceased WO1983001160A1 (fr) 1981-09-17 1981-09-17 Agencement de circuits semiconducteurs a multietages

Country Status (1)

Country Link
WO (1) WO1983001160A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0174397A3 (fr) * 1983-08-05 1986-09-24 Texas Instruments Incorporated Circuit logique comprenant une seule horloge pour logique à niveaux multiples, commandé par une charge fictive

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3567968A (en) * 1967-02-27 1971-03-02 North American Rockwell Gating system for reducing the effects of positive feedback noise in multiphase gating devices
UST926003I4 (en) * 1972-08-25 1974-09-03 Polyphase logical circuit employing complementary misfet
US3852625A (en) * 1972-04-03 1974-12-03 Hitachi Ltd Semiconductor circuit
US3927334A (en) * 1974-04-11 1975-12-16 Electronic Arrays MOSFET bistrap buffer
US3943377A (en) * 1972-05-16 1976-03-09 Tokyo Shibaura Electric Co., Ltd. Logic circuit arrangement employing insulated gate field effect transistors
US3986046A (en) * 1972-07-24 1976-10-12 General Instrument Corporation Dual two-phase clock system
US4040015A (en) * 1974-04-16 1977-08-02 Hitachi, Ltd. Complementary mos logic circuit
US4069429A (en) * 1976-09-13 1978-01-17 Harris Corporation IGFET clock generator
US4140927A (en) * 1977-04-04 1979-02-20 Teletype Corporation Non-overlapping clock generator

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3567968A (en) * 1967-02-27 1971-03-02 North American Rockwell Gating system for reducing the effects of positive feedback noise in multiphase gating devices
US3852625A (en) * 1972-04-03 1974-12-03 Hitachi Ltd Semiconductor circuit
US3943377A (en) * 1972-05-16 1976-03-09 Tokyo Shibaura Electric Co., Ltd. Logic circuit arrangement employing insulated gate field effect transistors
US3986046A (en) * 1972-07-24 1976-10-12 General Instrument Corporation Dual two-phase clock system
UST926003I4 (en) * 1972-08-25 1974-09-03 Polyphase logical circuit employing complementary misfet
US3927334A (en) * 1974-04-11 1975-12-16 Electronic Arrays MOSFET bistrap buffer
US4040015A (en) * 1974-04-16 1977-08-02 Hitachi, Ltd. Complementary mos logic circuit
US4069429A (en) * 1976-09-13 1978-01-17 Harris Corporation IGFET clock generator
US4140927A (en) * 1977-04-04 1979-02-20 Teletype Corporation Non-overlapping clock generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0174397A3 (fr) * 1983-08-05 1986-09-24 Texas Instruments Incorporated Circuit logique comprenant une seule horloge pour logique à niveaux multiples, commandé par une charge fictive

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