WO1983001160A1

WO1983001160A1 - Multistage semiconductor circuit arrangement

Info

Publication number: WO1983001160A1
Application number: PCT/US1981/001253
Authority: WO
Inventors: Inc. Western Electric Company; James Albert Cooper, Jr.; Robert Harold Krambeck
Original assignee: Western Electric Co Inc
Current assignee: AT&T Corp
Priority date: 1981-09-17
Filing date: 1981-09-17
Publication date: 1983-03-31
Anticipated expiration: 1984-03-17

Abstract

Dans un circuit intégré à semiconducteurs du type comportant plusieurs étages de réseaux (SN) conçus pour fonctionner suivant une relation synchronisée présélectionnés les uns par rapport aux autres, les moyens de synchronisation comprennent plusieurs circuits de temporisation (20) fabriqués directement sur la puce à semiconducteurs et comprenant des composants (p.ex. des transistors (61-64)) sensiblement identiques aux composants (p.ex. des transistors (47-48, 50-51)) des étages, et ayant une configuration de conception semblable. Il en résulte que les effets sur les caractéristiques des étages des réseaux dus aux variations de fabrication sont sensiblement reproduits dans les circuits de temporisation, permettant ainsi de régler et corriger automatiquement la vitesse de fonctionnement de chaque dispositif de circuit en fonction de ces variations.In a semiconductor integrated circuit of the type comprising several stages of networks (SN) designed to operate according to a synchronized relation preselected with respect to each other, the synchronization means comprise several timing circuits (20) manufactured directly on the semiconductor chip and comprising components (eg transistors (61-64)) substantially identical to the components (eg transistors (47-48, 50-51)) of the stages, and having a configuration of similar design. As a result, the effects on the characteristics of the stages of the networks due to manufacturing variations are substantially reproduced in the timing circuits, thus making it possible to automatically adjust and correct the operating speed of each circuit device as a function of these variations.

Description

MULTISTAGE SEMICONDUCTOR CIRCUIT ARRANGEMENT

Technical Field

This invention relates to integrated circuits and, although not limited thereto, particularly to those used for logic functions. Background of the Invention

A typical logic circuit comprises a series of logic stages designed to operate in succession in response to various input signals. It is known to use a single clock pulse to activate each of the stages in proper sequence, delay circuits being used to appropriately delay the application of the clock pulse to the successive stages. One problem with certain types of logic networks is that if later stages in the chain of stages are prematurely activated, by the early arrival of the clock pulse, erroneous logic signals can be generated. Moreover, owing to manufacturing processing variations, different supposedly identical logic integrated circuit devices operate at different speeds, whereby delay times which are sufficient for the faster operating circuits are too short for the slower operating circuits.

Thus, to avoid premature activation of the various network stages, while accommodating variations in the speed of operation between different devices, delay circuits have heretofore been designed to provide at least a minimum delay based upon the requirements of the slowest acting device likely to be produced by the manufacturing process. A shortcoming of this arrangement, however, is that the speed of operation of otherwise faster operating devices is thus restricted by the minimum delay time provided by the delay circuits.

Both the recognition of this shortcoming and the solution thereof are the basis of the following described invention. Summary of the Invention

A semiconductor integrated circuit, disposed on a single semiconductor chip, comprises a plurality of successive circuit stages and a corresponding plurality of delay circuits, each of the delay circuits being made up of components substantially identical, and in similar circuit configuration, to those used in each corresponding circuit stage. Because of the substantial similarities between the circuit stages and the associated delay circuits, variations in operating time of the circuit stages caused by processing variations during device manufacture are substantially exactly duplicated in the delay circuits disposed on the same semiconductor chip. Accordingly, the delay times generated by the various delay circuits on each semiconductor chip exactly track and are thus automatically custom selected to match the particular operating speed of the circuit stages on the same chip. Brief Description of the Drawing

FIG. 1 is a circuit diagram of a multistage combinatorial logic arrangement in accordance with this invention;

FIG. 2 is a circuit diagram of a portion of the arrangement of FIG. 1;

FIG. 3 is a pulse diagram for the circuit of FIG. 1; and

FIG. 4 is a diagram of an alternative organization in accordance with this invention. Detailed Description

FIG. 1 shows an illustrative combinatorial logic integrated circuit defined in a semiconductor chip 10. The circuit comprises a plurality of stages Si (viz: S₁, S₂, ...), each including an N-channel network 12_i and a 2channel active load element 13_i connected electrically in series between the drain of an N-channel device 15_i and a source of voltage V_DD. The network and load elements are designated 12_I and 13_I, respectively, for stage S _I . The source of each device 15_i is connected to ground and the gate is connected to a source of clock pulses 16. Network 12_i is connected to the drain of device 15_i and is electrically in series with active load 13_i. Load 13₂, like load 13_i, has its source connected to voltage source V_DD.

The gates of load 13₁ and 13₂ are connected to the gates of devices 151 and 15₂, respectively. In this manner, the edge of a single clock pulse from source 16 switches elements 13₁ and 13₂ in opposition to devices 15₁ and 15₂.

FIG. 2 shows a portion of FIG. 1 illustrating the details of either of N-channel networks, 12₁ or 12₂. Each such network includes paths 42_i and 43_i arranged electrically in parallel between the drain of load device 13₁ (or 13₂) and the drain of device 15₁ (or 15₂). Path 42_i includes two N-channel devices 47_i and 48_i, the source of the former being connected to the drain of the latter. Similarly path 43_i includes devices 50_i and 51_i. Inputs are shown connected to the gate of each of the devices 47_i, 48_i, 50_i, and 51_i.

FIG. 1 also shows a delay circuit 20 connected between the gates of devices 15₁ and 15₂. Delay circuit 20 is incorporated on the chip 10 with the logic network and is manufactured simultaneously therewith. The delay circuit 20 (one being disposed, in this embodiment of the invention, between each successive pair of network stages, S) is made up of components substantially identical, and in similar arrangement, to those used in each network stage, whereby substantially identical variations in operating characteristics are produced in both the delay circuits and the network stages associated therewith in response to the processing variations encountered during manufacture. Thus, in the illustrated embodiment, the delay circuit includes a sequence of N-channel devices 61_i, 62_i, 63_i, and 64^, shown is 61₁, 62₁, 63₁, and 64₁ for stage S ₁ in

FIG. 1. The devices are connected electrically in series source to drain as shown with their gates connected electrically in parallel to the source of voltage V_DD. The sequence of devices 61₁-64₁ is connected between the drains of N-channel device 13_D and N-channel device 15_D forming the equivalent of a stage in FIG. 1. In this connection, devices 13_D and 15_D are comparable to devices 13₁ and 15₁ of stage S₁, and operate in an analogous manner. However, owing to the greater number of series connected N-channel devices 61-64 in comparison with the series connected Nchannel devices 47-48 or 50-51 of the network stages, the delay circuit 20 is inherently slower in operation than the otherwise comparable stages.

The node between device 61₁ and device 13_D is connected to the gate of device 15₂ via an inverter 70₁. Inverter 70₁ comprises a P-channel device 71₁ and an Nchannel device 72₁, the drain of the latter being connected to the drain of the former. The source of device 71₁ is connected to source of voltage V_DD. The source of device 72₁ is connected to a reference voltage, conveniently ground. The gates of device 71₁ and 72₁ are connected to a node between devices 61₁ and 13_D. The drains of devices 71₁ and 72₁ are connected to the gate of device 15₂.

A portion of the operation of the circuit of FIGS. 1 and 2 is now described. An initial condition is assumed where device 15₁ is off, and devices 13₁ and 13₂ are on in the illustrative circuit. Under these conditions, no current flows through the networks, and nodes 90 and 93 (of FIG. 1) are high. If node 90 is in the high state, device 47₂ of the following stage is on.

Input signals are applied to the inputs of the devices of the N-channel networks, some typically from external sources (not shown); others from prior stages, as is clear from the figure, during ordinary operation. Device 15₁ is turned on at a time when the input signals are fixed and the devices of the N-channel networks are activated or not depending on the input signals. Either an electrical path to ground exists through the N-channel network 12₁ of stage S₁ or not. If not, node 90 remains high, and device 47₂ remains on. If device 48₂ is on at this time as a result of other inputs, node 93 of stage S₂ goes low. Conversely, if a path to ground exists in stage 1, node 90 goes low, device 47₂ turns off, and, for the aforestated logic condition, node 93 of stage S₂ stays high.

A finite response time for operation of stage S₁ is required after the clock signal reaches it before node 90 is able to go low. Therefore, it is necessary that an appropriate delay in the activation of stage S₂ be introduced to avoid premature (and possibly erroneous) discharge at state S₂. This is accomplished by the delay circuit 20 which delays activation of stage S₂ (by control of the turning on of device 152) by the clock signal for a time sufficient for the completion of operation of stage s₁.

The effect of the invention is illustrated in

FIG. 3 for two integrated circuit chips from the slow and fast extremes of a manufacturing distribution of integrated circuit chips. Time TIF represents the response time (at mode 90 of FIG. 1) of stage 1 after receipt of a clock pulse from source signal 16. Time T3F represents the response time (at mode 93 of FIG. 1) of stage S₂ after receipt of a clock signal from source 16, the signal being delayed, by delay circuit 20, by time T2F.

As previously described, the delay element 20 is implemented on-chip and so designed, in comparison with the various network stages, so that its delay, T2F, tracks the response time, TIF, under variations in processing. Note, for example, that the delay, T2F, in a fast chip (top of FIG. 3) is significantly less than the delay T2S in the slow chip (bottom of FIG. 3). The ability of the delay 20 to track the operating speed of the network stages with which it is associated clearly reduces the overall response time of the fast chip compared to the time required if a fixed delay (set to tolerate the slowest chip in the distribution) were used. The same on-chip delay circuit can be shared by several first stages operating in parallel as, for example, in the arithmetic logic unit of an 8-bit microprocessor, where eight first-stage units operate in parallel. This organization is illustrated in FIG. 4 where a delay circuit 20_D is shown connected in parallel with circuits S_1A, S_1B, sic. and S_2A, S_2B' S_2C et cetera, each comprising a single stage as S _i of FIG. 1.

The invention can be implemented with PMOS , NMOS, CNOS, bipolar or any other integrated circuit technology.

Claims

Claim

1. A multistage semiconductor integrated circuit comprising a number of network stages (S_N) designed to operate in a preselected sequentially timed relationship in response to the triggering of the successive stages by a clock pulse appropriately delayed between successive stages,

CHARACTERIZED IN THAT the delay means (20) is integrated directly on the semiconductor chip with the stages and comprises components (61-64) substantially identical to the components (47-48, 50-51) of the stages, and in similar design configuration, but operating more slowly than said stages.