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US9779017B2 - Data storage device and data accessing method thereof - Google Patents

Data storage device and data accessing method thereof Download PDF

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Publication number
US9779017B2
US9779017B2 US15/073,062 US201615073062A US9779017B2 US 9779017 B2 US9779017 B2 US 9779017B2 US 201615073062 A US201615073062 A US 201615073062A US 9779017 B2 US9779017 B2 US 9779017B2
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Prior art keywords
column
data
bad
columns
data set
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US15/073,062
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US20160283367A1 (en
Inventor
Chi-Lung Wang
Chia-Ta Huang
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Silicon Motion Inc
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Silicon Motion Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements

Definitions

  • the present invention relates to a data-storage device, and in particular to a data-storage device capable of skipping bad column according to bad column data sets.
  • Flash memory is a type of non-volatile memory which can be electronically erased or re-written. It is mainly used in memory cards, USB flash devices, eMMC and solid-state disks, for the transportation of information between computer devices and digital products.
  • the flash memory includes a plurality of blocks, and each of the blocks has a plurality of pages arranged to store data.
  • the minimum erase unit of flash memory is a block, and the minimum write unit of flash memory is a page. Certain columns of the flash memory may be inaccessible due to particles or mask defects in manufacturing. These are referred to as bad columns.
  • the present invention provides a data storage device.
  • the data storage device includes a flash memory and a controller.
  • the flash memory includes a plurality of dies, and each of the dies has a plurality of columns, wherein each of the columns is constituted by a plurality of sectors.
  • the controller performs a read operation or a write operation from a first column to an Nth column in response to a read command or a write command, and skips at least two columns within the range of the first column to the Nth column according to a first bad column data set during the read operation and the write operation, wherein the first bad column data set has first data and second data, the first data is a starting address, and the second is the number of columns.
  • the present invention provides another data storage device.
  • the data storage device includes a flash memory and a controller.
  • the flash memory includes a plurality of dies, and each of the dies has a plurality of columns constituted by a plurality of sectors.
  • the bad column table includes a plurality of bad column data sets arranged to record at least one of the columns which is unable to use, wherein the bad column data set has at least one first bad column data set, the first bad column data set has first data and second data, the first data is a starting address, and the second data is the number of columns.
  • the present invention further provides data accessing method applied to a data storage device.
  • the flash memory includes a plurality of dies, and each of the dies has a plurality of columns constituted by a plurality of sectors.
  • the data accessing method comprises: receiving a read command indicating to read from a first column to an Nth column or a write command indicating to write data from the first column to the Nth column; reading at least one first bad column data set corresponding to the die which is going to be accessed from a bad column table; and performing a read operation from the first column to the Nth column in response to the read command or performing a write operation from the first column to the Nth column in response to the write command, and skipping at least two columns within the range of the first column to the Nth column according to the obtained first bad column data set during the read operation and the write operation, wherein the first bad column data set comprises first data and second data, the first data is a starting address, and the second data is the number of columns.
  • FIG. 1 is a schematic diagram illustrating an embodiment of an electronic system of the present invention.
  • FIG. 2 is a flowchart of a data accessing method according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram illustrating an embodiment of an electronic system of the present invention.
  • the electronic system 100 includes a host device 120 and a data storage device 140 .
  • the data storage device 140 includes a flash memory 180 and a controller 160 , and capable of operating in response to the commands of the host device 110 .
  • the controller 160 includes a computing unit 162 , a non-volatile memory 164 (ROM) and a random access memory 166 (RAM).
  • the non-volatile memory 164 , the program code stored in the non-volatile memory 164 and data stored in the non-volatile memory 164 constitute firmware executed by the processing unit 162 , and the controller 160 is configured to control the flash memory 180 based on the firmware.
  • the random access memory 166 is arranged to load the program codes and parameters to provide the program codes and parameters to the controller 160 .
  • the flash memory 180 includes a plurality of dies, each of the dies includes a plurality of columns and a plurality of rows, and each of the columns and rows is constituted by a plurality of sectors, wherein the sectors of the flash memory 180 are further grouped into a plurality of pages of a plurality of blocks.
  • a sector arranged to store user data and a sector arranged to store ECC parity can constitute a chunk, wherein the chunk is the minimum unit of the ECC correction, but it is not limited thereto.
  • the chunk can be constituted by two sectors arranged to store user data and two sectors arranged to store the ECC parity.
  • the certain columns of the flash memory may be inaccessible due to particles or mask defects in the manufacturing process, referred to as bad columns.
  • the controller 160 perform a read operation from a first column to an Nth column in response to a read command or perform write operation from the first column to the Nth column in response to a write command, and skips at least two columns of the first column to the Nth column according to a first bad column data set during the read operation and write operation.
  • the first bad column data set includes first data and second data
  • the first data is a starting address
  • the second data is the number of columns. Therefore, the controller 160 can locate an address according to the first data which is a starting address, and determine how many numbers of columns are going to be skipped according to the second data which is the number of columns, but it is not limited thereto.
  • the controller 160 can skip 50 continuous columns from the located column according to the first data and the second data, wherein the first data and the second data of the first bad column data set only requires two chunks of memory space to be stored.
  • the controller 160 skips one column of the first column to the Nth column according to a second bad column data set during the read operation and the write operation.
  • the second bad column data set includes a third data
  • the third data indicates an address of a column of the flash memory 180 . Therefore, the controller 160 can locate an address according to the third data of the second bad column data set to skip the column on the address, but it is not limited thereto. For example, when 50 bad columns of the flash memory need to be skipped, the controller 160 can skip 50 columns according to the third data of 50 second bad column data sets, wherein each of the third data of the second bad column data sets requires a chunk of memory space. Therefore, in this embodiment, the controller 160 needs to read the data of 50 chunks to skip 50 columns.
  • the flash memory 180 stores a bad column table 182 .
  • the bad column table 182 includes a plurality of die areas to store the bad column data sets of the dies.
  • the bad column data set is arranged to record the bad columns of the flash memory 180 , wherein the bad column data set includes at least one first bad column data set.
  • each of the first bad column data sets includes one first data and one second data, the first data is a starting address, and the second is the number of columns.
  • the bad column data set further includes at least one second bad column data set.
  • each of the second bad column data set includes third data, the third data indicates an address of one of the columns.
  • the controller 160 reads the bad column table 182 to obtain the first bad column data set and/or the second bad column data set before or during the read operation and the write operation.
  • the controller 160 loads the bad column table 182 onto the random access memory 166 from the flash memory 180 when the data storage device 140 is powered on, so that the controller 160 can directly access the bad column table 182 from the random access memory 166 bad column table 182 .
  • the controller 160 determines which die is going to be accessed according to the read command or the write command, and reads the data corresponding to the determined die from the bad column table 182 .
  • the controller 160 determines which die is going to be accessed by the read command or the write command, and reads the bad column data sets corresponding to the determined die from the bad column table 182 .
  • the controller 160 performs a read operation in response to the read command to read data from the first column to the Nth column of the flash memory 180 or a write operation in response to the write command to write data into from the first column to the Nth column of the flash memory 180 , and skips at least one column of the first column to the Nth column according to the bad column data set during the read operation and the write operation, wherein the skipped column is corresponding to the bad column data set.
  • FIG. 2 is a flowchart of a data accessing method according to an embodiment of the present invention.
  • the data accessing method is applied to the data storage device 140 of FIG. 1 .
  • the process starts at step S 200 .
  • step S 200 the controller 160 receives a read command requiring to read data from a first column to an Nth column or a write command requiring to write data from the first column to the Nth column.
  • step S 202 the controller 160 reads at least one first bad column data set and/or at least one second first bad column data set from the bad column table 182 .
  • step S 204 the controller 160 performs a read operation from the first column to the Nth column in response to the read command or performs a write operation from the first column to the Nth column in response to the write command, and skips at least one column within the range of the first column to the Nth column according to the read first bad column data set and/or read second bad column data set. More specifically, the controller 160 determines the die which is going to be accessed by the read command or the write command and reads the bad column data sets corresponding to the determined die from the bad column table 182 .
  • the controller 160 locates an address according to the first data of the first bad column data set, and determines how many numbers of columns are going to be skipped according to the second data of the first bad column data set, but it is not limited thereto.
  • the controller 160 locates an address according to the third data of the second bad column data set to skip the column on the address, but it is not limited thereto.
  • the process ends at step S 204 .
  • the data storage device 140 and the data accessing method can skip the bad columns of the flash memory 180 according to the bad column data sets, wherein the first bad column data set can save memory space and reduce the workload of the controller by recording continuously bad columns using only two data units.
  • Data transmission methods may take the form of program code (i.e., executable instructions) embodied in tangible media, such as floppy diskettes, CD-ROMS, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine such as a computer, the machine thereby becomes an apparatus for practicing the methods.
  • the methods may also be embodied in the form of program code transmitted over some transmission medium, such as electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine such as a computer, the machine becomes an apparatus for practicing the disclosed methods.
  • the program code When implemented on a general-purpose processor, the program code combines with the processor to provide a unique apparatus that operates analogously to application-specific logic circuits.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
US15/073,062 2015-03-25 2016-03-17 Data storage device and data accessing method thereof Active US9779017B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
TW104109491 2015-03-25
TW104109491A 2015-03-25
TW104109491A TWI608488B (zh) 2015-03-25 2015-03-25 資料儲存裝置以及資料存取方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11170853B2 (en) * 2020-03-04 2021-11-09 Micron Technology, Inc. Modified write voltage for memory devices

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI605462B (zh) * 2016-05-11 2017-11-11 慧榮科技股份有限公司 資料儲存媒體之損壞資料行的篩選方法
CN108073473A (zh) * 2018-01-12 2018-05-25 江苏华存电子科技有限公司 一种闪存坏列表压缩方法
TWI774015B (zh) * 2020-07-03 2022-08-11 慧榮科技股份有限公司 資料的寫入方法及其資料儲存裝置
CN112083887B (zh) * 2020-09-10 2023-09-15 深圳芯邦科技股份有限公司 一种数据处理方法及相关设备

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US20150179279A1 (en) * 2013-12-23 2015-06-25 Storart Technology Co., Ltd. Method for replacing the address of some bad bytes of the data area and the spare area to good address of bytes in non-volatile storage system

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Publication number Priority date Publication date Assignee Title
US5295255A (en) * 1991-02-22 1994-03-15 Electronic Professional Services, Inc. Method and apparatus for programming a solid state processor with overleaved array memory modules
US20040022249A1 (en) * 1996-02-29 2004-02-05 Kunihiro Katayama Semiconductor memory device having faulty cells
US20020154543A1 (en) * 2000-02-17 2002-10-24 Conley Kevin M. Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US20030221144A1 (en) * 2002-05-22 2003-11-27 Mitsubishi Denki Kabushiki Kaisha Devices for storing and accumulating defect information, semiconductor device and device for testing the same
US20040085821A1 (en) * 2002-10-30 2004-05-06 Broadcom Corporation Self-repairing built-in self test for linked list memories
US20050193233A1 (en) * 2004-02-03 2005-09-01 Paul Magliocco Method for testing and programming memory devices and system for same
US20050281089A1 (en) * 2004-06-21 2005-12-22 Hiroshi Sukegawa Memory card and semiconductor device
US20130007544A1 (en) * 2011-07-01 2013-01-03 Avalanche Technology, Inc. Mapping of random defects in a memory device
US20130077419A1 (en) * 2011-09-22 2013-03-28 Kabushiki Kaisha Toshiba Data generation apparatus
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11170853B2 (en) * 2020-03-04 2021-11-09 Micron Technology, Inc. Modified write voltage for memory devices
US11705197B2 (en) 2020-03-04 2023-07-18 Micron Technology, Inc. Modified write voltage for memory devices

Also Published As

Publication number Publication date
CN106155572A (zh) 2016-11-23
US20160283367A1 (en) 2016-09-29
TW201635304A (zh) 2016-10-01
TWI608488B (zh) 2017-12-11
CN106155572B (zh) 2019-04-12

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