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US8125041B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US8125041B2
US8125041B2 US12/711,660 US71166010A US8125041B2 US 8125041 B2 US8125041 B2 US 8125041B2 US 71166010 A US71166010 A US 71166010A US 8125041 B2 US8125041 B2 US 8125041B2
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Prior art keywords
diffusion layer
electrode
semiconductor substrate
hole
top surface
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US12/711,660
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US20100148292A1 (en
Inventor
Masanori Minamio
Kyoko Fujii
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Nuvoton Technology Corp Japan
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Panasonic Corp
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Assigned to PANASONIC CORPORATION reassignment PANASONIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJII, KYOKO, MINAMIO, MASANORI
Publication of US20100148292A1 publication Critical patent/US20100148292A1/en
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Assigned to PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD. reassignment PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PANASONIC CORPORATION
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/804—Containers or encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10W20/0234—
    • H10W20/20—
    • H10W20/2125—
    • H10W70/65—
    • H10W72/242—
    • H10W72/244—
    • H10W72/29—
    • H10W72/922—
    • H10W72/944—
    • H10W74/129—

Definitions

  • the technology disclosed herein relates to semiconductor devices and electronic equipment using the same.
  • Semiconductor devices used in various types of electronic equipment generally have a configuration including: a semiconductor substrate; an impurity diffusion layer formed in an upper portion of the semiconductor substrate near one of its principal planes (top surface); and a through electrode filled in a through hole extending from one principal plane of the semiconductor substrate through the other principal plane thereof (bottom surface).
  • the through electrode having a conductor formed in the through hole, is electrically connected to a connection electrode formed on the top surface of the semiconductor substrate.
  • the through electrode is also electrically connected to an external connection terminal formed on the bottom surface of the semiconductor substrate.
  • An insulating film is formed on the wall of the through hole to cover the side surface of the through electrode (see Japanese Patent Publication No. P2006-41450, for example).
  • the conventional semiconductor devices described above have a problem as follows. In a region of an upper portion of the semiconductor substrate near the through electrode, a leakage current may occur between the second diffusion layer that has a potential difference against the through electrode and the conductor of the through electrode located near the second diffusion layer. As a result, the current carrying efficiency may be degraded.
  • the present inventors independently found the following. In a region of an upper portion of the semiconductor substrate near the through electrode, although the insulating film exists between the second diffusion layer that has a potential difference against the through electrode and the conductor of the through electrode near the second diffusion layer, even a potential difference as small as about 5V, for example, between the conductor and the second diffusion layer will be greatly influential since the distance between the second diffusion layer and the conductor of the through electrode is extremely infinitesimal, possibly causing occurrence of a leakage current.
  • a leakage current between a diffusion layer and a through electrode closely opposed to each other can be reduced, and the current carrying efficiency can be improved.
  • the first semiconductor device of an example of the present invention includes: a semiconductor substrate through which a through hole extending from the top surface through the bottom surface is formed; a through electrode filled in the through hole to extend through the semiconductor substrate; an insulating film formed on the inner wall of the through hole to surround the side surface of the through electrode; a first diffusion layer containing impurities formed in a region of an upper portion of the semiconductor substrate located on a side of the through electrode; a second diffusion layer formed to cover the first diffusion layer, the second diffusion layer containing impurities at a lower concentration and hence being higher in electric resistance than the first diffusion layer; and a connection electrode formed on the top surface of the semiconductor substrate to be connected to the through electrode, wherein a portion of the side surface of the through electrode facing the second diffusion layer is curved toward the inside of the through hole.
  • the distance between the through electrode and the second diffusion layer can be made longer compared with the case when the side surface is not curved.
  • the electric field between the through electrode and the second diffusion layer can be reduced, the withstand voltage increases. Accordingly, flowing of a leakage current between the through electrode and the semiconductor layer can be reduced even if the distance between the through electrode and the second diffusion layer is shortened, or if the insulating film is thinned, due to scaling down.
  • the second semiconductor device of an example of the present invention includes: a semiconductor substrate through which a through hole extending from the top surface through the bottom surface is formed; a through electrode filled in the through hole to extend through the semiconductor substrate; an insulating film formed on the inner wall of the through hole to surround the side surface of the through electrode; a first diffusion layer containing impurities formed in a region of an upper portion of the semiconductor substrate located on a side of the through electrode; a second diffusion layer formed to cover the first diffusion layer, the second diffusion layer containing impurities at a lower concentration and hence being higher in electric resistance than the first diffusion layer; and a connection electrode formed on the top surface of the semiconductor substrate to be connected to the through electrode, wherein a portion of the surface of the second diffusion layer facing the through electrode is curved.
  • the electric field concentration can be reduced compared with the case when the portion is not curved. Hence, occurrence of a tunnel current due to electric field concentration can be reduced. Accordingly, flowing of a leakage current between the through electrode and the semiconductor layer can be reduced even if the distance between the through electrode and the second diffusion layer is shortened, or if the insulating film is thinned, due to scaling down.
  • the distance between the through electrode and the nearby impurity diffusion layer is made long. Hence, occurrence of a leakage current between the semiconductor layer and the through electrode can be reduced, and this can improve the current carrying efficiency.
  • the surface of the impurity diffusion layer facing the through electrode is curved, occurrence of a tunnel current due to electric field concentration can be reduced. Hence, occurrence of a leakage current between the impurity diffusion layer and the through electrode can be reduced, and this can improve the current carrying efficiency and prevent increase in power consumption.
  • FIG. 1 is a perspective view of a solid-state imaging device of an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the solid-state imaging device of the embodiment of the present invention.
  • FIG. 3 is an enlarged cross-sectional view showing a configuration of part A shown in FIG. 2 .
  • FIG. 4 is an enlarged cross-sectional view showing a configuration of part B shown in FIG. 3 .
  • FIG. 5 is an enlarged cross-sectional view showing a configuration of part C shown in FIG. 4 .
  • a solid-state imaging device for electronic equipment such as a digital camera will be described, as an example of a semiconductor device of an embodiment of the present invention, with reference to the accompanying drawings.
  • FIG. 1 is a perspective view of a solid-state imaging device of an embodiment of the present invention
  • FIG. 2 is a cross-sectional view of the solid-state imaging device of this embodiment.
  • the solid-state imaging device of this embodiment includes: a p-type semiconductor substrate 1 made of silicon and the like whose external shape is rectangular in plan; an imaging region formed in a region on one of the principal planes (hereinafter referred to as the top surface) of the semiconductor substrate 1 including the center of the plane, in which a plurality of light-receiving elements (light-receiving portions) are arranged in a matrix; a peripheral circuit 6 formed on the periphery of or outside of the imaging region; microlenses provided for the respective light-receiving elements 2 at positions above the light-receiving elements 2 ; a glass substrate 4 bonded to the top surface of the semiconductor substrate 1 to be placed above the microlenses 3 ; and a bonding agent 5 applied to the region of the semiconductor substrate 1 other than the imaging region for bonding the semiconductor substrate 1 and the glass substrate 4 to each other.
  • the peripheral circuit 6 includes circuits responsible for drive and control of the light-receiving elements 2 .
  • the light-receiving elements 2 that may be photodiodes, for example, and the peripheral circuit 6 constructed of MOS transistors and the like are fabricated by a known semiconductor process.
  • the solid-state imaging device of this embodiment further includes: a plurality of connection electrodes 10 formed on the top surface of the semiconductor substrate 1 at positions surrounding the peripheral circuit 6 as viewed from top; external connection terminals 11 formed on the other principal plane (hereinafter referred to as the bottom surface) of the semiconductor substrate 11 ; ball-shaped external connection electrodes 17 formed below the semiconductor substrate 1 to be connected to the external connection terminals 11 ; through electrodes 7 each filled in a through hole 8 extending through the semiconductor substrate 1 from the bottom surface of the corresponding connection electrode 10 to the top surface of the corresponding external connection terminal 11 , to be connected to the connection electrode 10 and the external connection terminal 11 ; a first insulating film 12 formed on the inner wall of each through hole 8 ; a second insulating film 15 formed on the bottom surface of the semiconductor substrate 1 ; and a third insulating film 16 formed on the bottom surface of the second insulating film 15 to cover the bottom surfaces of the external connection terminals 11 except for predetermined regions.
  • Each through electrode 7 has a roughly cylindrical conductor 9
  • FIG. 3 is an enlarged cross-sectional view showing a configuration of part A in FIG. 2
  • FIG. 4 is an enlarged cross-sectional view showing a configuration of part B in FIG. 3
  • FIG. 5 is an enlarged cross-sectional view showing a configuration of part C in FIG. 4 .
  • the through electrode 7 includes: a conductor 9 made of Cu and the like; a conductor film 14 made of Cu and the like covering the top and side surfaces of the conductor 9 ; and a barrier metal 13 made of Ti covering the top and side surfaces of the conductor film 14 .
  • the barrier metal 13 is provided to reduce or prevent the metal material constituting the conductor 9 from diffusing into the semiconductor substrate 1 .
  • FIG. 3 shows an example of configuration in which an electrostatic-discharge (ESD) protection circuit 18 A on the input circuit side and a control circuit 18 B for driving the light-receiving elements 2 are respectively provided on the left and right of the through electrode 7 (conductor 9 ).
  • the control circuit 18 B is part of the peripheral circuit 6 .
  • the ESD protection circuit 18 A includes: an n-type diffusion layer 20 containing phosphorus and the like at a concentration of about 10 18 cm ⁇ 3 formed in an upper portion of the semiconductor substrate 1 ; a p-type diffusion layer 19 containing boron and the like at a concentration of about 10 20 cm ⁇ 3 formed in an upper portion of the diffusion layer 20 ; and an element isolation insulating film 26 formed on the semiconductor substrate 1 including the diffusion layers 19 and 20 .
  • the element isolation insulating film 26 may be a local oxidation of silicon (LOCOS) film or a shallow trench isolation (STI) film.
  • the diffusion layer 19 is connected to the connection electrode 10 via an interconnect 21 .
  • the diffusion layer 19 is formed by diffusing impurities that are introduced by ion implantation and the like from the top side of the semiconductor substrate 1 .
  • the diffusion layer 19 constitutes part of the circuit that protects circuit elements from static electricity.
  • the ESD protection circuit 18 A including a resistance gives rise to nondestructive discharge (punch-through) instantaneously, dropping the overvoltage to the ground potential thereby to protect the circuit elements.
  • the ESD protection circuit 18 A is placed near the head of a power supply circuit, and directly connected to the connection electrode 10 that is connected to the through electrode 7 as shown in FIG. 3 .
  • control circuit 18 B for driving the light-receiving elements 2 placed on the right of the through electrode 7 as viewed from FIG. 3 is not directly connected to the connection electrode 10 but connected to a circuit downstream of the ESD protection circuit 18 A.
  • the control circuit 18 B includes: a diffusion layer (second diffusion layer) 24 containing impurities of the first conductivity type formed in an upper portion of the semiconductor substrate 1 ; diffusion layers (first diffusion layers) 22 and 23 containing impurities of the second conductivity type formed in an upper portion of the diffusion layer 24 ; a gate electrode formed on the diffusion layer 24 via a gate insulating film at a position between the diffusion layers 22 and 23 as viewed from top; and the element isolation insulating film 26 formed on the semiconductor substrate 1 including the diffusion layers 22 , 23 , and 24 .
  • the diffusion layers 22 and 23 are higher in impurity concentration than the diffusion layer 24 , and hence serve as low-resistance regions.
  • the diffusion layers 22 and 23 are isolated from the other portion of the semiconductor substrate 1 by the diffusion layer 24 .
  • a lower interlayer insulating film 27 and an upper interlayer insulating film 28 are formed on the element isolation insulating film 26 except for regions where interconnects 25 are formed.
  • the diffusion layers 22 and 23 constitute a MOS transistor of the control circuit 18 B together with the gate electrode, and, as is found from FIGS. 3 and 4 , are not directly connected to the nearby connection electrode 10 but connected to a circuit downstream of the ESD protection circuit 18 A as described above. Specifically, as shown in FIG. 4 , no electrical connection is made between the interconnect 25 and the connection electrode 10 , but an insulating surface protection layer 29 is formed therebetween and on the interconnect 25 .
  • the diffusion layer 24 that is in contact with the diffusion layers 22 and 23 and the through electrode 7 are often different in voltage value from each other (although they are in the same voltage value at some operation timing). In such a case, a potential difference will occur between the diffusion layer 24 and the barrier metal 13 of the through electrode 7 .
  • the distance between the diffusion layer 24 and the barrier metal 13 of the through electrode 7 adjacent to each other via the semiconductor substrate 1 is as small as several micrometers, an electric field of 3 ⁇ 10 4 to 5 ⁇ 10 4 V/cm will be applied even with a potential difference of 5 V, for example.
  • the first insulating film 12 is thin, a leakage current may possibly occur via a minute defect and the like of the first insulating film 12 if no measures are taken.
  • a portion of the side surface of the through electrode 7 (side surface of the barrier metal 13 ) that faces the diffusion layer 24 of the control circuit 18 B adjacent to the through electrode 7 is curved, and a portion of the surface of the diffusion layer 24 facing the through electrode 7 is also curved.
  • the portion of the through electrode 7 facing the diffusion layer 24 is curved not only in the direction horizontal to the substrate plane (horizontal direction) with a given curvature but also in the vertical direction with a given curvature as shown in FIG. 4 .
  • a portion of the inner wall of the through hole 8 facing the diffusion layer 24 is curved to suit to the through electrode 7 .
  • the distance between the portion of the through electrode 7 facing the semiconductor layer (diffusion layer 24 ) formed adjacent to the through electrode 7 and the diffusion layer 24 can be made long compared with the conventional configuration.
  • the portion of the side surface of the through electrode 7 facing the diffusion layer 24 is curved, electric field concentration does not easily occur between the portion of the surface of the diffusion layer 24 facing the through electrode 7 and the portion of the side surface of the through electrode 7 (or the barrier metal 13 ) facing the diffusion layer 24 .
  • the occurrence of a leakage current between the diffusion layer 24 and the barrier metal 13 indicates that a leakage current is flowing between the diffusion layers 22 , 23 , and 24 and the structure of the barrier metal 13 , the conductor film 14 , and the conductor 9 via the first insulating film 12 .
  • the solid-state imaging device of this embodiment since the occurrence of a leakage current flowing between the through electrode 7 and the diffusion layer 24 is reduced, degradation in current carrying efficiency and occurrence of operation failure can be reduced or prevented. Hence, the reliability improves compared with the conventional solid-state imaging device.
  • the portions of the surfaces of the diffusion layer 24 and the nearby through electrode 7 (barrier metal 13 ) facing each other are curved as shown in FIGS. 3 to 5 .
  • the portion of the inner wall of the through hole 8 facing the diffusion layer 24 must be curved. In this embodiment, therefore, a mask for opening the bottom of the through hole 8 is formed on the bottom surface of the semiconductor substrate 1 .
  • the semiconductor substrate 1 is subjected to wet etching and dry etching, whereby the opening area of the through hole 8 can be made larger as the position in the through hole 8 is farther from the bottom surface of the semiconductor substrate 1 toward the top surface up to a predetermined position (e.g., a position deeper than the bottom of the diffusion layer 24 ).
  • a predetermined position e.g., a position deeper than the bottom of the diffusion layer 24 .
  • the inner wall of the through hole 8 can be curved in the vertical and horizontal directions.
  • an overhang 30 is formed at a position in the through hole 8 near the bottom surface of the semiconductor substrate 1 as shown in FIG. 5 .
  • the overhang 30 is covered with the first insulating film 12 , the barrier metal 13 , and the conductor film 14 , it is free from a breakage or the like.
  • the curved surface formed for the through hole 8 is also transferred to the first insulating film 12 and the barrier metal 13 that are formed along the inner wall of the through hole 8 in subsequent steps.
  • the diffusion layer 24 conductive impurities are introduced in a predetermined region of an upper portion of the semiconductor substrate 1 by ion implantation and the like in a manner of dividing the implantation into a plurality of times according to the depth direction, and then diffused and activated by thermal treatment.
  • the mask opening size is changed so that the opening is farther from the through hole as the depth is greater.
  • the portion of the surface of the diffusion layer facing the through electrode 7 can be curved.
  • the thickness of the semiconductor substrate 1 in which the semiconductor layer (diffusion layer 24 ) is formed is preferably less than 50 ⁇ m. Particularly, a thickness in the range of 5 ⁇ m to 30 ⁇ m is preferable. The reason is that, if the semiconductor substrate 1 is sufficiently thin, the overhang 30 of the through electrode 7 will be close to the diffusion layer 24 . Occurrence of a leakage current will be sufficiently reduced even if the distance between the through electrode 7 and the diffusion layer 24 is as small as about 10 ⁇ m, for example.
  • the semiconductor layer is not limited to the diffusion layer 24 of the control circuit 18 B, but may be a semiconductor layer in which a diffusion layer formed inside is not electrically connected to the through electrode 10 or the connection electrode 10 directly.
  • a similar configuration to that of the semiconductor layer and the through electrode 7 of the solid-state imaging device of this embodiment may be applied to a semiconductor device other than the solid-state imaging device. In this case, also, a similar effect to that described above can be obtained.
  • the present invention is applicable favorably to solid-state imaging devices used in imaging apparatuses such as cameras and to other semiconductor devices used in various types of electronic equipment.

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  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US12/711,660 2008-11-07 2010-02-24 Semiconductor device Active 2030-04-10 US8125041B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008286893A JP2010114320A (ja) 2008-11-07 2008-11-07 半導体装置
JP2008-286893 2008-11-07
PCT/JP2009/004099 WO2010052816A1 (ja) 2008-11-07 2009-08-25 半導体装置

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US20100148292A1 US20100148292A1 (en) 2010-06-17
US8125041B2 true US8125041B2 (en) 2012-02-28

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JP5455538B2 (ja) * 2008-10-21 2014-03-26 キヤノン株式会社 半導体装置及びその製造方法
JP5197436B2 (ja) * 2009-02-26 2013-05-15 株式会社東芝 センサーチップ及びその製造方法。
JP5684157B2 (ja) * 2012-01-04 2015-03-11 株式会社東芝 半導体装置
KR20150057148A (ko) * 2013-11-18 2015-05-28 삼성전자주식회사 반도체 장치
US20150189204A1 (en) * 2013-12-27 2015-07-02 Optiz, Inc. Semiconductor Device On Cover Substrate And Method Of Making Same
JP6905040B2 (ja) * 2018-08-08 2021-07-21 キヤノン株式会社 半導体デバイスの製造方法
US11804561B2 (en) * 2019-03-20 2023-10-31 Sony Semiconductor Solutions Corporation Light receiving element, method of manufacturing light receiving element, and imaging apparatus

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WO2010052816A1 (ja) 2010-05-14
JP2010114320A (ja) 2010-05-20

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