[go: up one dir, main page]

US5859544A - Dynamic configurable elements for programmable logic devices - Google Patents

Dynamic configurable elements for programmable logic devices Download PDF

Info

Publication number
US5859544A
US5859544A US08/716,789 US71678996A US5859544A US 5859544 A US5859544 A US 5859544A US 71678996 A US71678996 A US 71678996A US 5859544 A US5859544 A US 5859544A
Authority
US
United States
Prior art keywords
programmable logic
dynamic
memory circuit
source memory
logic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/716,789
Inventor
Kevin Alan Norman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Priority to US08/716,789 priority Critical patent/US5859544A/en
Assigned to ALTERA CORPORATION reassignment ALTERA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NORMAN, KEVIN
Assigned to ALTERA CORPORATION, A CORPORATION OF DELAWARE reassignment ALTERA CORPORATION, A CORPORATION OF DELAWARE MERGER (SEE DOCUMENT FOR DETAILS). Assignors: ALTERA CORPORATION, A CORPORATION OF CALIFORNIA
Application granted granted Critical
Publication of US5859544A publication Critical patent/US5859544A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters

Definitions

  • the present invention relates in general to programmable logic devices (PLDs), and in particular to dynamic configurable elements for PLDs.
  • PLDs programmable logic devices
  • Programmable logic devices are circuits that include a large number of logic gates whose logic function and interconnection can be programmed via programmable elements to form a desired logic function. Programmability is achieved using any one of a variety of programmable technologies, such as fusible links, erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM.
  • EPROM erasable programmable read only memory
  • EEPROM electrically erasable programmable read only memory
  • flash EEPROM flash EEPROM.
  • a fuse element is typically a small value resistor as fabricated which is selectively transformed into an open circuit upon programming.
  • EPROM technology uses a transistor that has low turn on voltage upon fabrication, and is selectively transformed into an open circuit by raising the turn on voltage higher than the power supply during programming.
  • EEPROM technology produces a high turn on voltage transistor after bulk erasure, and selectively transforms the transistor into a depletion mode device by electrically reducing the turn on
  • FIG. 1 shows an SRAM cell 100 having an access transistor 102 and a pair of back-to-back connected inverters 104 that acts as a latch.
  • the cell 100 drives the gate terminal of a pass transistor 106 that forms part of the programmable logic gate.
  • the SRAM cell does not retain its contents when power is removed. For this reason an external source of programming (or configuration) data must be provided along with an SRAM based PLD for reconfiguring the PLD in case of a momentary power failure. Once the PLD is reconfigured upon power up, however, the source of configuration data is idle and serves no purpose during the operation of the PLD.
  • the programmable element in the non-volatile technologies tend to be smaller in size which enhance the logic density of a PLD.
  • PLDs using any one of the non-volatile programmable technologies require special fabrication steps which increase the cost of manufacture and reduce the number of qualified sources of manufactured silicon wafer.
  • the SRAM based PLDs on the other hand may be fabricated on, for example, a standard complementary metal-oxide-semiconductor (CMOS) process or a process tuned for CMOS logic and SRAM circuits. The cost of manufactured wafers is thus lower for the SRAM based PLDs with many more qualified sources of manufactured wafers.
  • CMOS complementary metal-oxide-semiconductor
  • the SRAM cell however is considerably larger than its non-volatile counterparts.
  • a typical SRAM cell may be twice as large as an EEPROM cell and ten times the size of an EPROM or flash EEPROM cell.
  • DRAM cells dynamically store the configuration data on leaky storage capacitors
  • the cells require periodic refreshing.
  • a typical DRAM refresh cycle includes the steps of addressing the cells, sensing their contents (i.e. logic high or logic low), and writing the information back in the cells.
  • the circuit must perform a read operation before writing back. This requires additional circuitry, such as sense amplifiers.
  • the operation of the PLD must be synchronized to avoid reading of the cells during refresh. This requires more circuitry and tends to limit the operating speed of the circuit.
  • Wahlstrom offers various embodiments to allow the PLD to rely on the DRAM cell voltage even during a refresh cycle.
  • the various embodiments of the proposed DRAM cell either require larger storage capacitors or additional circuit elements that result in an overall larger programmable cell. There is therefore room for further improvements in the design of smaller and more cost effective programmable elements for PLDs.
  • the present invention provides a smaller and lower cost programmable element for use in programmable logic devices.
  • the programmable element is based on dynamic charge storage which results in very small cell size and retains low cost manufacturability.
  • the present invention provides a method for reusing the initial source of configuration data to periodically refresh the dynamic programmable elements. This eliminates the requirement of performing a read operation and leaves the charge stored in the dynamic programmable cell undisturbed.
  • the present invention offers a method for operating a programmable logic device (PLD) including the steps of: (a) providing a source of configuration data external to the PLD; (b) using a plurality of dynamic programmable elements to store the configuration data on the PLD; (c) providing an interface between the source of configuration data and the PLD; and (d) refreshing the plurality of dynamic programmable elements by periodically rewriting the configuration data from the source into the PLD.
  • PLD programmable logic device
  • the present invention provides a programmable logic system including a source memory circuit for storing configuration data, a programmable logic device (PLD) having a plurality of dynamic programmable elements coupled to a plurality of logic elements, and an interface circuit connecting the source memory circuit to the PLD, wherein, the plurality of dynamic programmable elements in the PLD are refreshed by periodically rewriting the configuration data from the source memory circuit into the PLD via the interface circuit.
  • PLD programmable logic device
  • FIG. 1 is a simplified schematic showing the prior art use of an SRAM cell as configuration bit in a PLD;
  • FIG. 2 shows an exemplary embodiment of a configuration bit for a dynamic PLD according to the present invention
  • FIGS. 3 shows a symbol for the cell of FIG. 2
  • FIG. 4 shows the interconnection for an array of dynamic configuration cells
  • FIG. 5 is a block diagram of a programmable logic system using dynamic storage elements according to the present invention.
  • FIGS. 6A and 6B are exemplary embodiments for the programmable logic system of the present invention using two different types of memories as sources of configuration data;
  • FIG. 7 is an exemplary embodiment for the loading circuitry of the dynamic PLD.
  • the present invention uses the charge stored on the gate oxide capacitor of an MOS pass transistor or the gate oxides of an input to an integrated CMOS logic gate.
  • FIG. 2 there is shown an exemplary embodiment of a dynamic configuration bit using the gate oxide of a pass transistor 200 as the storage capacitor.
  • An access transistor 202 with its drain terminal connected to a data line, gate terminal connected to a select line and source terminal connected to the storage node 204, provides access to the storage node 204 when turned on.
  • pass transistor 200 When programmed to store positive charge equivalent to a logic high, pass transistor 200 is rendered conductive and its source and drain terminals are shorted together. When storing zero charge, transistor 200 is off causing an open circuit between its source and drain terminals.
  • FIG. 3 shows a symbol 300 for the exemplary dynamic configuration bit of FIG. 2 having data, select, source and drain terminals.
  • the dynamic PLD includes a large number of data lines that run in parallel with each other and perpendicular to a large number of select lines.
  • the collection of all of the programmable elements 300 are distributed at the intersection of the grid formed by the data and select lines. Such an array is shown in FIG. 4.
  • the storage capacitors are programmed in parallel when the desired state of a row of configuration bits is placed on the collection of vertical data lines and the particular select line for the given row of configuration bits is pulsed high and then returned low. This is repeated for each select line until all of the configuration storage capacitors have been programmed. Further details of programming and refreshing mechanism will be discussed hereinafter.
  • a dynamic PLD An important aspect of a dynamic PLD is the provision for the refresh mechanism. Referring back to the dynamic configuration cell of FIG. 2, it can be seen that any charge stored on the gate oxide of pass transistor 200 will over time leak and eventually discharge to a level below the recognizable logic threshold levels. The contents of the cell must therefore be refreshed periodically (e.g., every 10 msec.) for proper operation of the device. Instead of the conventional refresh cycle which includes tedious sensing procedures and adds to circuit complexity, the present invention uses the initial source of configuration data to periodically rewrite the same configuration data back into the dynamic programmable elements. The refresh mechanism thus involves nothing more than a repeated loading of the configuration data into the dynamic PLD. This eliminates the requirement of performing a read operation and leaves the charge stored in the dynamic programmable cell undisturbed.
  • FIG. 5 is a block diagram of a programmable logic system 500 using dynamic storage elements according to the present invention.
  • the system 500 includes a dynamic PLD 502 that connects to a configuration data source 504 and a controller 506.
  • External processing elements 508 and 510 process the system inputs and outputs, respectively.
  • the controller 506 monitors the configuration data source 504 continuously, and causes a periodic transfer of configuration data from the source 504 to the dynamic PLD 502. There is no need to sense and read the contents of the dynamic configuration bits inside the dynamic PLD 502 since the same configuration data that was used to originally program the dynamic cells is being used again to write into the cells.
  • FIG. 6A shows one exemplary embodiment of a dynamic PLD using an SRAM as the configuration data source.
  • a general purpose PLD can be used to implement a programmable controller 602 that controls the down loading of data into the SRAM device 604 as well as the programming of the dynamic PLD 600.
  • the programmable controller 602 connects to an external source (e.g., disk) via a microprocessor bus 606, and receives other system signals such as system clock, WE and RD signals for down loading of the configuration data.
  • the programmable controller 602 programs the SRAM 604 via address and data buses 608 and 610.
  • the programmable controller 602 also provides data clock (DCLK) and horizontal and vertical synch. signals SYNCH and SYNCV that control the timing of programming as well as refreshing.
  • DCLK data clock
  • SYNCH and SYNCV that control the timing of programming as well as refreshing.
  • the device and bus sizes are provided as exemplary values for this specific embodiment.
  • FIG. 6B shows another exemplary embodiment of a dynamic PLD using a serial EPROM as the configuration source.
  • both the controller 612 and the PROM 616 are implemented by a single special purpose PLD such as the Altera EPC1064.
  • a counter 618 is prompted by the controller 612 to cause a steady stream of configuration data to be written into the dynamic PLD 600.
  • the controller 612 also supplies the timing data (DCLK, SYNCH, and SYNCV) to the dynamic PLD 600.
  • FIG. 7 shows a portion of the internal circuitry of the dynamic PLD receiving configuration data serially.
  • the loading circuit includes 1024 rows of data registers 700 with each register including eight 128-bit wide shift registers.
  • the configuration data is clocked into the first row of registers 700 and once all 1024 bits (8 ⁇ 128) are loaded, all 1024 bits are shifted into the next row of registers. This process continues until all 1024 rows are loaded with 1 Meg of configuration data.
  • a row decoder 702 selects one of 1024 rows of dynamic configuration cells to be programmed with a selected row of data stored in the selected row of registers.
  • An advantage of the present invention is that it allows the refresh cycle to start at any time during the operation of the dynamic PLD without any adverse effects. This is better understood by considering the signal channel properties of the dynamic cell of FIG. 2. Assume first that a logic low charge is stored on the gate terminal of the pass transistor 200 (i.e., at storage node 204). When there is no change in the voltages at the source/drain terminals of transistor 200, there is no impact on the cell conditions at refresh.
  • a minor, self-correcting overcharge in the negative direction occurs when the voltage at source/drain terminals of the pass transistor 200 move from a logic high level (e.g., 5 v) to a low level (e.g., Vss). This is caused by negative charge being coupled to the gate of transistor 200 through its source and drain overlap capacitances.
  • the voltage at node 204, V(204) may under these conditions drop below the logic low level Vss.
  • Vtn due to body effect
  • the pass transistor 200 stores a high charge at the time of refresh.
  • the source/drain terminals of transistor 200 are tied together by the on channel of the transistor and may both be high or low.
  • the potential V(signal) at source/drain terminals of transistor 200 is low at refresh.
  • V(data) supplies the new potential if it is less than V(select)-Vtn!, and the storage node 204 will discharge to V(data). It would therefore be desirable to set V(data.high)> V(select.high)-Vtn!> V(signal.high)+Vtn! to get optimal results.
  • V(data.low) and V(select.low) should preferably be set to Vss, while V(signal.low) should be preferably greater or equal to Vss.
  • the preferred implementation would also ensure that whenever a select signal V(select) goes high, each high level on a storage node 204 is supplied by a voltage on the data line V(data) that is already charged to a potential greater than V(select.high)-Vtn plus some margin.
  • the present invention provides methods and circuits for refreshing dynamic configuration bits in a dynamic PLD.
  • the present invention makes use of the configuration source to periodically write the configuration data back into the dynamic PLD to refresh the dynamic storage cells. This eliminates the need to perform a sense and read operation for each refresh cycle. Analysis of signal channel properties for the transistors in the dynamic configuration cell of the present invention show that efficient and accurate refresh can be performed without tedious timing requirements.
  • the present invention therefore makes efficient use of the configuration source and provides a lower cost programmable logic device which retains all of the manufacturability, low cost standard wafers and flexibility of SRAM based devices, while gaining the small element size of the EPROM based devices.
  • the charge storage node may be an input to a logic gate. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents.

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)

Abstract

A programmable logic device using dynamic programmable elements to store configuration data is refreshed by periodic writing of configuration data from the source memory into the dynamic programmable elements. The invention takes advantage of smaller sized dynamic programmable elements and eliminates the need to perform tedious read/sense operation for each refresh cycle.

Description

BACKGROUND OF THE INVENTION
The present invention relates in general to programmable logic devices (PLDs), and in particular to dynamic configurable elements for PLDs.
Programmable logic devices are circuits that include a large number of logic gates whose logic function and interconnection can be programmed via programmable elements to form a desired logic function. Programmability is achieved using any one of a variety of programmable technologies, such as fusible links, erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM. A fuse element is typically a small value resistor as fabricated which is selectively transformed into an open circuit upon programming. EPROM technology uses a transistor that has low turn on voltage upon fabrication, and is selectively transformed into an open circuit by raising the turn on voltage higher than the power supply during programming. EEPROM technology produces a high turn on voltage transistor after bulk erasure, and selectively transforms the transistor into a depletion mode device by electrically reducing the turn on voltage to below zero volts.
All of the above-mentioned programmable technologies fall in the non-volatile category. That is, when the power is removed from the circuit momentarily, these programmable elements retain the programmed information. It is therefore only necessary to load the programming information into the part once. For the fuse based PLD, it is impossible to reverse the programming (or patterning) step. For the EPROM based PLD about half an hour of exposure to ultra violet radiation is required to deprogram the device. For the EEPROM and flash EEPROM based PLD, the programmable element may be reset to its initial state using less than a few minutes of electrical stress.
Another type of programmable element used in PLDs is the static random access memory (SRAM) cell. An SRAM cell operates as a bistable latch. FIG. 1 shows an SRAM cell 100 having an access transistor 102 and a pair of back-to-back connected inverters 104 that acts as a latch. The cell 100 drives the gate terminal of a pass transistor 106 that forms part of the programmable logic gate. The SRAM cell does not retain its contents when power is removed. For this reason an external source of programming (or configuration) data must be provided along with an SRAM based PLD for reconfiguring the PLD in case of a momentary power failure. Once the PLD is reconfigured upon power up, however, the source of configuration data is idle and serves no purpose during the operation of the PLD.
There are advantages and disadvantages associated with both the volatile and the non-volatile programmable technologies. The programmable element in the non-volatile technologies tend to be smaller in size which enhance the logic density of a PLD. However, PLDs using any one of the non-volatile programmable technologies require special fabrication steps which increase the cost of manufacture and reduce the number of qualified sources of manufactured silicon wafer. The SRAM based PLDs on the other hand may be fabricated on, for example, a standard complementary metal-oxide-semiconductor (CMOS) process or a process tuned for CMOS logic and SRAM circuits. The cost of manufactured wafers is thus lower for the SRAM based PLDs with many more qualified sources of manufactured wafers. As can be seen by the required circuitry in FIG. 1, the SRAM cell however is considerably larger than its non-volatile counterparts. With today's technologies, a typical SRAM cell may be twice as large as an EEPROM cell and ten times the size of an EPROM or flash EEPROM cell.
An approach for a PLD design that retains the low cost and manufacturability of SRAM based PLDs while reducing the size of the programmable element is offered by Wahlstrom in U.S. Pat. No. 5,317,212. Wahlstrom teaches using a dynamic random access memory (DRAM) cell as the programmable element in a PLD instead of an SRAM cell. The DRAM cell can be fabricated using standard CMOS technology, and typically includes a small storage capacitor coupled to a single small access transistor which results in a much smaller cell.
Because DRAM cells dynamically store the configuration data on leaky storage capacitors, the cells require periodic refreshing. A typical DRAM refresh cycle includes the steps of addressing the cells, sensing their contents (i.e. logic high or logic low), and writing the information back in the cells. Thus, to refresh DRAM cells, the circuit must perform a read operation before writing back. This requires additional circuitry, such as sense amplifiers. Also, because a read operation disturbs the amount of charge stored on the cell capacitor, the operation of the PLD must be synchronized to avoid reading of the cells during refresh. This requires more circuitry and tends to limit the operating speed of the circuit. Wahlstrom offers various embodiments to allow the PLD to rely on the DRAM cell voltage even during a refresh cycle. However, the various embodiments of the proposed DRAM cell either require larger storage capacitors or additional circuit elements that result in an overall larger programmable cell. There is therefore room for further improvements in the design of smaller and more cost effective programmable elements for PLDs.
SUMMARY OF THE INVENTION
The present invention provides a smaller and lower cost programmable element for use in programmable logic devices. The programmable element is based on dynamic charge storage which results in very small cell size and retains low cost manufacturability. Instead of performing a conventional refresh cycle which includes tedious sensing procedures and adds to circuit complexity, the present invention provides a method for reusing the initial source of configuration data to periodically refresh the dynamic programmable elements. This eliminates the requirement of performing a read operation and leaves the charge stored in the dynamic programmable cell undisturbed.
Accordingly, in one embodiment, the present invention offers a method for operating a programmable logic device (PLD) including the steps of: (a) providing a source of configuration data external to the PLD; (b) using a plurality of dynamic programmable elements to store the configuration data on the PLD; (c) providing an interface between the source of configuration data and the PLD; and (d) refreshing the plurality of dynamic programmable elements by periodically rewriting the configuration data from the source into the PLD.
In another embodiment, the present invention provides a programmable logic system including a source memory circuit for storing configuration data, a programmable logic device (PLD) having a plurality of dynamic programmable elements coupled to a plurality of logic elements, and an interface circuit connecting the source memory circuit to the PLD, wherein, the plurality of dynamic programmable elements in the PLD are refreshed by periodically rewriting the configuration data from the source memory circuit into the PLD via the interface circuit.
A better understanding of the nature and advantages of the programmable logic system of the present invention may be had with reference to the drawings and detailed description below.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified schematic showing the prior art use of an SRAM cell as configuration bit in a PLD;
FIG. 2 shows an exemplary embodiment of a configuration bit for a dynamic PLD according to the present invention;
FIGS. 3 shows a symbol for the cell of FIG. 2;
FIG. 4 shows the interconnection for an array of dynamic configuration cells;
FIG. 5 is a block diagram of a programmable logic system using dynamic storage elements according to the present invention;
FIGS. 6A and 6B are exemplary embodiments for the programmable logic system of the present invention using two different types of memories as sources of configuration data; and
FIG. 7 is an exemplary embodiment for the loading circuitry of the dynamic PLD.
DESCRIPTION OF SPECIFIC EMBODIMENTS
In place of non-volatile or SRAM cells that are conventionally used as configuration bits to control each of the programmable elements in a PLD, the present invention uses the charge stored on the gate oxide capacitor of an MOS pass transistor or the gate oxides of an input to an integrated CMOS logic gate. Referring to FIG. 2 there is shown an exemplary embodiment of a dynamic configuration bit using the gate oxide of a pass transistor 200 as the storage capacitor. An access transistor 202 with its drain terminal connected to a data line, gate terminal connected to a select line and source terminal connected to the storage node 204, provides access to the storage node 204 when turned on. When programmed to store positive charge equivalent to a logic high, pass transistor 200 is rendered conductive and its source and drain terminals are shorted together. When storing zero charge, transistor 200 is off causing an open circuit between its source and drain terminals.
FIG. 3 shows a symbol 300 for the exemplary dynamic configuration bit of FIG. 2 having data, select, source and drain terminals. The dynamic PLD includes a large number of data lines that run in parallel with each other and perpendicular to a large number of select lines. The collection of all of the programmable elements 300 are distributed at the intersection of the grid formed by the data and select lines. Such an array is shown in FIG. 4. The storage capacitors are programmed in parallel when the desired state of a row of configuration bits is placed on the collection of vertical data lines and the particular select line for the given row of configuration bits is pulsed high and then returned low. This is repeated for each select line until all of the configuration storage capacitors have been programmed. Further details of programming and refreshing mechanism will be discussed hereinafter.
An important aspect of a dynamic PLD is the provision for the refresh mechanism. Referring back to the dynamic configuration cell of FIG. 2, it can be seen that any charge stored on the gate oxide of pass transistor 200 will over time leak and eventually discharge to a level below the recognizable logic threshold levels. The contents of the cell must therefore be refreshed periodically (e.g., every 10 msec.) for proper operation of the device. Instead of the conventional refresh cycle which includes tedious sensing procedures and adds to circuit complexity, the present invention uses the initial source of configuration data to periodically rewrite the same configuration data back into the dynamic programmable elements. The refresh mechanism thus involves nothing more than a repeated loading of the configuration data into the dynamic PLD. This eliminates the requirement of performing a read operation and leaves the charge stored in the dynamic programmable cell undisturbed.
FIG. 5 is a block diagram of a programmable logic system 500 using dynamic storage elements according to the present invention. The system 500 includes a dynamic PLD 502 that connects to a configuration data source 504 and a controller 506. External processing elements 508 and 510 process the system inputs and outputs, respectively. The controller 506 monitors the configuration data source 504 continuously, and causes a periodic transfer of configuration data from the source 504 to the dynamic PLD 502. There is no need to sense and read the contents of the dynamic configuration bits inside the dynamic PLD 502 since the same configuration data that was used to originally program the dynamic cells is being used again to write into the cells.
FIG. 6A shows one exemplary embodiment of a dynamic PLD using an SRAM as the configuration data source. A general purpose PLD can be used to implement a programmable controller 602 that controls the down loading of data into the SRAM device 604 as well as the programming of the dynamic PLD 600. The programmable controller 602 connects to an external source (e.g., disk) via a microprocessor bus 606, and receives other system signals such as system clock, WE and RD signals for down loading of the configuration data. Using the down loaded configuration data, the programmable controller 602 programs the SRAM 604 via address and data buses 608 and 610. The programmable controller 602 also provides data clock (DCLK) and horizontal and vertical synch. signals SYNCH and SYNCV that control the timing of programming as well as refreshing. The device and bus sizes are provided as exemplary values for this specific embodiment.
FIG. 6B shows another exemplary embodiment of a dynamic PLD using a serial EPROM as the configuration source. In this embodiment, both the controller 612 and the PROM 616 are implemented by a single special purpose PLD such as the Altera EPC1064. Once the PROM 616 is programmed with the configuration data, a counter 618 is prompted by the controller 612 to cause a steady stream of configuration data to be written into the dynamic PLD 600. The controller 612 also supplies the timing data (DCLK, SYNCH, and SYNCV) to the dynamic PLD 600.
One example of the loading (and refreshing) of the configuration data into the dynamic PLD is described hereinafter in connection with FIG. 7. FIG. 7 shows a portion of the internal circuitry of the dynamic PLD receiving configuration data serially. The loading circuit includes 1024 rows of data registers 700 with each register including eight 128-bit wide shift registers. The configuration data is clocked into the first row of registers 700 and once all 1024 bits (8×128) are loaded, all 1024 bits are shifted into the next row of registers. This process continues until all 1024 rows are loaded with 1 Meg of configuration data. A row decoder 702 selects one of 1024 rows of dynamic configuration cells to be programmed with a selected row of data stored in the selected row of registers.
The only critical timing factor with respect to the refresh operation is maintaining an adequate rate of refresh. An advantage of the present invention is that it allows the refresh cycle to start at any time during the operation of the dynamic PLD without any adverse effects. This is better understood by considering the signal channel properties of the dynamic cell of FIG. 2. Assume first that a logic low charge is stored on the gate terminal of the pass transistor 200 (i.e., at storage node 204). When there is no change in the voltages at the source/drain terminals of transistor 200, there is no impact on the cell conditions at refresh. A minor, self-correcting overcharge in the negative direction, however, occurs when the voltage at source/drain terminals of the pass transistor 200 move from a logic high level (e.g., 5 v) to a low level (e.g., Vss). This is caused by negative charge being coupled to the gate of transistor 200 through its source and drain overlap capacitances. The voltage at node 204, V(204), may under these conditions drop below the logic low level Vss. For a reduced value of n-channel transistor threshold voltage Vtn (due to body effect), as soon as node 204 drops below -Vtn, current flows under the select transistor 202 from the data line to the storage node 204. This limits the negative excursion of V(204) to -Vtn. In the reverse situation, when the voltage at source/drain terminals of transistor 200 move from a logic low level to a logic high level, a small amount of positive charge is coupled to the gate (storage node 204) via the source/drain overlap capacitances. However, given a very large capacitive divide with a large pass transistor 200 and a small select transistor 202, only a small fraction of the drain's potential change couples to node 204. As a result, under these conditions node 204 does not rise much, if at all, above its low level. Thus, when a low charge is stored at the gate of pass transistor 200, not much happens but spurts of ground current via the data lines, and the channels stay off regardless of the signal behavior at the source/drain terminals.
Now assume that the pass transistor 200 stores a high charge at the time of refresh. The source/drain terminals of transistor 200 are tied together by the on channel of the transistor and may both be high or low. Suppose first that the potential V(signal) at source/drain terminals of transistor 200 is low at refresh. The voltage at node 204 would then be increased (refreshed) to the smaller of either the voltage on the data line, V(data), or the voltage on the select line V(select) minus the n-channel threshold voltage Vtn of the select transistor 202. That is, V(204)=min V(select)-Vtn, V(data)!. If the potential at node 204 is already (i.e., before refresh) greater than the minimum of the above two potentials, then V(data) supplies the new potential if it is less than V(select)-Vtn!, and the storage node 204 will discharge to V(data). It would therefore be desirable to set V(data.high)> V(select.high)-Vtn!> V(signal.high)+Vtn! to get optimal results.
When the voltage V(signal) at the source/drain terminals of pass transistor 200 transition from low to high level, positive charge is coupled (via overlap capacitors) to the gate terminal of transistor 200 (i.e., storage node 204). The amount of charge coupled (by a relatively high coupling ratio) is given by ΔV=(coupling-ratio)* V(signal.high)-V(signal.low)!. If the refresh cycle starts now, given the above signal setting is observed, the potential V(204) at the gate terminal of the pass transistor 200 will not be decreased. As the source/drain terminals of transistor 200 transition from V(signal.high) to V(signal.low), V(204) fluctuates between V(select.high)-Vtn! and V(select.high)-Vtn+ΔV!.
The above analysis demonstrates that an accurate refresh of the dynamic PLD according to the method of the present invention can be performed at any time during the operation of the PLD. This analysis also suggests that for optimal operation several restrictions should be placed on relative signal levels. For an n-channel implementation of the dynamic cell as in the exemplary embodiment shown in FIG. 2, the following relationships are preferable for optimal operation:
*V(data.high)> V(select.high)-Vtn!>V(signal.high)+Vtn. This ensures that a full V(signal.high) level is passed across the on channel of pass transistor 200.
*V(signal.low)>V(select.low)-Vtn, and
*V(data.low)>V(select.low)-Vtn.
Both of these settings ensure that select transistor 202 remains completely off when unselected.
If Vss is the lowest available potential, V(data.low) and V(select.low) should preferably be set to Vss, while V(signal.low) should be preferably greater or equal to Vss. The preferred implementation would also ensure that whenever a select signal V(select) goes high, each high level on a storage node 204 is supplied by a voltage on the data line V(data) that is already charged to a potential greater than V(select.high)-Vtn plus some margin.
In conclusion, the present invention provides methods and circuits for refreshing dynamic configuration bits in a dynamic PLD. The present invention makes use of the configuration source to periodically write the configuration data back into the dynamic PLD to refresh the dynamic storage cells. This eliminates the need to perform a sense and read operation for each refresh cycle. Analysis of signal channel properties for the transistors in the dynamic configuration cell of the present invention show that efficient and accurate refresh can be performed without tedious timing requirements. The present invention therefore makes efficient use of the configuration source and provides a lower cost programmable logic device which retains all of the manufacturability, low cost standard wafers and flexibility of SRAM based devices, while gaining the small element size of the EPROM based devices. While the above is a complete description of the preferred embodiments of the present invention, it is possible to use various alternatives, modifications and equivalents. For example, instead of a using a pass transistor as the programmable element, the charge storage node may be an input to a logic gate. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents.

Claims (7)

What is claimed is:
1. A dynamic programmable logic system comprising:
a programmable logic device having a plurality of dynamic programmable elements for dynamic storage of configuration data;
a source memory circuit provided in a separate device external to the programmable logic device, said source memory circuit for storing the configuration data; and
a controller coupled to the programmable logic device and the source memory circuit, the controller for controlling an interface between the programmable logic device and the source memory circuit.
wherein, the plurality of dynamic programmable elements inside the programmable logic device are refreshed at a predetermined rate by periodically writing the configuration data from the source memory circuit into the programmable logic device, thereby eliminating a need for sense and read operations is for refresh purposes,
wherein the interface comprises:
a data bus coupled between the source memory circuit and the programmable logic device;
a clock interconnect line coupled between the controller and the programmable logic device; and
a synch interconnect line coupled between the controller and the programmable logic device to facilitate loading of data into the programmable logic device.
2. The dynamic programmable logic system of claim 1 wherein the synch interconnect line comprises a horizontal synch signal and a vertical synch signal for controlling the loading of configuration data into the programmable logic device.
3. The dynamic programmable logic system of claim 1 wherein the programmable logic device further comprises:
a plurality of data registers coupled to the data bus, synch and clock interconnect lines and configured to serially receive configuration data in response to signals on said synch and clock interconnect lines.
4. The dynamic programmable logic system of claim 1 further comprises:
a second data bus coupled between the controller and the source memory circuit;
an address bus coupled between the controller and the source memory circuit; and
a write enable interconnect line coupled between the controller and the source memory circuit.
5. The dynamic programmable logic system of claim 4 further comprising a system interface bus configured to down load configuration data from a data processing unit to the source memory circuit in response to a system clock signal.
6. The dynamic programmable logic system of claim 1 further comprises:
a clock generator coupled to the controller, the clock generator being configured to generate and supply a clock signal to the controller; and
a counter coupled to the source memory circuit, the counter being configured to generate and supply address signals to the source memory circuit.
7. The dynamic programmable logic system of claim 6 wherein the source memory circuit, the controller, the clock generator and the counter are all implemented by another programmable logic device.
US08/716,789 1996-09-05 1996-09-05 Dynamic configurable elements for programmable logic devices Expired - Lifetime US5859544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/716,789 US5859544A (en) 1996-09-05 1996-09-05 Dynamic configurable elements for programmable logic devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/716,789 US5859544A (en) 1996-09-05 1996-09-05 Dynamic configurable elements for programmable logic devices

Publications (1)

Publication Number Publication Date
US5859544A true US5859544A (en) 1999-01-12

Family

ID=24879442

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/716,789 Expired - Lifetime US5859544A (en) 1996-09-05 1996-09-05 Dynamic configurable elements for programmable logic devices

Country Status (1)

Country Link
US (1) US5859544A (en)

Cited By (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5999441A (en) * 1997-02-14 1999-12-07 Advanced Micro Devices, Inc. Random access memory having bit selectable mask for memory writes
US6038627A (en) * 1998-03-16 2000-03-14 Actel Corporation SRAM bus architecture and interconnect to an FPGA
US6049487A (en) * 1998-03-16 2000-04-11 Actel Corporation Embedded static random access memory for field programmable gate array
US6057703A (en) * 1997-08-22 2000-05-02 Holoplex Inc. Reconfigurable programmable logic devices
US6075721A (en) * 1997-12-18 2000-06-13 Advanced Micro Devices, Inc. Random access memory having bit selectable mask for memory writes
US6088795A (en) * 1996-12-27 2000-07-11 Pact Gmbh Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)
US6150837A (en) 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US6198303B1 (en) * 1998-03-25 2001-03-06 Altera Corporation Configuration eprom with programmable logic
US20030046607A1 (en) * 2001-09-03 2003-03-06 Frank May Method for debugging reconfigurable architectures
US20030056085A1 (en) * 1996-12-09 2003-03-20 Entire Interest Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)
US6538468B1 (en) * 2000-07-31 2003-03-25 Cypress Semiconductor Corporation Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD)
US6549035B1 (en) 1998-09-15 2003-04-15 Actel Corporation High density antifuse based partitioned FPGA architecture
US20030135686A1 (en) * 1997-02-11 2003-07-17 Martin Vorbach Internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US20040052130A1 (en) * 1997-02-08 2004-03-18 Martin Vorbach Method of self-synchronization of configurable elements of a programmable unit
US6727726B1 (en) 2002-11-12 2004-04-27 Actel Corporation Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array
US20040083399A1 (en) * 1997-02-08 2004-04-29 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US6750674B1 (en) 2002-10-02 2004-06-15 Actel Corporation Carry chain for use between logic modules in a field programmable gate array
US6765427B1 (en) 2002-08-08 2004-07-20 Actel Corporation Method and apparatus for bootstrapping a programmable antifuse circuit
US6772387B1 (en) 1998-03-16 2004-08-03 Actel Corporation Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture
US6774667B1 (en) 2002-05-09 2004-08-10 Actel Corporation Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays
US20040181726A1 (en) * 1997-12-22 2004-09-16 Martin Vorbach Method and system for alternating between programs for execution by cells of an integrated circuit
US6799240B1 (en) 1998-03-16 2004-09-28 Actel Corporation SRAM bus architecture and interconnect to an FPGA
US6825690B1 (en) 2003-05-28 2004-11-30 Actel Corporation Clock tree network in a field programmable gate array
US20040243984A1 (en) * 2001-06-20 2004-12-02 Martin Vorbach Data processing method
US20040249880A1 (en) * 2001-12-14 2004-12-09 Martin Vorbach Reconfigurable system
US6838902B1 (en) 2003-05-28 2005-01-04 Actel Corporation Synchronous first-in/first-out block memory for a field programmable gate array
US20050053056A1 (en) * 2001-09-03 2005-03-10 Martin Vorbach Router
US6867615B1 (en) 2003-05-30 2005-03-15 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US20050066213A1 (en) * 2001-03-05 2005-03-24 Martin Vorbach Methods and devices for treating and processing data
US20050086649A1 (en) * 2001-08-16 2005-04-21 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US6885218B1 (en) 2002-10-08 2005-04-26 Actel Corporation Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA
US6891394B1 (en) 2002-06-04 2005-05-10 Actel Corporation Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
US6891396B1 (en) 2002-12-27 2005-05-10 Actel Corporation Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
US20050132344A1 (en) * 2002-01-18 2005-06-16 Martin Vorbach Method of compilation
US20050201141A1 (en) * 2004-03-10 2005-09-15 Altera Corporation Dynamic RAM storage techniques
US6946871B1 (en) 2002-12-18 2005-09-20 Actel Corporation Multi-level routing architecture in a field programmable gate array having transmitters and receivers
US20050223212A1 (en) * 2000-06-13 2005-10-06 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US20060001045A1 (en) * 2004-07-01 2006-01-05 Sidhu Lakhbeer S Integrated circuit structures for increasing resistance to single event upset
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US20060031595A1 (en) * 1996-12-27 2006-02-09 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like
US20060075211A1 (en) * 2002-03-21 2006-04-06 Martin Vorbach Method and device for data processing
US20060090062A1 (en) * 2002-01-19 2006-04-27 Martin Vorbach Reconfigurable processor
US20060117234A1 (en) * 2004-11-30 2006-06-01 Fujitsu Limited Programmable logic device, information processing device and programmable logic device control method
US20060192586A1 (en) * 2002-09-06 2006-08-31 Martin Vorbach Reconfigurable sequencer structure
US20060248317A1 (en) * 2002-08-07 2006-11-02 Martin Vorbach Method and device for processing data
US20070011433A1 (en) * 2003-04-04 2007-01-11 Martin Vorbach Method and device for data processing
US7174443B1 (en) 1996-12-20 2007-02-06 Pact Xpp Technologies Ag Run-time reconfiguration method for programmable units
US20070050603A1 (en) * 2002-08-07 2007-03-01 Martin Vorbach Data processing method and device
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US20070113046A1 (en) * 2001-03-05 2007-05-17 Martin Vorbach Data processing device and method
US20070123091A1 (en) * 2005-11-18 2007-05-31 Swedberg Benjamin D Releasable Wire Connector
US20070150637A1 (en) * 2002-02-18 2007-06-28 Martin Vorbach Bus systems and method for reconfiguration
US7378867B1 (en) 2002-06-04 2008-05-27 Actel Corporation Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
US7385419B1 (en) 2003-05-30 2008-06-10 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US7389487B1 (en) 1998-04-28 2008-06-17 Actel Corporation Dedicated interface architecture for a hybrid integrated circuit
US20080222329A1 (en) * 1996-12-20 2008-09-11 Martin Vorbach I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US7434080B1 (en) 2002-09-03 2008-10-07 Actel Corporation Apparatus for interfacing and testing a phase locked loop in a field programmable gate array
US20090031104A1 (en) * 2005-02-07 2009-01-29 Martin Vorbach Low Latency Massive Parallel Data Processing Device
US7539914B1 (en) * 2006-01-17 2009-05-26 Xilinx, Inc. Method of refreshing configuration data in an integrated circuit
US7545168B2 (en) 2003-05-28 2009-06-09 Actel Corporation Clock tree network in a field programmable gate array
US20090146691A1 (en) * 2000-10-06 2009-06-11 Martin Vorbach Logic cell array and bus system
US7549138B2 (en) 2002-10-08 2009-06-16 Actel Corporation Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA
US20090172351A1 (en) * 2003-08-28 2009-07-02 Martin Vorbach Data processing device and method
US20090199167A1 (en) * 2006-01-18 2009-08-06 Martin Vorbach Hardware Definition Method
US20090210653A1 (en) * 2001-03-05 2009-08-20 Pact Xpp Technologies Ag Method and device for treating and processing data
US7579869B2 (en) 2002-12-27 2009-08-25 Actel Corporation Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US7595659B2 (en) 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US20090300262A1 (en) * 2001-03-05 2009-12-03 Martin Vorbach Methods and devices for treating and/or processing data
US20100153654A1 (en) * 2002-08-07 2010-06-17 Martin Vorbach Data processing method and device
US7772881B1 (en) * 2006-09-29 2010-08-10 Altera Corporation Method and apparatus for in-system programmability
US20100228918A1 (en) * 1999-06-10 2010-09-09 Martin Vorbach Configurable logic integrated circuit having a multidimensional structure of configurable elements
US20110060942A1 (en) * 2001-03-05 2011-03-10 Martin Vorbach Methods and devices for treating and/or processing data
US20110145547A1 (en) * 2001-08-10 2011-06-16 Martin Vorbach Reconfigurable elements
US20110238948A1 (en) * 2002-08-07 2011-09-29 Martin Vorbach Method and device for coupling a data processing unit and a data processing array
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
JP2015122738A (en) * 2013-11-22 2015-07-02 株式会社半導体エネルギー研究所 Semiconductor device
US20150263734A1 (en) * 2014-03-13 2015-09-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
US9722615B2 (en) 2014-03-13 2017-08-01 Semiconductor Energy Laboratory Co., Ltd. Method for operating programmable logic device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4546273A (en) * 1983-01-11 1985-10-08 Burroughs Corporation Dynamic re-programmable PLA
US4717912A (en) * 1982-10-07 1988-01-05 Advanced Micro Devices, Inc. Apparatus for producing any one of a plurality of signals at a single output
US5317212A (en) * 1993-03-19 1994-05-31 Wahlstrom Sven E Dynamic control of configurable logic
US5396452A (en) * 1993-07-02 1995-03-07 Wahlstrom; Sven E. Dynamic random access memory
US5423388A (en) * 1994-08-08 1995-06-13 Hale; Robert G. Direction controllable subsurface borehole tool
US5581198A (en) * 1995-02-24 1996-12-03 Xilinx, Inc. Shadow DRAM for programmable logic devices
US5640106A (en) * 1995-05-26 1997-06-17 Xilinx, Inc. Method and structure for loading data into several IC devices
US5640107A (en) * 1995-10-24 1997-06-17 Northrop Grumman Corporation Method for in-circuit programming of a field-programmable gate array configuration memory

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4717912A (en) * 1982-10-07 1988-01-05 Advanced Micro Devices, Inc. Apparatus for producing any one of a plurality of signals at a single output
US4546273A (en) * 1983-01-11 1985-10-08 Burroughs Corporation Dynamic re-programmable PLA
US5317212A (en) * 1993-03-19 1994-05-31 Wahlstrom Sven E Dynamic control of configurable logic
US5396452A (en) * 1993-07-02 1995-03-07 Wahlstrom; Sven E. Dynamic random access memory
US5423388A (en) * 1994-08-08 1995-06-13 Hale; Robert G. Direction controllable subsurface borehole tool
US5581198A (en) * 1995-02-24 1996-12-03 Xilinx, Inc. Shadow DRAM for programmable logic devices
US5640106A (en) * 1995-05-26 1997-06-17 Xilinx, Inc. Method and structure for loading data into several IC devices
US5640107A (en) * 1995-10-24 1997-06-17 Northrop Grumman Corporation Method for in-circuit programming of a field-programmable gate array configuration memory

Cited By (203)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7237087B2 (en) 1996-12-09 2007-06-26 Pact Xpp Technologies Ag Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells
US20030056085A1 (en) * 1996-12-09 2003-03-20 Entire Interest Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)
US20110010523A1 (en) * 1996-12-09 2011-01-13 Martin Vorbach Runtime configurable arithmetic and logic cell
US20040168099A1 (en) * 1996-12-09 2004-08-26 Martin Vorbach Unit for processing numeric and logic operations for use in central processing units (CPUs), multiprocessor systems
US7822968B2 (en) 1996-12-09 2010-10-26 Martin Vorbach Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
US8156312B2 (en) 1996-12-09 2012-04-10 Martin Vorbach Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units
US20080010437A1 (en) * 1996-12-09 2008-01-10 Martin Vorbach Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)
US7565525B2 (en) 1996-12-09 2009-07-21 Pact Xpp Technologies Ag Runtime configurable arithmetic and logic cell
US20090146690A1 (en) * 1996-12-09 2009-06-11 Martin Vorbach Runtime configurable arithmetic and logic cell
US20080222329A1 (en) * 1996-12-20 2008-09-11 Martin Vorbach I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US7174443B1 (en) 1996-12-20 2007-02-06 Pact Xpp Technologies Ag Run-time reconfiguration method for programmable units
US7650448B2 (en) 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US20100082863A1 (en) * 1996-12-20 2010-04-01 Martin Vorbach I/O AND MEMORY BUS SYSTEM FOR DFPs AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
US8195856B2 (en) 1996-12-20 2012-06-05 Martin Vorbach I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7899962B2 (en) 1996-12-20 2011-03-01 Martin Vorbach I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US20100287318A1 (en) * 1996-12-20 2010-11-11 Martin Vorbach I/o and memory bus system for dfps and units with two- or multi-dimensional programmable cell architectures
US20090144485A1 (en) * 1996-12-27 2009-06-04 Martin Vorbach Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
US6088795A (en) * 1996-12-27 2000-07-11 Pact Gmbh Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)
US7028107B2 (en) * 1996-12-27 2006-04-11 Pact Xpp Technologies Ag Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
US20090153188A1 (en) * 1996-12-27 2009-06-18 Martin Vorbach PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE)
US20060031595A1 (en) * 1996-12-27 2006-02-09 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like
US7822881B2 (en) 1996-12-27 2010-10-26 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
US20030093662A1 (en) * 1996-12-27 2003-05-15 Pact Gmbh Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three-dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
US6968452B2 (en) 1997-02-08 2005-11-22 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable unit
US20040083399A1 (en) * 1997-02-08 2004-04-29 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US20040052130A1 (en) * 1997-02-08 2004-03-18 Martin Vorbach Method of self-synchronization of configurable elements of a programmable unit
USRE45223E1 (en) 1997-02-08 2014-10-28 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
US7036036B2 (en) 1997-02-08 2006-04-25 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
USRE45109E1 (en) 1997-02-08 2014-09-02 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
USRE44383E1 (en) 1997-02-08 2013-07-16 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US7010667B2 (en) 1997-02-11 2006-03-07 Pact Xpp Technologies Ag Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US20030135686A1 (en) * 1997-02-11 2003-07-17 Martin Vorbach Internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US5999441A (en) * 1997-02-14 1999-12-07 Advanced Micro Devices, Inc. Random access memory having bit selectable mask for memory writes
US6150837A (en) 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US6057703A (en) * 1997-08-22 2000-05-02 Holoplex Inc. Reconfigurable programmable logic devices
US6075721A (en) * 1997-12-18 2000-06-13 Advanced Micro Devices, Inc. Random access memory having bit selectable mask for memory writes
US20090300445A1 (en) * 1997-12-22 2009-12-03 Martin Vorbach Method and system for alternating between programs for execution by cells of an integrated circuit
US8819505B2 (en) 1997-12-22 2014-08-26 Pact Xpp Technologies Ag Data processor having disabled cores
US20040181726A1 (en) * 1997-12-22 2004-09-16 Martin Vorbach Method and system for alternating between programs for execution by cells of an integrated circuit
US20040199689A1 (en) * 1998-03-16 2004-10-07 Actel Corporation, A California Corporation SRAM bus architecture and interconnect to an FPGA
US6049487A (en) * 1998-03-16 2000-04-11 Actel Corporation Embedded static random access memory for field programmable gate array
US7124347B2 (en) 1998-03-16 2006-10-17 Actel Corporation Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture
US6799240B1 (en) 1998-03-16 2004-09-28 Actel Corporation SRAM bus architecture and interconnect to an FPGA
US7054967B2 (en) 1998-03-16 2006-05-30 Actel Corporation SRAM bus architecture and interconnect to an FPGA
US6038627A (en) * 1998-03-16 2000-03-14 Actel Corporation SRAM bus architecture and interconnect to an FPGA
US20040237021A1 (en) * 1998-03-16 2004-11-25 Actel Corporation, A California Corporation Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture
US6772387B1 (en) 1998-03-16 2004-08-03 Actel Corporation Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture
US6198303B1 (en) * 1998-03-25 2001-03-06 Altera Corporation Configuration eprom with programmable logic
US8990757B2 (en) 1998-04-28 2015-03-24 Microsemi SoC Corporation Dedicated interface architecture for a hybrid integrated circuit
US7389487B1 (en) 1998-04-28 2008-06-17 Actel Corporation Dedicated interface architecture for a hybrid integrated circuit
US20080204074A1 (en) * 1998-04-28 2008-08-28 Actel Corporation Dedicated interface architecture for a hybrid integrated circuit
US6549035B1 (en) 1998-09-15 2003-04-15 Actel Corporation High density antifuse based partitioned FPGA architecture
US8468329B2 (en) 1999-02-25 2013-06-18 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US20100228918A1 (en) * 1999-06-10 2010-09-09 Martin Vorbach Configurable logic integrated circuit having a multidimensional structure of configurable elements
US8726250B2 (en) 1999-06-10 2014-05-13 Pact Xpp Technologies Ag Configurable logic integrated circuit having a multidimensional structure of configurable elements
US8312200B2 (en) 1999-06-10 2012-11-13 Martin Vorbach Processor chip including a plurality of cache elements connected to a plurality of processor cores
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US20110012640A1 (en) * 1999-06-10 2011-01-20 Martin Vorbach Configurable logic integrated circuit having a multidimensional structure of configurable elements
US8301872B2 (en) 2000-06-13 2012-10-30 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US20050223212A1 (en) * 2000-06-13 2005-10-06 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US7003660B2 (en) 2000-06-13 2006-02-21 Pact Xpp Technologies Ag Pipeline configuration unit protocols and communication
US6538468B1 (en) * 2000-07-31 2003-03-25 Cypress Semiconductor Corporation Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD)
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US20090146691A1 (en) * 2000-10-06 2009-06-11 Martin Vorbach Logic cell array and bus system
US9047440B2 (en) 2000-10-06 2015-06-02 Pact Xpp Technologies Ag Logical cell array and bus system
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US8471593B2 (en) 2000-10-06 2013-06-25 Martin Vorbach Logic cell array and bus system
US7595659B2 (en) 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US20070113046A1 (en) * 2001-03-05 2007-05-17 Martin Vorbach Data processing device and method
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US8312301B2 (en) 2001-03-05 2012-11-13 Martin Vorbach Methods and devices for treating and processing data
US20100023796A1 (en) * 2001-03-05 2010-01-28 Martin Vorbach Methods and devices for treating and processing data
US9075605B2 (en) 2001-03-05 2015-07-07 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US20110173389A1 (en) * 2001-03-05 2011-07-14 Martin Vorbach Methods and devices for treating and/or processing data
US20090300262A1 (en) * 2001-03-05 2009-12-03 Martin Vorbach Methods and devices for treating and/or processing data
US20090100286A1 (en) * 2001-03-05 2009-04-16 Martin Vorbach Methods and devices for treating and processing data
US20050066213A1 (en) * 2001-03-05 2005-03-24 Martin Vorbach Methods and devices for treating and processing data
US8145881B2 (en) 2001-03-05 2012-03-27 Martin Vorbach Data processing device and method
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US20090210653A1 (en) * 2001-03-05 2009-08-20 Pact Xpp Technologies Ag Method and device for treating and processing data
US20110060942A1 (en) * 2001-03-05 2011-03-10 Martin Vorbach Methods and devices for treating and/or processing data
US20090144522A1 (en) * 2001-03-05 2009-06-04 Martin Vorbach Data Processing Device and Method
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US8099618B2 (en) 2001-03-05 2012-01-17 Martin Vorbach Methods and devices for treating and processing data
US20040243984A1 (en) * 2001-06-20 2004-12-02 Martin Vorbach Data processing method
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US20100095094A1 (en) * 2001-06-20 2010-04-15 Martin Vorbach Method for processing data
US20110145547A1 (en) * 2001-08-10 2011-06-16 Martin Vorbach Reconfigurable elements
US8869121B2 (en) 2001-08-16 2014-10-21 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US20050086649A1 (en) * 2001-08-16 2005-04-21 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US20090006895A1 (en) * 2001-09-03 2009-01-01 Frank May Method for debugging reconfigurable architectures
US8407525B2 (en) 2001-09-03 2013-03-26 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US20030046607A1 (en) * 2001-09-03 2003-03-06 Frank May Method for debugging reconfigurable architectures
US20060245225A1 (en) * 2001-09-03 2006-11-02 Martin Vorbach Reconfigurable elements
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US7840842B2 (en) 2001-09-03 2010-11-23 Martin Vorbach Method for debugging reconfigurable architectures
US7480825B2 (en) 2001-09-03 2009-01-20 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US20050022062A1 (en) * 2001-09-03 2005-01-27 Martin Vorbach Method for debugging reconfigurable architectures
US20090037865A1 (en) * 2001-09-03 2009-02-05 Martin Vorbach Router
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US8069373B2 (en) 2001-09-03 2011-11-29 Martin Vorbach Method for debugging reconfigurable architectures
US20050053056A1 (en) * 2001-09-03 2005-03-10 Martin Vorbach Router
US8209653B2 (en) 2001-09-03 2012-06-26 Martin Vorbach Router
US8429385B2 (en) 2001-09-03 2013-04-23 Martin Vorbach Device including a field having function cells and information providing cells controlled by the function cells
US20090150725A1 (en) * 2001-09-03 2009-06-11 Martin Vorbach Method for debugging reconfigurable architectures
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US20040249880A1 (en) * 2001-12-14 2004-12-09 Martin Vorbach Reconfigurable system
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
US20050132344A1 (en) * 2002-01-18 2005-06-16 Martin Vorbach Method of compilation
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
US20060090062A1 (en) * 2002-01-19 2006-04-27 Martin Vorbach Reconfigurable processor
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US20070150637A1 (en) * 2002-02-18 2007-06-28 Martin Vorbach Bus systems and method for reconfiguration
US20060075211A1 (en) * 2002-03-21 2006-04-06 Martin Vorbach Method and device for data processing
US20100174868A1 (en) * 2002-03-21 2010-07-08 Martin Vorbach Processor device having a sequential data processing unit and an arrangement of data processing elements
US6774667B1 (en) 2002-05-09 2004-08-10 Actel Corporation Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays
US6891394B1 (en) 2002-06-04 2005-05-10 Actel Corporation Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
US7545166B2 (en) 2002-06-04 2009-06-09 Actel Corporation Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
US7378867B1 (en) 2002-06-04 2008-05-27 Actel Corporation Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
US7119573B2 (en) 2002-06-04 2006-10-10 Actel Corporation Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
US20080197905A1 (en) * 2002-06-04 2008-08-21 Actel Corporation Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
US8281265B2 (en) 2002-08-07 2012-10-02 Martin Vorbach Method and device for processing data
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US20110238948A1 (en) * 2002-08-07 2011-09-29 Martin Vorbach Method and device for coupling a data processing unit and a data processing array
US8156284B2 (en) 2002-08-07 2012-04-10 Martin Vorbach Data processing method and device
US20070050603A1 (en) * 2002-08-07 2007-03-01 Martin Vorbach Data processing method and device
US20100153654A1 (en) * 2002-08-07 2010-06-17 Martin Vorbach Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US20060248317A1 (en) * 2002-08-07 2006-11-02 Martin Vorbach Method and device for processing data
US20100070671A1 (en) * 2002-08-07 2010-03-18 Martin Vorbach Method and device for processing data
US6765427B1 (en) 2002-08-08 2004-07-20 Actel Corporation Method and apparatus for bootstrapping a programmable antifuse circuit
US20090045855A1 (en) * 2002-09-03 2009-02-19 Actel Corporation Apparatus for interfacing and testing a phase locked loop in a field programmable gate array
US7434080B1 (en) 2002-09-03 2008-10-07 Actel Corporation Apparatus for interfacing and testing a phase locked loop in a field programmable gate array
US7774665B2 (en) 2002-09-03 2010-08-10 Actel Corporation Apparatus for testing a phrase-locked loop in a boundary scan enabled device
US20110148460A1 (en) * 2002-09-06 2011-06-23 Martin Vorbach Reconfigurable sequencer structure
US7602214B2 (en) 2002-09-06 2009-10-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US8310274B2 (en) 2002-09-06 2012-11-13 Martin Vorbach Reconfigurable sequencer structure
US7782087B2 (en) 2002-09-06 2010-08-24 Martin Vorbach Reconfigurable sequencer structure
US20060192586A1 (en) * 2002-09-06 2006-08-31 Martin Vorbach Reconfigurable sequencer structure
US20080191737A1 (en) * 2002-09-06 2008-08-14 Martin Vorbach Reconfigurable sequencer structure
US7928763B2 (en) 2002-09-06 2011-04-19 Martin Vorbach Multi-core processing system
US8803552B2 (en) 2002-09-06 2014-08-12 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US20100039139A1 (en) * 2002-09-06 2010-02-18 Martin Vorbach Reconfigurable sequencer structure
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US20110006805A1 (en) * 2002-09-06 2011-01-13 Martin Vorbach Reconfigurable sequencer structure
US6750674B1 (en) 2002-10-02 2004-06-15 Actel Corporation Carry chain for use between logic modules in a field programmable gate array
US7111272B1 (en) 2002-10-08 2006-09-19 Actel Corporation Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA
US6885218B1 (en) 2002-10-08 2005-04-26 Actel Corporation Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA
US7549138B2 (en) 2002-10-08 2009-06-16 Actel Corporation Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA
US6727726B1 (en) 2002-11-12 2004-04-27 Actel Corporation Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array
US7126374B2 (en) 2002-12-18 2006-10-24 Actel Corporation Multi-level routing architecture in a field programmable gate array having transmitters and receivers
US6946871B1 (en) 2002-12-18 2005-09-20 Actel Corporation Multi-level routing architecture in a field programmable gate array having transmitters and receivers
US7579869B2 (en) 2002-12-27 2009-08-25 Actel Corporation Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
US7075334B1 (en) 2002-12-27 2006-07-11 Actel Corporation Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
US6891396B1 (en) 2002-12-27 2005-05-10 Actel Corporation Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
US20070011433A1 (en) * 2003-04-04 2007-01-11 Martin Vorbach Method and device for data processing
US20100122064A1 (en) * 2003-04-04 2010-05-13 Martin Vorbach Method for increasing configuration runtime of time-sliced configurations
US7394289B2 (en) 2003-05-28 2008-07-01 Actel Corporation Synchronous first-in/first-out block memory for a field programmable gate array
US20060082385A1 (en) * 2003-05-28 2006-04-20 Actel Corporation, A California Corporation Synchronous first-in/first-out block memory for a field programmable gate array
US6825690B1 (en) 2003-05-28 2004-11-30 Actel Corporation Clock tree network in a field programmable gate array
US6838902B1 (en) 2003-05-28 2005-01-04 Actel Corporation Synchronous first-in/first-out block memory for a field programmable gate array
US20070182446A1 (en) * 2003-05-28 2007-08-09 Actel Corporation Synchronous first-in/first-out block memory for a field programmable gate array
US7049846B1 (en) 2003-05-28 2006-05-23 Actel Corporation Clock tree network in a field programmable gate array
US7545168B2 (en) 2003-05-28 2009-06-09 Actel Corporation Clock tree network in a field programmable gate array
US7227380B2 (en) 2003-05-28 2007-06-05 Actel Corporation Synchronous first-in/first-out block memory for a field programmable gate array
US6867615B1 (en) 2003-05-30 2005-03-15 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US20060087341A1 (en) * 2003-05-30 2006-04-27 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US20080231319A1 (en) * 2003-05-30 2008-09-25 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US7385419B1 (en) 2003-05-30 2008-06-10 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US6980028B1 (en) 2003-05-30 2005-12-27 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US7102385B2 (en) 2003-05-30 2006-09-05 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US20100241823A1 (en) * 2003-08-28 2010-09-23 Martin Vorbach Data processing device and method
US8812820B2 (en) 2003-08-28 2014-08-19 Pact Xpp Technologies Ag Data processing device and method
US20090172351A1 (en) * 2003-08-28 2009-07-02 Martin Vorbach Data processing device and method
US20050201141A1 (en) * 2004-03-10 2005-09-15 Altera Corporation Dynamic RAM storage techniques
US7277316B2 (en) 2004-03-10 2007-10-02 Altera Corporation Dynamic RAM storage techniques
US20060245238A1 (en) * 2004-03-10 2006-11-02 Altera Corporation Dynamic RAM storage techniques
US7602634B2 (en) 2004-03-10 2009-10-13 Altera Corporation Dynamic RAM storage techniques
US20070285979A1 (en) * 2004-03-10 2007-12-13 Altera Corporation Dynamic ram storage techniques
US7088606B2 (en) 2004-03-10 2006-08-08 Altera Corporation Dynamic RAM storage techniques
WO2006007566A1 (en) * 2004-07-01 2006-01-19 Altera Corporation Integrated circuit structures for increasing resistance to single event upset
US20060001045A1 (en) * 2004-07-01 2006-01-05 Sidhu Lakhbeer S Integrated circuit structures for increasing resistance to single event upset
US20080074145A1 (en) * 2004-07-01 2008-03-27 Sidhu Lakhbeer S Integrated circuit structures for increasing resistance to single event upset
US7319253B2 (en) 2004-07-01 2008-01-15 Altera Corporation Integrated circuit structures for increasing resistance to single event upset
US7465971B2 (en) 2004-07-01 2008-12-16 Altera Corporation Integrated circuit structures for increasing resistance to single event upset
US7647537B2 (en) * 2004-11-30 2010-01-12 Fujitsu Limited Programmable logic device, information processing device and programmable logic device control method
US20060117234A1 (en) * 2004-11-30 2006-06-01 Fujitsu Limited Programmable logic device, information processing device and programmable logic device control method
US20090031104A1 (en) * 2005-02-07 2009-01-29 Martin Vorbach Low Latency Massive Parallel Data Processing Device
US20070123091A1 (en) * 2005-11-18 2007-05-31 Swedberg Benjamin D Releasable Wire Connector
US7539914B1 (en) * 2006-01-17 2009-05-26 Xilinx, Inc. Method of refreshing configuration data in an integrated circuit
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
US20090199167A1 (en) * 2006-01-18 2009-08-06 Martin Vorbach Hardware Definition Method
US7772881B1 (en) * 2006-09-29 2010-08-10 Altera Corporation Method and apparatus for in-system programmability
JP2015122738A (en) * 2013-11-22 2015-07-02 株式会社半導体エネルギー研究所 Semiconductor device
US20150263734A1 (en) * 2014-03-13 2015-09-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
US9385720B2 (en) * 2014-03-13 2016-07-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
US9722615B2 (en) 2014-03-13 2017-08-01 Semiconductor Energy Laboratory Co., Ltd. Method for operating programmable logic device

Similar Documents

Publication Publication Date Title
US5859544A (en) Dynamic configurable elements for programmable logic devices
US4651304A (en) EPROM memory device having a test circuit
EP0293339B1 (en) Nonvolatile memory device with a high number of cycle programming endurance
JP3373632B2 (en) Nonvolatile semiconductor memory device
US5917753A (en) Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells
US6052307A (en) Leakage tolerant sense amplifier
US20070081379A1 (en) Write assist for latch and memory circuits
US5117426A (en) Circuit, device, and method to detect voltage leakage
US7869275B2 (en) Memory structure capable of bit-wise write or overwrite
JPH07326199A (en) Source Programmable Nonvolatile Programmable Bistable Multivibrator for Memory Redundancy Circuits
KR960001327B1 (en) Dynamic random access memory device with built-in test mode
US5790448A (en) On-chip program voltage generator for antifuse repair
EP0309180A2 (en) Semiconductor non-volatile memory device
US7301797B2 (en) Method of operating semiconductor integrated circuit including SRAM block and semiconductor integrated circuit including SRAM block
EP0544461B1 (en) Method for programming a field prgrammable gate array
US5274778A (en) EPROM register providing a full time static output signal
EP0412781B1 (en) Test method for an integrated circuit including non-volatile memory cell capable of temporarily holding information
US5568436A (en) Semiconductor device and method of screening the same
KR100215535B1 (en) Semiconductor memory device
JPH0773686A (en) Nonvolatile semiconductor memory device and test method thereof
US4827451A (en) Safety device for the programming of an electrically programmable non-volatile memory
US7016219B1 (en) Single transistor non-volatile memory system, design, and operation
US6826112B2 (en) Low power logic gate
JPH09320296A (en) Semiconductor memory device
US5198998A (en) Erasable programmable read only memory

Legal Events

Date Code Title Description
AS Assignment

Owner name: ALTERA CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NORMAN, KEVIN;REEL/FRAME:008203/0937

Effective date: 19960903

AS Assignment

Owner name: ALTERA CORPORATION, A CORPORATION OF DELAWARE, CAL

Free format text: MERGER;ASSIGNOR:ALTERA CORPORATION, A CORPORATION OF CALIFORNIA;REEL/FRAME:009040/0698

Effective date: 19970325

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12