JPH09320296A - Semiconductor memory device - Google Patents

Abstract

(57) An object of the present invention is to provide a semiconductor memory device capable of shortening a test time by surely applying a voltage stress to a plurality of word lines in a burn-in mode. In a test mode, in response to a test instruction signal TEST, an external power supply voltage V _CCQ is applied to a word line drive voltage V _pp output from a V _pp generation circuit 107. The word line drive signal generation circuit 505 receives the test instruction signal TEST and the burn-in signal TC to select a plurality of word lines to drive, and receives the word line drive voltage V _pp to drive the selected word line. Generate a word line drive signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a structure for reliably performing an accelerated test such as a burn-in test of the semiconductor memory device.

[0002]

2. Description of the Related Art For semiconductor devices such as semiconductor memory devices, in order to ensure product reliability, potential defects of the semiconductor device are revealed and defective devices are removed before shipment. Screening is performed. As a method of performing this screening, "burn-in" that can simultaneously realize both electric field acceleration and temperature acceleration is often used.
In this burn-in, the operating voltage and the operating temperature are made higher than the values in actual use to operate the semiconductor device.
A semiconductor device that is likely to cause an initial operation failure due to a stress applied to the semiconductor device for a short period of time under an initial failure period under actual use conditions is preliminarily selected and screened before shipment. Alternatively, by removing a semiconductor device which may cause an initial operation failure due to a potential failure due to a minute defect before shipment, the reliability of the product of the semiconductor device can be increased.

A dynamic random access memory (hereinafter abbreviated as DRAM) will be specifically described. In actual use, the power supply voltage is 3.3 V and the ambient temperature is 70 ° C.
However, in burn-in, the power supply voltage is set to 4.9.
It is common to set 5V and the ambient temperature to 125 ° C.

As described above, a semiconductor device having a defect is screened in a short period of time by operating the semiconductor device under conditions severer than actual use conditions. With higher integration and larger capacity of semiconductor memory devices, screening tends to become difficult and the time required for screening tends to significantly increase.

For example, in a semiconductor memory device, memory cells are arranged in rows and columns, word lines are arranged corresponding to each row, and bit line pairs are arranged corresponding to each row. By selecting the word line and bit line pairs,
A memory cell arranged corresponding to the intersection of the bit line and the word line is selected, and data is written or read in the selected memory cell. When a memory cell is selected, one word line is selected from a plurality of word lines, and a drive voltage for bringing this word line into a selected state is transmitted onto this selected word line.

In the burn-in test, a driving voltage higher than that in the normal operation is repeatedly applied to the plurality of word lines in a predetermined order, so that a voltage stress is applied to the insulating film around the word lines. It is added for a long time. As a result, if there is a portion having a low breakdown voltage in the insulating film around the word line, that portion is destroyed, and a potential defective device can be screened. Other potential defects are caused by dielectric breakdown of the interlayer insulating film or the gate insulating film of a MOS transistor (insulated gate field effect transistor), and electromigration of word lines and other signal wirings. There are disconnections.

In the case of a semiconductor memory device, as the storage capacity increases, the number of word lines also increases accordingly. If the burn-in test time is constant, the number of times one word line is selected decreases in proportion to the increase in the number of word lines. The number of selections is represented by N / T. Here, N is the number of word lines and T is the burn-in time. However, the burn-in time indicates the time during which the semiconductor device operates under acceleration conditions.

As a result, since the applied voltage stress is reduced, a potential defect that could be realized in the past cannot be realized, which causes a problem that the defect cannot be detected. If the same voltage stress is applied, this problem can be solved, but for this purpose, the burn-in time needs to be lengthened, the time required for screening becomes longer, and the screening test cannot be performed effectively. The problem arises. It may be possible to increase the voltage applied during burn-in, but in this case, the insulating film in a normal portion may be destroyed, which causes a problem that a normal semiconductor device is defective.

Therefore, as a method of applying a desired voltage stress without increasing the burn-in time, a plurality of word lines are simultaneously selected at the time of burn-in. That is, a circuit for simultaneously selecting a plurality of word lines at the time of burn-in is provided inside the semiconductor memory device, and a state in which a plurality of word lines can be simultaneously selected is set. An operation mode in which a plurality of word lines are simultaneously selected in the burn-in test is generally called "burn-in mode", and is already known as disclosed in, for example, Japanese Patent Laid-Open No. 4-258880.

FIG. 10 is a block diagram schematically showing an overall structure of a conventional DRAM. Referring to FIG. 10, a conventional DRAM 100 has a memory cell array 1 having memory cells arranged in a matrix of rows and columns.
01, an address buffer 102 for generating internal row address signals A ₀ to A _N receives an address signal X ₀ to X _N from the outside, and decodes the internal row address signal from the address buffer 102, the memory cell 101 A row decoder 103 for selecting a corresponding row, and a word driver 104 for raising the potential of a word line arranged in the selected row in response to a decode signal output from row decoder 103 are included.

A plurality of word lines are provided in memory cell array 101, and each word line is connected to a memory cell in a corresponding row. In FIG. 10, 2
Book word lines WL1 and WL2 are representatively shown.

DRAM 100 further includes an internal power supply voltage circuit 106 which brings externally applied power supply voltage V _cc to a predetermined voltage level for an internal circuit.

The internal power supply voltage circuit 106, more specifically, V boosts the external power supply voltage V _cc to a predetermined voltage level.
_{A pp} generation circuit 107 is included.

The word line drive voltage V _pp output from the V _pp generator 107 is the word line drive signal generator 105.
And the word driver 104.

The DRAM 100 further receives a control signal generation circuit 108 which receives various timing signals from the outside and generates an internal control signal, an internal control signal / RAS output from the control signal generation circuit 108, and an address buffer 1.
And a word line drive signal generation circuit 105 which outputs a word line drive signal in response to a predetermined internal row address signal input from the signal line 02. The word driver 104 transmits this word line drive signal to the word line corresponding to the row selected by the row decoder 103.

The DRAM 100 further decodes an internal column address signal from the address buffer 102 and selects a corresponding column of the memory cell array 101, and a data of the memory cell of the selected one row of the memory cell array 101. A sense amplifier that detects and amplifies the column, and an IO gate that connects the column selected by the column address decoder 109 to the output circuit 110. FIG.
In 0, the sense amplifier and the IO gate are shown as one block 111.

The output circuit 110 uses the external power supply voltage V _CCQ, which is different from the above-mentioned power supply voltage V _cc , as a power supply and blocks 1
According to the internal read data read from 11, external read data D / Q is generated.

FIG. 11 shows the word line drive voltage shown in FIG.
V_ppTo generate V_ppAn example of the circuit configuration of the generation circuit 107
FIG. In FIG. 11, V_ppGeneration circuit 107
Is a black oscillator composed of a ring oscillator (not shown).
Clock signal input from the clock signal source via input terminal 3.
Power supply voltage V in response to signal φ_ccTo a predetermined voltage level
Charge pump circuit 120 for compressing, and word line described later
Drive original signal φ_WClock signal source (not shown)
Clock signal φ supplied from the input terminal 7 via _RIn response
In response, the power supply voltage V_ccVoltage to a predetermined voltage level.
Charge pump circuit 121 and charge pump circuit 12
V in response to the output of 0, 121_ppOutput of generation circuit 107
A voltage control circuit 122 for suppressing the force to a predetermined potential, and V_ppDeparture
Word line drive voltage V, which is the output voltage of the raw circuit_ppThe charge of
Capacity C that accumulates in shape₀And

Charge pump circuit 120 includes a capacitor C1 and N channel MOS transistors NT1 and NT2. The N-channel MOS transistor NT1 includes a V _cc power supply node 1 for supplying a power supply voltage V _cc and a capacitor C.
1 connected to the output node 2 of the _Vcc power supply node 1
Receives the potential of. The N-channel MOS transistor NT2 is connected to the output node 2 of the capacitor C1 and V _pp
It is connected between V _pp power supply node 4 corresponding to the output node of the generation circuit and receives the potential of output node 2 of capacitor C1 at its gate.

In the charge pump circuit 120, when the clock signal φ is not input to the node 3,
Since N channel MOS transistor NT1 is in the conductive state, the voltage level of output node 2 is ( _Vcc - _VTN ). Here, V _TN is an N-channel MOS transistor N
It is the threshold voltage of T1 and NT2. In this state,
When clock signal φ is input to node 3, the charge of capacitor C1 is injected into output node 2 and the voltage level of output node 2 is boosted. As a result, N-channel MOS
Transistor NT2 becomes conductive and the voltage level of V _pp power supply node 4 rises corresponding to the voltage charged by capacitor C1.

[0021] When the clock signal φ is applied repeatedly, the voltage level of the final output node 2 (2V _cc -V _TN), and the voltage level of V _pp supply node 4 (2V _cc -2
V _TN ).

The operation of the charge pump circuit 121 is basically the same as that of the charge pump circuit 120. When the word line is driven by the voltage level of the V _pp power supply node 4, the charge pump circuit 121 supplements the charges supplied to the word line and prevents the voltage supplied to the word line from decreasing.

The voltage control circuit 122 is an N channel MOS.
The transistors NT5 and NT6 are included and connected in series between the V _cc power supply node 1 and the V _pp power supply node 4. The gate of the N-channel MOS transistor NT6 is connected to the V _pp power supply node 4 and is connected to the N-channel MOS transistor N6.
The gate of T5 is an N-channel MOS transistor NT5
And NT6 are connected to each other.

In the voltage control circuit 122, when the voltage level of the V _pp power supply node 4 rises to (V _cc + 2V _TN ) or more, the N-channel MOS transistors NT6 and NT5 become conductive, and the voltage level of the V _pp power supply node 4 becomes high. To (V
_cc + 2V _TN )

The stabilizing capacitor C ₀ stores electric charges corresponding to the voltage level of (V _cc + 2V _TN ). V _pp power supply node 4
The word line drive voltage V _pp corresponding to the output voltage of V is held at (V _cc + 2V _TN ) by the function of the stabilizing capacitance C ₀ .

FIG. 12 is a block diagram showing an example of the structure of the word line drive signal generation circuit 105 shown in FIG.
In FIG. 12, the word line drive signal generation circuit 105
Is an internal control signal / RA from the control signal generation circuit 108.
Input S and generate word line drive original signal φ _W φ _W
A generation circuit 125, a predecoder 126 for decoding the internal row address signal input from the address buffer 102 in response to the original word line drive signal φ _W , and the V _pp generation circuit 10.
A signal booster circuit 127 that receives the output voltage V _{pp of} 6 and boosts the decode signal generated from the predecoder 126.
With.

FIG. 13 is a diagram showing an example of a circuit configuration of the predecoder 126 and the signal boosting circuit 127 of FIG. In FIG. 13, the predecoder 126 has a word line driving original signal φ _W from the φ _W generation circuit 125 and internal row address signals A ₀ and A ₁ from the address buffer 102.
An inverter (not shown) receives / A ₀ and / A ₁ obtained by inverting A ₀ and A ₁ , respectively, and outputs four decoded signals.

The signal boosting circuit 127 includes four level shifters 128 having the same structure, only one of which has an internal structure, and the rest of which is not shown. One corresponding level shifter 128 is connected to each of the four decoded signals output from the predecoder 126. Each level shifter 128 commonly receives the word line drive voltage V _pp from the V _pp power supply node 4 of the V _pp generation circuit 107.

The predecoder 126 receives the internal row address signal.
A according to the combination of input₀And A ₁And enter the address
NAND circuit 40a for signal, / A₀And A₁And enter
A NAND circuit 40b for inputting a force address signal, and₀When/
A₁NAND circuit 40c with and as input address signals
And / A₀And / A₁NAN whose input address signals are and
D circuit 40d. Each NAND circuit has a word line
Drive original signal φ_WIs further input.

In predecoder 126, when word line drive original signal φ _W rises to H level, the output of the NAND circuit in which the applied input address signals are both at H level becomes L level, and the output of the other NAND circuits. The output becomes H level. Therefore, one of the four decoded signals
The decoded signal of becomes the L level.

Each level shifter 128 has an N channel MO.
S transistors NT10 and NT11 and P channel MO
It includes S transistors PT1 and PT2 and an inverter 10a.

N-channel MOS transistor NT10
Is connected between the P channel MOS transistor PT1 and the ground node and is the output of the predecoder 126.
The gate receives a signal obtained by inverting a corresponding one decode signal of the two decode signals by the inverter 10a. N-channel MOS transistor NT11 is connected between P-channel MOS transistor PT2 and the ground node, and receives corresponding one decode signal of the four decode signals output from predecoder 126 at its gate. The P-channel MOS transistor PT1 has V _pp
V _pp power supply node 4 of generation circuit 107 and N-channel MOS
It is connected between transistor NT10 and its gate, and is connected to output node 11 which is a connection point between P channel MOS transistor PT2 and N channel MOS transistor NT11. P-channel MOS transistor PT2 is, V V of _pp generating circuit 107 _pp supply node 4 and N
It is connected to the channel MOS transistor NT11 and has its gate connected to the P-channel MOS transistor PT.
1 and the N-channel MOS transistor NT10.

The level shifters 128, if the input signal is L level, the N-channel MOS transistor NT10 is turned (NT11 is nonconductive), by conducting a P-channel MOS transistor PT2, the output node 11 of the V _pp Output a signal with voltage amplitude. On the other hand, when the input signal is at H level, the N-channel MOS transistor N
T11 becomes conductive and the potential of the output node 11 becomes the ground level.

That is, the output of the predecoder 126.
One of the four decoded signals at the L level
The level shifter 128 to which the input signal is input is activated,
As a result, the word line drive voltage V_pp(= V_cc+ 2V_TN)of
Output voltage level signal. On the other hand, for other H levels
The three decode signals that are
You. Therefore, the output of each level shifter 128 is
Drive line drive signal φ_W1~ Φ _W4Signal of any one of
It is transmitted to the word driver 104 in a sexualized state.

FIG. 14 shows the row decoder 103 shown in FIG.
FIG. 3 is a block diagram showing an example of configurations of a word driver 104 and a word line. The word driver 104 includes a plurality of drive circuits 129 corresponding to a plurality of decode signals which are output signals of the row decoder 103. Drive circuit 1
Each of 29 is connected to four word lines.

FIG. 15 is a diagram showing an example of the drive circuit 129 shown in FIG. In FIG. 15, drive circuit 129 corresponding to four word lines WL1, WL2, WL3, WL4 is representatively shown.

N-channel MOS transistor NT22,
When the decode signal input from the row decoder 103 is L level, NT25, NT28, and NT31 become conductive by the H level signal inverted via the inverter 51a, and are connected to the word lines WL1, WL2, WL3, WL4. The voltage levels of 20, node 21, node 22, and node 23 are set to the ground level.

N-channel MOS transistor NT21,
NT24, NT27, and NT30 drive word lines WL1, WL2, WL3, and WL4, respectively. Each N-channel MOS transistor NT21, NT24, NT2
7 and NT30 respectively receive the output signals φ _W1 , φ _W2 , φ _W3 and φ _W4 of the signal boosting circuit 127 in the word line drive signal generation circuit 105 shown in FIG.

N-channel MOS transistor NT20,
NT23, NT26 and NT29 are an input node 25 for inputting a decode signal output from the row decoder 103 and N channel MOS transistors NT21, NT24 and NT2.
7 and the gate of NT30, respectively. Each N-channel MOS transistor NT20, NT23, N
T26 and NT29 are N-channel MOS transistors N
By collecting all the charges charged through the gate capacitances of T21, NT24, NT27, and NT30 into the gates of the N-channel MOS transistors NT21, NT24, NT27, and NT30, each N-channel MOS transistor NT
Increase the gate voltage of 21, NT24, NT27 and NT30.

When the decode signal input from row decoder 103 is at H level, N channel MOS transistor N
T20, NT23, NT26, and NT29 become conductive, and N-channel MOS transistors NT21 and NT2
4, NT27, NT30 are all conductive. On the other hand, N-channel MOS transistors NT22, NT25, NT2
8 and NT31 become non-conductive by the L level signal via the inverter 51a.

Here, the output signal φ of the signal boosting circuit 127
_W1 of the to [phi] _W4, for example, if phi _W1 is the active state (voltage amplitude _{V pp = V cc + 2V TN} ) in, N-channel MOS
The voltage level of the node 20 becomes V _pp = V _cc + 2V _TN via the transistor NT21, and the word line WL1 is activated (selected). On the other hand, φ _W2 and φ
N-channel MOS transistor NT input by _W3 and φ _W4
The word lines WL2, WL3, and WL4 respectively connected to 24, NT27, and NT30 are surely in the non-selected state.

[0042]

Therefore, in the normal operation mode (a mode other than the operation mode in which the acceleration test such as the burn-in mode is performed), the drive voltage applied to one selected word line is shown in FIG. It is determined by the output voltage of the V _pp generation circuit 107. In this state,
Normally, the selected word line voltage level is the word line drive voltage V _pp (= V _cc +) which is the output voltage of the V _pp generator.
2V _TN ).

On the other hand, in the burn-in mode, as shown in FIG.
A plurality of word lines are driven using the V _pp generation circuit 107 shown in FIG. In this case, the voltage level of the selected word line changes due to the parasitic capacitance of the selected word lines. Therefore, in the burn-in mode, there are cases where a sufficiently high voltage load cannot be applied to the word line, which causes a problem that the burn-in test cannot be performed accurately.

Therefore, in the burn-in mode,
Since a sufficient voltage level cannot be obtained using the conventional V _pp generation circuit 107, a means of increasing the output voltage level of the V _pp generation circuit 107 can be considered.

However, in order to raise the output voltage level of the V _pp generation circuit 107, it is necessary to increase the capacity of the stabilizing capacity C ₀ for accumulating the word line drive voltage V _pp in the form of electric charges, which increases the chip size. This leads to an increase in chip cost.

Normally, in a 4M DRAM, the parasitic capacitance per word line is about 3.5 _PF . All word lines 20
In the case of selecting every other word line out of 48, assuming that the total parasitic capacitance of 1024 word lines is C _X , C _X = 3.5 _PF × 1024 = 3584 _PF . In order to use the reduction in the voltage level of the word line, in the V _pp generation circuit 106, at least 10 of C _X is required.
Double stabilizing capacitance C ₀ is required.

In fact, the oxide film used in 4M DRAMs
Stabilizing capacitance of MOS type capacitance of 120Å₀Used as
In that case, the above-mentioned stabilizing capacity C₀To meet the conditions of
, The size of the MOS capacitor is 12.1mm^TwoBecomes this
The value is 50, which is the typical chip size of 4M DRAM.
mm^Two24% of the total. Therefore, the stabilizing capacity C ₀
By increasing, the chip area increases and the chip cost increases.
There is a problem that

Therefore, an object of the present invention is to provide a semiconductor device capable of selecting a plurality of word lines in the test mode, preventing a decrease in the voltage level of the word lines, and imposing a sufficient voltage condition. That is.

[0049]

According to another aspect of the semiconductor memory device of the present invention, a plurality of memory cells are arranged in a matrix of a plurality of rows and columns, and are connected to the plurality of rows of the memory cells. A plurality of word lines, an internal power supply voltage circuit that supplies a drive voltage to each of the plurality of word lines, an external power supply that supplies a voltage for an output circuit that outputs the data of the memory cells, and a normal mode when specified. ,
A first state in which the output of the internal power supply voltage circuit is selected and supplied; and a first state in which the output voltage of the external power supply is selected and supplied when the test mode is designated. The voltage switching means for switching between the two states and the word line selection driving means for simultaneously selecting a plurality of word lines from the plurality of word lines when the test mode is designated and driving them by the output of the voltage switching means. .

In the semiconductor memory device according to a second aspect of the invention, the voltage switching means discriminates between the first state and the second state in response to a test instruction signal for designating the test mode. First switching means for
Second switching means for applying the supply voltage of the external power supply for the output circuit to the output of the internal power supply voltage circuit in response to the output of the first switching means for determining the second state. Including.

According to another aspect of the semiconductor memory device of the present invention, the voltage switching means generates a predetermined voltage in response to the test instruction signal for designating the test mode, and the voltage generating means. Third switching means controlled by the output of the means to apply the supply voltage of the external power supply for the output circuit to the output of the internal power supply voltage circuit.

According to another aspect of the semiconductor memory device of the present invention, the voltage generating means performs a logical operation of the test instruction signal and the clock signal and outputs a discrimination signal, and a charge according to the discrimination signal. And a charge pump circuit for accumulating the charge to generate the predetermined voltage.

According to another aspect of the semiconductor memory device of the present invention, the word line selection drive means selects a word by receiving a test instruction signal for designating a test mode and a signal designating a selection mode of the word line. Selection control means for generating a selection signal designating a line, predecoding means for decoding an internal row address signal of a word line to be selected based on a test instruction signal and the selection signal, and an output of the predecoding means And boosting means for boosting the original word line driving signal applied to the word line to be driven by the output of the voltage switching means.

According to another aspect of the semiconductor memory device of the present invention, the word line selection driving means receives the test instruction signal for designating the test mode and the signal designating the selection mode of the word line and selects the word. A selection control means for generating a selection signal for designating a line; a predecoding means for decoding an internal row address signal of a word line to be selected based on the test instruction signal and the selection signal; and an output of the predecoding means. Drive means for receiving and supplying a voltage to the word line to be driven by the output of the voltage switching means.

According to another aspect of the semiconductor memory device of the present invention, the word line selection driving means includes means for selecting every other one of the plurality of word lines.

[0056]

According to the above-mentioned means, by selecting a plurality of word lines at the same time and placing them under a stable high voltage condition,
It is possible to apply a desired voltage stress to the selected word line while significantly shortening the burn-in test time.

Further, since the voltage switching means applies the power supply voltage from the outside to the word line drive voltage V _pp according to the test mode, in the normal operation mode, the high voltage is not applied to the word line and the word line is not applied. Avoid the loss of wire.

[0058]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a schematic block diagram showing an entire structure of a DRAM according to a first embodiment of the present invention. The components common to the conventional example of FIG. 10 are designated by the same reference numerals and reference symbols. , The description is omitted.

The embodiment of FIG. 1 differs from the conventional example of FIG. 10 in the following points. That is, an internal power supply voltage circuit 501 for generating a word line drive voltage is provided in place of the internal power supply voltage circuit 106 of FIG. In this case, the internal power supply voltage circuit 501 adds the external power supply voltage V _CCQ to the word line drive voltage according to the test instruction signal TEST designating the test mode applied from the outside, in addition to the V _pp generation circuit 107 shown in FIG. It includes a voltage switching circuit 502 applied to V _pp .

FIG. 2 is a diagram specifically showing a structure of internal power supply voltage circuit 501 for generating a word line drive voltage used in the DRAM of FIG.

In FIG. 2, the internal power supply voltage circuit 501
As described above, the conventional V _pp generator 1 shown in FIG.
07 and a test instruction signal TEST designating a test mode input from the outside, the external power supply voltage V _CCQ supplied from the external power supply is selectively applied to the word line drive voltage V _pp output from the V _pp generation circuit 107. Applied voltage switching circuit 5
02.

[0062] Voltage switching circuit 502 includes a P-channel MOS transistor PT50 connected between the V _pp supply node 4 V _CCQ power supply node 5 and V _pp generating circuit 107, P
A gate channel MOS transistor PT50 and an N-channel MOS transistor NT50 connected between the ground node, high connected between V _pp supply node 4 of the gate and the V _pp generating circuit 107 of the P-channel MOS transistor PT50 And a resistance element R50. The N-channel MOS transistor NT50 has a test instruction signal T
Or holding the word line driving voltage V _pp in accordance with EST, choose whether to apply the external power supply voltage V _CCQ to word line driving voltage V _pp.

P-channel MOS transistor PT50
The high resistance element R50 is connected to the test instruction signal TEST at the H level.
The bell becomes the N-channel MOS transistor NT50
Depending on the state of conduction, V_CCQPower node 5
From the word line drive voltage V _ppApply to.

That is, when test instruction signal TEST is at H level (test mode), N channel MOS transistor NT50 is rendered conductive, and node 50 which is the connection point between the gate of P channel MOS transistor PT50 and N channel MOS transistor NT50. Potential becomes the ground level. As a result, the P-channel MOS transistor P
When T50 becomes conductive, a predetermined voltage is supplied from the V _CCQ power supply node 5 to the V _pp power supply node 4 to prevent the drive voltage on the word line from decreasing.

Normally, when the power supply voltage V _cc is 3.3 V, V _cc is about 1.5 times 4.95 V in the burn-in mode.
Is set to _Assuming that the threshold value V _TN of the N-channel MOS transistor in the V _pp generation circuit 107 is 0.7 V, the word line drive voltage which is the output of the V _pp generation circuit 107 is 4 from the above equation (V _cc + 2V _TN ). .95 + 2 ×
It becomes 0.7 = 6.35V. Therefore, from the power supply voltage (not shown) for the output circuit to the external power supply voltage V of 6.35V.
_{If CCQ} is supplied and applied to the word line drive voltage V _pp at the time of testing, the word line can be driven more stably than in the case of driving only with the output V _pp of the V _pp generation circuit 107.

It should be noted that it is possible to use a vacant terminal of the semiconductor memory device (for example, an address terminal which becomes unnecessary at the time of testing due to selection of a plurality of word lines at the time of testing) for voltage application at the time of testing as described above. However, the reason why another terminal of the external power supply voltage V _CCQ is used as described above is as follows.

That is, according to the present invention, a switching element having a large size (that is, a large parasitic capacitance) for applying a voltage to V _pp (for example, the P channel MO of FIG. 2).
The S-transistor PT50) is required, and if an address terminal or the like is used to supply the applied voltage, a large parasitic capacitance of the switching element will be coupled to the address terminal. Therefore, in normal operation other than the test mode, the propagation speed of the address signal becomes slow due to this parasitic capacitance. However, in the present invention, such a problem does not occur because the external power supply terminal is used instead of the vacant address terminal.

In the output circuit to which external power supply voltage V _CCQ is applied, since the operating power supply voltage margin is large, there is no operational problem even if the external power supply voltage V _CCQ is large.

[Second Embodiment] FIG. 3 is a diagram showing another embodiment of voltage switching circuit 502 of FIG. In FIG. 3, the voltage switching circuit 502 includes a voltage generation circuit 503 that generates a predetermined voltage according to the test instruction signal TEST, and a word line drive voltage V _pp according to the output of the voltage generation circuit 503.
N-channel MO that applies voltage of external power supply voltage V _CCQ to
S-transistor NT51.

The voltage generating circuit 503 has a charge pump circuit 504 for generating a predetermined voltage and a 2-input NAND circuit 50a for controlling the operation of the charge pump circuit 504.
And a high resistance element R51.

A test instruction signal TEST and a clock signal supplied from a clock signal source (not shown) are input to the NAND circuit 50a.

When the test instruction signal TEST is at H level (test mode), the NAND signal is generated by the clock signal φ.
The charge pump circuit 504 operates via the circuit 50a, whereby the charge pump circuit 504 outputs a boosted signal from its output node 51. As a result, the N-channel MO in which the output node 51 and its gate are connected
The S transistor NT51 is rendered conductive, and a predetermined voltage is applied to the V _pp power supply node 4 from the V _CCQ power supply node 5.

On the other hand, the test instruction signal TEST is at L level
If it is (in normal operation mode), charge
Since the pump circuit 504 does not operate, the output node 51 is
V by R51_CCQThe same voltage level as the power supply node 5
Become. Therefore, the N-channel MOS transistor NT
51 is a non-conduction state, and V_CCQPower supply node 5 to V _pp
No voltage is applied to the power supply node 4.

[Third Embodiment] FIG. 4 is a schematic block diagram showing an entire structure of a DRAM according to a third embodiment of the present invention. D of the first and second embodiments shown in FIGS.
It differs from the RAM in the following points. That is, in place of the word line drive signal generation circuit 105 of FIG. 1, a word line drive signal generation circuit 505 that receives a test instruction signal TEST and a burn-in signal TC from the outside and generates a word line drive signal is provided.

FIG. 5 is a diagram schematically showing a configuration of word line drive signal generation circuit 505 used in the DRAM of FIG.

In FIG. 5, a word line drive signal generation circuit
505 is the same φ as in the conventional example of FIG. _WGeneration circuit 125
And a word to select with the test instruction signal TEST from the outside
In response to the burn-in signal TC that specifies the line, the selection signal
Output selection control circuit 506 and this selection signal and test
Selection by receiving instruction signal TEST and internal row address signal
To decode the internal row address signal of the word line to be
A coder 507 and an output signal of the predecoder 507
φ_WWord line drive original signal φ output from the generation circuit 125_W
The word line drive original signal of the word line to be driven based on
φ_WAnd a boosting circuit 508 for boosting the voltage.

FIG. 6 is a diagram showing an example of a circuit configuration of selection control circuit 506 in word line drive signal generation circuit 505 shown in FIG. The selection control circuit 506 includes two 2-input NAND circuits 51a and 51b and inverters 60a and 6b.
0b.

The NAND circuit 51a receives the test instruction signal T
The signal obtained by inverting the EST and the burn-in signal TC are input. The NAND circuit 51b receives the signal obtained by inverting the test instruction signal TEST and the signal obtained by inverting the burn-in signal TC.

When the test instruction signal TEST is at H level (test mode) and the burn-in signal TC is at L level, the output signal A of the NAND circuit 51a is at H level,
The output signal B of the NAND circuit 51b becomes L level. On the other hand, if the burn-in signal TC is set to H level, NAND
The output signal A of the circuit 51a is L level, and the NAND circuit 51
The output signal B of B becomes H level. That is, the output signals A and B show different states.

FIG. 7 shows a word line drive signal generation circuit 505.
6 is a diagram showing a specific configuration of a predecoder 507 and a booster circuit 508 in FIG.

The predecoder 507 has four 3-input NAs.
It includes ND circuits 52a, 52b, 52c and 52d and four 2-input NAND circuits 53a, 53b, 53c and 53d. NAND circuit 52a receives internal row address signals A ₀ and A ₁ at its inputs. NAND circuit 52b receives internal row address signals / A ₀ and A ₁ at its inputs. NAND
Circuit 52c receives internal row address signals A ₀ and / A ₁ at its inputs. NAND circuit 52d receives internal row address signals / A ₀ and / A ₁ at its inputs. Furthermore, each NAN
A signal / TEST obtained by inverting the test instruction signal TEST by the inverter 70a shown in FIG. 5 is input to the D circuits 52a, 52b, 52c, 52d.

The NAND circuit 53a is the NAND circuit 52.
The input receives the output of a and the output signal A of the selection control circuit 506. NAND circuit 53b receives the output of NAND circuit 52b and the output signal B of selection control circuit 506 at its inputs.
NAND circuit 53c receives the output of NAND circuit 52c and the output signal A of selection control circuit 506 at its inputs. NAN
The D circuit 53d receives the output of the NAND circuit 52d and the output signal B of the selection control circuit 506 at its inputs.

When the test instruction signal TEST is at the H level (test mode), the NAND circuits 52a, 52b, 52c and 52d at the previous stage in the predecoder 507 have the L level signal / TEST inverted by the inverter 70a.
By T, all H level signals are temporarily output regardless of the internal row address signal from address buffer 102.

Here, if the burn-in signal TC is at the H level, the output signals A and B of the selection control circuit 506 have different logic levels as described above, so that the output signal A of the selection control circuit 506 is changed to the output signal A. NAND circuit 5 for input
The decode signals T ₁ and T ₃ output from 3a and 53c become L level, and the decode signals T ₂ and T ₄ output from the NAND circuits 53b and 53d receiving the output signal B of the selection control circuit 506 as input become H level. .

That is, the decode signal corresponding to the even-numbered word line and the decode signal corresponding to the odd-numbered word line are forcibly set to different values by the output signals A and B of the selection control circuit 506.

The booster circuit 508 includes four 2-input NANDs.
The circuit 54a, 54b, 54c, 54d and the same level shifter 128 as the conventional example shown in FIG. 12 are provided.

The NAND circuit 54a includes a predecoder 50.
The output T ₁ of the NAND circuit 53a in FIG. NAND circuit 54b receives as input the output T ₂ of NAND circuit 53b in predecoder 507. NA
The ND circuit 54c is a NAN in the predecoder 507.
The output T ₃ of the D circuit 53c is received at the input. The NAND circuit 54d is the NAND circuit 5 in the predecoder 507.
The 3d output T ₄ is received at the input. Further, each of the NAND circuits 54a, 54b, 54c, 54d has a φ _W generation circuit 1
The word line drive original signal φ _W output by 25 is input.

The NAND circuits 54a, 54b, 54c,
One level shifter 128 is connected corresponding to the output of 54d.

Of the decode signals T ₁ , T ₂ , T ₃ , T ₄ output from the predecoder 507, those of the L level are NAND circuits 54a, 54b, 54c, 54d.
The corresponding one of them is activated by the level shifter 128 and becomes a signal of the voltage level of the word line drive voltage V _pp . In this case, since the test mode is specified, the external power supply voltage V _CCQ is applied to the word line drive voltage V _pp as already described in connection with the first and second embodiments of FIGS. ing. On the other hand, of the decoded signals T ₁ , T ₂ , T ₃ and T ₄ output from the predecoder 507, those of the H level have the corresponding level shifter 12
The output signal of 8 is in the deactivated state. Therefore, in the third embodiment, by the control of the selection control circuit 506,
Every other word line is burned in.

Output signals φ _W1 , φ _W2 , φ of booster circuit 508
_W3 and φ _W4 are transmitted to the word driver 104.

[Fourth Embodiment] FIG. 8 is a block diagram showing a modification of word line drive signal generating circuit 505 and word driver 104 in FIG. In FIG. 8, the word line drive signal generation circuit 509 is the selection control circuit 5 of FIG.
06 and a predecoder 507.

The output signal of the word line drive signal generation circuit 509 is the NAND circuits 53a, 53b, 53 in FIG.
c, 53d output the decoded signals T ₁ , T ₂ , T ₃ ,
T ₄ and these signals are input to the word driver 510 whose specific configuration is shown in FIG.

The word driver 510 in FIG. 9 is supplied with the word line drive voltage V _pp from the internal power supply voltage circuit 501 as a power supply. In FIG. 9, word line WL1
Is connected to a node 30 which is a connection point between N channel MOS transistor NT52 and P channel MOS transistor PT52. P channel MOS transistor PT
52 is connected between V _pp power supply node 4 and node 30, and N-channel MOS transistor NT52 is connected between node 30 and the ground node. P channel MO
The gates of S-transistor PT52 and N-channel MOS transistor NT52 are connected at node 31 which is a connection point between N-channel MOS transistor NT53. P
The channel MOS transistors PT53 and PT54 have V
_pp is connected in parallel between the power supply node 4 and the node 31. The gate of P channel MOS transistor PT53 is connected to node 30. A precharge voltage is applied to the gate of the P channel MOS transistor PT54.
The N-channel MOS transistor NT53 is a row decoder 1
The decode signal output from the circuit 03 is input, and its gate receives the output signal T ₁ of the predecoder 507 shown in FIG.

Word lines WL1, WL2, WL3, WL4
Of the decode signals T ₁ , T ₂ , T ₃ , and T ₄ , the corresponding word lines of H level are activated by the word line drive voltage V _pp from the internal power supply voltage circuit 501.

Also in the fourth embodiment, every other word line is burned in under the control of the selection control circuit 506.

As described above, the present invention has been described by taking the example of the DRAM, but the present invention can be applied to all memories having a boosted word line such as static RAM and ROM. In the above embodiment, the word lines are selectively driven every other word line, but it is also possible to drive every four word lines and every eight word lines. However, in this case, the effect is inferior.

Further, although the effect of the burn-in test is described in the present invention, it is effective to select a plurality of word lines at the same time also in the memory retention characteristic test during operation (so-called disturb test). It can be applied for this purpose.

[0098]

As described above, the semiconductor memory device according to the first aspect includes the voltage switching means for supplying the voltage obtained by applying the supply voltage of the external power supply to the output of the internal power supply voltage circuit when the test mode is designated. Similarly, when the test mode is designated, a plurality of word lines are selected at the same time, and the word line selection driving means for driving the selected word line by the output of the voltage switching means is provided. Therefore, in a burn-in test or the like, stable high voltage stress can be applied to a plurality of selected word lines at the same time, so that the test time can be significantly shortened and a desired voltage stress can be applied to the selected word line. You can

According to the invention of claim 2, the voltage switching means receives the test instruction signal designating the test mode, determines whether the mode is the test mode or the normal operation mode, and according to the result, Since the output voltage of the internal power supply voltage circuit is selectively applied to the output voltage of the external power supply, when the normal operation mode is specified, the output of the internal power supply voltage circuit is supplied as it is and the test mode When specified, a higher voltage can be supplied than in the normal operation mode.

According to the third aspect of the invention, the voltage switching means generates the predetermined voltage according to the test instruction signal, and the output of the internal power supply voltage circuit under the control of this voltage. Since it is configured to include means for selectively applying the supply voltage of the external power supply, the output of the internal power supply voltage circuit must be supplied when the normal operation mode is specified, and when the test mode is specified. It is possible to supply a higher voltage than in the normal operation mode.

According to the fourth aspect of the present invention, the voltage generating means is configured to accumulate charges and generate a predetermined voltage when the test mode is designated by using the test instruction signal and the clock signal. Therefore, it is possible to easily determine that the test mode state is entered from the outside.

According to the invention of claim 5, the word line selection drive means receives the test instruction signal and the signal designating the selection mode of the word line and generates the selection signal designating the word line to be selected. Then, based on the selection signal, the internal row address signal of the selected word line is decoded, and in response to the decoding result, the word line drive original signal corresponding to the selected word line is boosted by the output of the voltage switching means. It is configured to generate a word line drive signal for a word line to be driven.
Therefore, when designating the test mode, you can easily select multiple word lines to be driven from the outside, and make sure that the selected word line is under a higher voltage condition than when designating the normal operation mode. You can

According to the invention of claim 6, the word line selection drive means receives the test instruction signal and the signal designating the selection mode of the word line and generates the selection signal designating the word line to be selected. Then, based on the selection signal, the internal row address signal of the selected word line is decoded, and upon receiving the decoding result, the voltage is supplied to the word line to be driven by the output of the voltage switching means. . Therefore, when designating the test mode, you can easily select multiple word lines to be driven from the outside, and make sure that the selected word line is under a higher voltage condition than when designating the normal operation mode. You can

According to the invention of claim 7, since every other word line can be selected, the test time such as the burn-in test can be greatly shortened.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a diagram specifically showing a configuration of an internal power supply voltage circuit for generating a word line drive voltage in the DRAM of the first embodiment of the present invention.

FIG. 3 is a diagram specifically showing a configuration of an internal power supply voltage circuit for generating a word line drive voltage in the DRAM of the second embodiment of the present invention.

FIG. 4 is a schematic block diagram showing an overall configuration of a DRAM according to a third embodiment of the present invention.

FIG. 5 is a diagram schematically showing a configuration of a word line drive signal generation circuit in a DRAM according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of a selection control circuit according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a specific configuration of a predecoder and a booster circuit according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing configurations of a word line drive signal generation circuit and a word driver in a DRAM according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a circuit configuration of a word driver according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional DRAM.

FIG. 11 is a circuit diagram showing a configuration of a conventional internal power supply voltage circuit.

FIG. 12 is a block diagram showing a configuration of a conventional word line drive signal generation circuit.

FIG. 13 is a circuit diagram showing a configuration of a conventional word line drive signal generation circuit.

FIG. 14 is a block diagram showing a configuration of a conventional row decoder and word driver.

FIG. 15 is a circuit diagram showing a configuration of a conventional word driver.

[Explanation of symbols]

1 V _CC power supply node, 4 V _pp power supply node, 5 V _CCQ
Power supply node, 102 address buffer, 103 row decoder, 104,510 word driver, 105,50
5, 509 word line drive signal generation circuit, 106, 50
1 Internal power supply voltage circuit, 107 V _pp generation circuit, 125
φ _W generation circuit, 502 voltage switching circuit, 503 voltage generation circuit, 506 selection control circuit, 507 predecoder, 508 booster circuit, NT1, NT2, NT5, NT
6, NT10, NT11, NT20 to NT31, NT5
0, NT51, NT52, NT53 N channel MOS
Transistors, PT1, PT2, PT50, PT52,
PT53, PT54 P-channel MOS transistor,
40a-40d, 50a, 51a, 51b, 52a-5
2d, 53a to 53d, 54a to 54d NAND circuit, R50, R51 high resistance element, C ₁ capacitor, C ₀
Stabilizing capacity 10a, 51a, 60a, 60b, 70
a inverter, 120, 121, 504 charge pump circuit, 128 level shifter, 122 voltage control circuit.

Claims (7)

[Claims] 1. A plurality of memory cells arranged in a matrix having a plurality of rows and columns, a plurality of word lines respectively connected to the plurality of rows of the memory cells, and a plurality of word lines respectively. An internal power supply voltage circuit that supplies a drive voltage, an external power supply that supplies a voltage for an output circuit that outputs the data of the memory cell, and an output of the internal power supply voltage circuit that is selectively supplied when a normal mode is designated. A voltage switching means for switching between a first state and a second state in which when a test mode is designated, a voltage obtained by applying the supply voltage of the external power supply to the output of the internal power supply voltage circuit is selected and supplied; Of the plurality of word lines at the same time, the word line selection driving means for driving by the output of the voltage switching means. 2. The voltage switching means, in response to a test instruction signal for designating the test mode, first switching means for discriminating between the first state and the second state, and Second switching means for applying a supply voltage of an external power supply for the output circuit to an output of the internal power supply voltage circuit in response to an output of the first switching means for determining the second state. The semiconductor memory device according to claim 1. 3. The voltage switching means is controlled by a voltage generating means for generating a predetermined voltage in response to a test instruction signal for designating the test mode, and an output of the voltage generating means, 2. The semiconductor memory device according to claim 1, further comprising a third switching unit that applies a supply voltage of an external power supply for the output circuit to an output of an internal power supply voltage circuit. 4. The voltage generating means performs a logical operation between the test instruction signal and the clock signal and outputs a determination signal; and a predetermined operation for accumulating charges according to the determination signal. 4. The semiconductor memory device according to claim 3, further comprising a charge pump circuit that generates the voltage of. 5. The word line selection drive means receives a test instruction signal for designating a test mode and a signal designating a selection mode of the word line, and generates a selection signal for designating a word line to be selected. Selection control means, predecoding means for decoding an internal row address signal of a word line to be selected based on the test instruction signal and the selection signal, and a word line to be driven based on the output of the predecoding means A boosting means for boosting the word line drive original signal applied to the output voltage of the voltage switching means.
The semiconductor memory device described. 6. The word line selection driving means receives a test instruction signal for designating a test mode and a signal designating a selection mode of the word line, and generates a selection signal designating a word line to be selected. A selection control means, a predecoding means for decoding an internal row address signal of a word line to be selected based on the test instruction signal and the selection signal, and a word line to be driven upon receiving an output of the predecoding means. 2. The semiconductor memory device according to claim 1, further comprising drive means for supplying a voltage according to the output of said voltage switching means. 7. The semiconductor memory device according to claim 1, wherein the word line selection driving means selects every other one of the plurality of word lines.