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US4552118A - Control circuit for controlling output pulse width using negative feedback signal - Google Patents

Control circuit for controlling output pulse width using negative feedback signal Download PDF

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Publication number
US4552118A
US4552118A US06/590,662 US59066284A US4552118A US 4552118 A US4552118 A US 4552118A US 59066284 A US59066284 A US 59066284A US 4552118 A US4552118 A US 4552118A
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Prior art keywords
signal
circuit
pulse
output
pulse width
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US06/590,662
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English (en)
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Hirokazu Fukaya
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NEC Corp
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NEC Corp
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
    • G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
    • G01R29/0273—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
    • F02P3/00—Other installations
    • F02P3/02—Other installations having inductive energy storage, e.g. arrangements of induction coils
    • F02P3/04—Layout of circuits
    • F02P3/045—Layout of circuits for control of the dwell or anti dwell time
    • F02P3/0453—Opening or closing the primary coil circuit with semiconductor devices
    • F02P3/0456—Opening or closing the primary coil circuit with semiconductor devices using digital techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant

Definitions

  • the present invention relates to a control circuit for controlling the pulse width of an output pulse signal by an input signal and a negative feedback signal, and more particularly, to a circuit for controlling the pulse width of a pulse signal used for determining a current supply time to an ignition coil in an ignition system for an internal combustion engine.
  • pulse width of a signal means a time period when the signal takes a high level or a low level within one cycle period.
  • the negative feedback signal is produced by converting the output signal into a first d.c. signal relative to the pulse width thereof.
  • the output signal is detected in the form of a pulse current flowing through a load driven by the output signal, and the pulse current is smoothed.
  • the input signal is also converted into a second d.c. signal relative to a pulse width thereof.
  • the circuit of this type can be applied to an ignition system in an internal combustion engine for the purpose of making the ignition energy from an ignition coil substantially constant.
  • the pulse signal in synchronism with the revolution of the engine is employed as the input signal. Therefore, the cycle period (the frequency) of the input signal is varied in accordance with the number of revolutions of the engine.
  • the pulse width of the input signal is also varied in accordance with the number of revolutions of the engine.
  • the output signal is used for controlling a current supply time to the ignition coil. In other words, a time period in which the output signal takes, for example, a high level (i.e., the pulse width of the output signal) affords the current supply time to the coil.
  • the negative feedback signal is generated in the form of a first d.c.
  • the input signal is converted into a second d.c. signal relative to the pulse width of the input signal.
  • the first and second d.c. signals are compared with each other to control the pulse width of the output signal.
  • the pulse width of the output signal becomes substantially constant, and the sufficient and substantially constant ignition energy is generated from the ignition coil over the entire range from a low revolution speed to a high revolution speed of the engine.
  • the pulse width of the input signal is, for example, shortened or prolonged for each period, there occurs such a serious problem that it becomes impossible to obtain the output signal having a predetermined pulse width.
  • the pulse width of the output signal is controlled by the input and negative feedback signals. More specifically, when the engine is under smooth revolution and producing an input signal having a pulse width corresponding to the number of revolutions of the engine, the cycle period (or pulse width) of the input signal is gradually varied in accordance with the acceleration and deceleration of the engine. Since the time-constant for the conversion of the output signal to the negative feedback signal is set smaller than such a gradual change in cycle period of the input signal, the output signal may be controlled so as to have a substantially constant pulse width. However, the engine is not always under smooth revolution.
  • the engine is started with the aid of self-starting motors.
  • the viscosity of the engine oil is increased to impair the smooth reciprocal movement of pistons.
  • smooth revolution of the engine can not be obtained.
  • the pulse width of the input signal produced in synchronism with the engine revolution may be randomly shortened or prolonged for each period, even when the frequency of the input signal is constant.
  • the conversion time-constant for producing the negative feedback signal becomes larger than the change in the pulse width of the input signal, thereby generating an output signal having a pulse width small than the desired one.
  • Such an undesired output signal is generated frequently if the pulse width of the input signal undergoes random changes continually.
  • the current supply time to the ignition coil is determined by the pulse width of the output signal.
  • the ignition coil is an inductive element, so that a current flowing therethrough is increased gradually in accordance with the time-constant which is determined by the inductance and resistance components of the coil. Therefore, the reduction in pulse width of the output signal causes a malfunction that the current flowing through the ignition coil does not reach the predetermined value. In other words, insufficient ignition energy is generated from the ignition coil. The insufficient ignition energy results in incomplete combustion of a gas mixture within the cylinder. If such a condition is repeated frequently, environmental pollution will be caused.
  • Another object of the present invention is to provide a pulse width control circuit suitable for use in an ignition system of internal combustion engines.
  • Still another object of the present invention is to provide a control circuit in which the frequent generation of an output signal having a pulse width smaller than a predetermined width is prevented.
  • An additional object of the present invention is to provide a detector for detecting a pulse having a pulse height less than a predetermined voltage.
  • a control circuit comprises a first circuit receiving an input signal and generating an output pulse signal and a feedback signal, the output pulse signal having a pulse width controlled by the input and feedback signals, a second circuit detecting the pulse width of the output signal and generating a detection signal when the detected width is narrower than a predetermined width, and a third circuit acting on the first circuit so as to broaden the pulse width of the output signal in response to the detection signal from the second circuit.
  • the circuit according to the present invention is provided with an additional loop consisting of the second and third circuits for changing the pulse width of the output signal in response to the detection signal in addition to a main loop for controlling the pulse width of the output signal by a negative feedback.
  • the additional loop operates to broaden the pulse width of the output signal.
  • the pulse width of the output signal is broadened so long as the additional loop is under operation, thereby preventing the frequent generation of the output signal having a pulse width smaller than the predetermined width.
  • the random change in pulse width of the input signal will not continue for a long time, particularly in the ignition system for internal combustion engines. It is, therefore, convenient that a timer circuit is incorporated to control an operation period of the additional loop. It is also convenient that the third circuit acts on the first circuit so as to vary the level of the feedback signal to broaden a pulse width of the output signal.
  • the pulse width of the output signal may be monitored by detecting the current flowing through the inductive load. This is because the current flowing through the inductive load is varied in accordance with the time constant thereof.
  • a pulse detector comprising an input terminal receiving an input pulse signal, a comparator having first and second input ends, a source of a reference voltage which is supplied to said second input end, the comparator comparing the input pulse signal supplied to the first input end with the reference voltage, a non-coincidence detector producing a pulse when the output of the comparator is not coincident with the input pulse signal, and a flip-flop being set and reset in responce to the output from the comparator and the non-coincidence detector.
  • the pulse detector produces a detection output when the input pulse signal is less than the reference voltage.
  • the input pulse signal is less than the reference voltage, normal output cannot be obtained and the consecutive outputs of the ignition system are not controlled normally.
  • the control of the ignition system can be easily recovered.
  • FIG. 1 is a block diagram showing a preferred embodiment of the present invention
  • FIG. 2 is a view showing waveforms of voltage and current at respective points of the circuit shown in FIG. 1 under normal operation;
  • FIG. 3 is a view showing waveforms of voltage and current at the respective points of the circuit without first and second circuits according to the present invention, in the case where the pulse width (period) of the input signal is disturbed randomly;
  • FIG. 4 is a view showing waveforms of voltage and current at the respective points of the circuit shown in FIG. 1, in the case where the pulse width of the input signal is disturbed randomly;
  • FIG. 5 is a circuit diagram showing a circuit configuration of the second circuit shown in FIG. 1;
  • FIG. 6 is a circuit diagram showing a circuit configuration of the third circuit shown in FIG. 1;
  • FIG. 7 is a circuit diagram showing another configuration of the second circuit
  • FIG. 8 is a circuit diagram showing still another configuration of the second circuit
  • FIG. 9 is a view showing waveforms of voltage at respective points of the circuit as shown in FIG. 7;
  • FIG. 10 is a view showing waveforms of voltage at respective points of the circuit as shown in FIG. 8.
  • FIG. 1 The configuration of the illustrated circuit, which is applied to an ignition system for internal combustion engines, will be described together with its operation represented by voltage and current waveforms shown in FIG. 2.
  • an input terminal 1 Supplied to an input terminal 1 is an input signal having a frequency (cycle period) in synchronism with the number of revolutions of the engine.
  • the input signal is obtained by detecting the revolution of the engine using a Hall sensor.
  • the duty ratio (the ratio of a high-level period to a low-level period in one cycle period) of the input signal is held constant regardless of the number of revolutions of engine. In other words, the pulse width of the input signal is varied in accordance with the number of revolutions of the engine.
  • the input signal is supplied to an input circuit 7 within a first circuit 2 which serves to make substantially constant the pulse width of an output signal therefrom over a variable frequency range of the input signal.
  • the input circuit 7 produces a wave-shaped signal Va (FIG. 2) of the input signal and may be composed of a comparator or a Schmitt triger circuit by way of example.
  • the signal Va is supplied to an integrator 8.
  • the integrator 8 includes a capacitor C 1 . This capacitor C 1 is charged with a current I 1 during the low-level period of the signal Va and discharged with a current I 2 ( ⁇ I 1 , I 1 >I 2 ) during the high-level period thereof.
  • the charge and discharge voltage Vb of the capacitor C 1 is supplied to a inverting (-) input terminal of an comparator 9 as the output voltage from the integrator 8.
  • a non-inverting (+) input terminal of the comparator 9 is supplied with a signal Vc from a feedback circuit 14 which is described later.
  • the comparison output between the signals Vb and Vc is supplied to one input end of an AND circuit 10 as a signal Vd.
  • the AND circuit has the other input end supplied with the signal Va.
  • the output Ve of the AND circuit 10 is fed back to the integrator 8 in order to make the charge starting level of the capacitor C 1 constant.
  • the signal Ve discharges the capacitor C 1 when it has a high level.
  • the output signal Vb from the integrator 8 has the waveform as shown in FIG. 2.
  • the AND circuit 10 produces the signal Ve shown in FIG. 2 in response to signals Va and Vd.
  • a driver 11 receives the signal Ve to produce a drive signal having voltage and current levels Ve' and Ie' (FIG. 2) enough to drive an output circuit 3.
  • the drive signal from the driver 11 is, thereinafter, referred to as signal Ve'.
  • the signal Ve' serves as an output signal of the first circuit 2.
  • the output circuit 3 is driven by the signal Ve' from the first circuit 2 to supply a current to an ignition coil 4 as a load.
  • the output circuit 3 has a Darlington-connected transistor Q 1 .
  • the transistor Q 1 is turned on when the signal Ve' takes a high level, and thereby a current flows through the coil 4. Accordingly, a current supply time to the ignition coil 4 is determined by the pulse width of the signal Ve'.
  • the current flowing therethrough is increased in accordance with the time constant which is determined by the inductance component and the resistance component of the coil 4. Eventually, the current I OUT flowing through the ignition coil 4 is varied as shown in FIG. 2.
  • a current detector 12 detects the current flowing through the ignition coil 4 and has a resistor R 1 .
  • the resistor R 1 is connected to the emitter of the transistor Q 1 . Since the emitter and collector currents thereof are almost equal to each other, the resistor R 1 converts the current I OUT flowing through the coil 4 into a voltage signal V f . Accordingly, the change in level of the signal V f is similar to that in the current I OUT , as shown in FIG. 2.
  • a current limiter 13 makes the ignition energy obtained from the ignition coil 4 constant in response to the signal Vf from the current detector 12.
  • the current limiter 13 detects the voltage across the resistor R 1 representing that the current I OUT reaches an I OUT1 level, and limits the drive current Ie' so as to maintain the I OUT1 level of the current I OUT flowing through the coil 4, as shown in FIG. 2.
  • the signal Vf from the current detector 12 is further supplied to the feedback circuit 14.
  • the feedback circuit 14 includes a capacitor C 2 and controls the charge and discharge of the capacitor C 2 in response to the signal Vf.
  • the capacitor C 2 is charged with the current I 3 when the current I OUT flowing through the ignition coil 4 (resistor R 1 ) is lower than the I OUT1 level, and discharged with the current I 4 ( ⁇ 1 3 , I 3 ⁇ I 4 ), when the current I out is maintained at the I OUT1 level.
  • the capacitor C 2 produces the charge/discharge voltage waveform represented by a signal Vc shown in FIG. 2.
  • the signal Vc is supplied to the non-inverting (+) input terminal of the comparator 9 as a negative feedback signal.
  • the feedback signal Vc is produced in accordance with the current I OUT flowing through the ignition coil 4, and the pulse width of the signal Ve' for determining a current supply time to the coil 4 is controlled by the feedback signal Vc and the signal Vb. Consequently, although FIG. 2 shows the case that the cycle period of the signal Va is constant (i.e., the number of revolutions of the engine is constant), the levels of the signals Vb and Vc are varied so as to obtain a substantially constant current supply time to the coil 4 (i.e., a substantially constant pulse width of the signal Ve') over the entire revolution range of the engine.
  • the circuit shown in FIG. 1 further comprises a second circuit 5 for monitoring the pulse width of the output signal (Ve') from the first circuit, and a third circuit 6 for forcibly changing the pulse width of the output signal (Ve') in response to the output of the second circuit 5.
  • the second circuit 5 receives the signal Vf from the current detector 12, and thereby monitors the pulse width of the signal Ve'. This is from the reason that the voltage level of the signal Vf is varied in accordance with the change in the current I OUT flowing through the ignition coil 4 and the current I OUT is controlled by the pulse width of the signal Ve'.
  • the current I OUT flowing through the ignition coil 4 may not reach the current level I OUT1 and may become smaller than a current level I OUT2 .
  • the second circuit 5 detects the above state in response to the voltage level of the signal Vf.
  • the maximum value of the current I OUT flowing through the coil is smaller than the current level I OUT2 , the ignition energy obtained from the coil 4 is not enough to achieve complete combustion of a mixture gas. This results in the air pollution.
  • the current I OUT reaches the predetermined current level I OUT1 . Accordingly, the second and third circuits 5 and 6 are not activated in this case.
  • FIG. 2 shows the current and voltage waveforms upon the normal operation in which the pulse width control of the output signal Ve' is effected in response to the input signal Va having a cycle period corresponding to the revolution of the engine.
  • the engine is not always under the smooth revolution.
  • the engine is started with the aid of a selfstarting motor.
  • the engine oil has very high viscosity.
  • the smooth revolution of the engine is not effected.
  • the cycle period (pulse width) of the signal supplied to the input terminal 1 is shortened or prolonged every few periods, as represented by the signal Va in FIG. 3. This results in the voltage and current waveforms at the respective points, as shown in FIG. 3, in the case that the second and third circuits 5 and 6 are not provided.
  • FIG. 3 there frequently occurs such a state that the current I OUT flowing through the ignition coil 4 does not reach the predetermined current level I OUT1 .
  • the signal Vb is produced from the capacitor C 1 in the integrator 8, which is charged with the current I 1 when the signal Va takes a low level and discharged with the current I 2 when the signal Va takes a high level. Therefore, the charged level of the capacitor C 1 is increased as the low-level period of the signal Va becomes long.
  • the signal Vc of the feedback circuit 14 is produced from the capacitor C 2 which is charged with the current I 3 when the current I OUT takes a value smaller than the current level I OUT1 , and discharged with the current I 4 , when the current I OUT takes the current level I OUT1 .
  • T 1 , T 2 shown in FIG. 3 when the pulse width (i.e.
  • the pulse width of the signal Ve becomes small, whereby the current I OUT does not reach the current level I OUT1 .
  • the charge of the capacitor C 1 is started from the reference level due to the feedback of the signal Vd from the AND circuit 9 to the integrator 8.
  • the output current I OUT has not reached the predetermined level I OUT1 , the capacitor C 2 continues to be charged with the current I 3 . Consequently, in the period T 3 , the pulse width of the signal Ve' is abruptly prolonged.
  • the signal Vc for controlling the pulse width of the signal Ve is obtained by the charge and discharge of the capacitor C 2 in response to the level of the output current I OUT , the signal Ve having a pulse width smaller than a predetermined width is produced frequently when the period (pulse width) of the signal Va is disturbed randomly.
  • the current I OUT flows in a very small amount.
  • the ignition energy from the ignition coil 4 becomes extremely small, so that a portion of the gas mixture is released directly to the atmosphere as exhaust gas after the incomplete combustion. This results in environmental pollution such as air contamination.
  • the circuit shown in FIG. 1 further includes the second circuit 5 and the third circuit 6.
  • the operation waveforms as shown in FIG. 4 is obtained even if there occurs a signal similar as the signal Va shown in FIG. 3.
  • the second circuit 5 includes a comparator 15.
  • the signal Vf from the current detector 12 in the first circuit 2 and the comparison voltage V DET from a reference voltage source 16 are supplied to the non-inverting (+) and inverting (-) input ends of the comparator 15, respectively.
  • the comparison voltage V DET is set at the same voltage as a voltage drop across the resistor R 1 obtained when the current I OUT flowing through the ignition coil 4 reaches the current level I OUT2 . Therefore, the comparator 15 produces a signal Vg having a high level when the current I OUT reaches the current level I OUT2 and a low level other than the above case, as shown in FIG. 4.
  • This signal Vg is supplied to the set terminal S of an S-R flip-flop (hereinafter, referred to as S-R F/F) 17 and further to one input end of a NOR circuit 19.
  • the other input end of the NOR circuit 19 is supplied with a signal Vh (see FIG. 4) which is obtained by inverting the signal Va from the input circuit 7 with an inverter 18.
  • the NOR circuit 19 outputs a NOR signal Vi in response to the signals Vg and Vh, as shown in FIG. 4.
  • This signal Vi is supplied to the reset terminal R of the S-R F/F 17.
  • a signal Vj from the Q output of the S-R F/F 17 and the signal Va from the input signal 7 are supplied to two input ends of a NOR circuit 20, respectively.
  • the NOR circuit 20 produces an output signal Vk as an output signal of the second circuit 5.
  • the third circuit 6 is activated in response to the pulse signal Vk generated from the second circuit 5.
  • the third circuit 6 comprises a C 2 level control circuit 21, a time-constant converter circuit 22 and a timer circuit 23, and these circuits are started to operate by the pulse signal Vk from the second circuit 5.
  • the C 2 level control circuit 21 has a function of holding the level of the capacitor C 2 in the feedback circuit 14 higher than that of the capacitor C 1 in the integrator 8 during the operation thereof.
  • the control circuit 21 monitors the charged level of the capacitor C 1 in the integrator 8 and controls the level of the capacitor C 2 at a level higher than the charged level of the capacitor C 1 by a constant voltage. As seen from FIG.
  • the level of the capacitor C 2 is held higher than that charged level. Since the output signal Ve of the AND circuit 10 is fed back to the integrator 8, the capacitor C 1 is discharged immediately when the signal Ve takes a high level. In response to this, the level of the capacitor C 2 is controlled by the time-constant converter circuit 22.
  • the time-constant converter circuit 22 has a function of converting the charge and discharge time-constants of the capacitor C 2 in the feedback circuit 14, and converts the charge current to the capacitor C 2 from I 3 to I 5 ( ⁇ I 3 ) and the discharge current of the capacitor C 2 from I 4 to I 6 ( ⁇ I 4 ), respectively.
  • the charge and discharge time-constants of the capacitor C 2 are converted by the converter 22, the charge and discharge periods thereof are controlled by the signal Vf from the current detector 12 in a similar manner to that as previously mentioned. Therefore, the capacitor C 2 is further charged with the current I 5 from the voltage level higher than that of the capacitor C 1 at the charge completion time point by the constant level, and then discharged with the current I 6 when the output current I OUT comes under the current limiting mode.
  • the signal Vc obtained from the feedback circuit 14 has the waveform shown in FIG. 4 and takes a level always higher than that of the signal Vb so long as the circuit 21 and the converter 22 are under operation.
  • the output signal Vd of the comparator 9 holds a high level, so that the pulse width of output signal Ve' from the first circuit 2 is made coincident with that of the signal Va.
  • the current I OUT flowing through the ignition coil 4 always reaches the predetermined level I OUT1 to generate the sufficient and constant ignition energy from the coil 4.
  • the timer circuit 23 in the third circuit 6 serves to set the operation time of the C 2 level control circuit 21 and the time-constant converter 22.
  • the pulse signal Vk makes the pulse width of the signal Ve' coincident with that of the input signal Va, so that the current limiting time of the output current I OUT is prolonged.
  • the prolongation of the current limiting time increases the power loss of the transistor Q 1 in the output circuit 3. Therefore, the operation of the third circuit 6 for a longer time is not preferred, because the thermal breakdown of the transistor Q 1 may occur.
  • the random disturbance of the period of the signal Va will not continue for a so long a time. For these reasons, the timer circuit 23 is provided.
  • the timer circuit 23 starts clocking in response to the signal Vk and then generates two signals V l and Vm. These signals V l and Vm are not generated simultaneously.
  • the signal V l is generated before the signal Vm, as shown in FIG. 4.
  • the C 2 level control circuit 21 stops its operation.
  • the control of the charge and discharge of the capacitor C 2 is carried out only by the converter 22, and the charge and discharge times thereof are determined by the level of the output current I OUT . This causes the pulse width of the output signal Ve' to be shortened gradually.
  • the time-constant converter 22 also stops its operation.
  • the level of the capacitor C 2 is hence controlled by the charge/discharge time-constant of the feedback circuit 14 after the period T 13 . That is, the pulse width of the signal Ve' is now controlled by the negative feedback loop in the first circuit 2.
  • the times when those signals V l and Vm are generated are preferably set at 250 to 500 msec and 550 to 1100 msec, respectively, after the generation of the pulse signal Vk.
  • the third circuit 6 operates to control the signal Vc from the feedback circuit 14 at a level higher than the signal Vb from the integrator 8. As a result, the frequent occurrence of such a state as shown in FIG. 3 where the output current I OUT flows in a very small amount only is prevented.
  • the third circuit 5 may be modified to directly act on the comparator 9 so as to control the output signal Vd at a high level for a predetermined time.
  • the first, second and third circuits 2, 5 and 6 are fabricated on one semiconductor substrate as an integrated circuit device, except for the capacitors C 1 , C 2 and the resistor R 1 .
  • FIG. 5 shows one example of the concrete circuit configurations of the output circuit 3 and the second circuit 5, in which the same components as those in FIG. 1 are denoted by the same numerals.
  • the signal Ve' from the driver 11 is supplied to base of the Darligntonconnected transistor Q 1 , the collector of which is connected to a power supply terminal 24 through a primary winding 4-1 of the ignition coil 4.
  • the emitter of the transistor Q is grounded through the current detection resistor R 1 .
  • the signal Vf obtained in the form of a voltage drop across the resistor R 1 is supplied to base of a transistor Q 2 in the comparator 15.
  • the transistor Q 2 constitutes a differential amplifier together with a transistor Q 3 which has its base supplied with the comparison voltage V DET from the reference voltage source 16.
  • Transistors Q 4 , Q 5 serve as an active load and a resistor R 2 serves as a current source.
  • the collector output of the transistor Q 2 is supplied to an emitter-follower amplifier comprising a transistor Q 6 and resistors R 3 and R 4 .
  • the output of the transistor Q 6 is supplied to an inverting amplifier comprising a transistor Q 7 and a resistor R 5 .
  • Those components constitute a comparator 15.
  • the S-R flip-flop (F/F) 17 comprises two pairs of transistors Q 8 , Q 9 and Q 10 , Q 11 , each pair having emitters and collectors commonly connected to each other.
  • Base of the transistor Q 8 serves as the set terminal S supplied with the signal Vg through a resistor R 6 .
  • Base of the transistor Q 9 is connected to the collector joint of the transistors Q 10 and Q 11 through a resistor R 9 .
  • Base of the transistor Q 10 is connected to the collector joint of the transistors Q 8 and Q 9 through a resistor R 8 .
  • Resistors R 7 and R 10 serve as collector resistors.
  • Base of the transistor Q 11 serves as the reset terminal R. The output Q is obtained from collector thereof.
  • the signal Vg is also supplied to the base of a transistor Q 12 through a resistor R 11 .
  • the transistor Q 12 constitutes a NOR circuit 19 together with a transistor Q 13 , collectors of the transistors Q 12 and Q 13 being commonly connected to the reset terminal R of the S-R F/F 17 (i.e., the base of the transistor Q 11 ).
  • a resistor R 13 is a collector load.
  • the base of the transistor Q 13 is supplied through a resistor R 12 with the signal Vh which is obtained by inverting the signal Va through the inverter 18 comprising a transistor Q 16 and resistors R 18 and R 19 .
  • the base of the transistor Q 8 (the set terminal S) is at a high level and the base of the transistor Q 11 (the reset terminal R) is at a low level. Accordingly, the transistors Q 8 and Q 9 are turned on and the transistors Q 10 and Q 11 are turned off. As a result, the signal Vj takes a high level.
  • the signals Vg and Vh have a low level
  • the set terminal S takes a low level
  • the reset terminal R takes a high level.
  • the transistors Q 8 and Q 9 are turned off and the transistors Q 10 and Q 11 are turned on. As a result, the signal Vj becomes a low level.
  • the signal Vj is supplied to the base of a transistor Q 14 through a resistor R 14 .
  • the transistor Q 14 constitutes the NOR circuit 20 together with a transistor Q 15 .
  • the transistors Q 14 and Q 15 have collectors commonly connected.
  • the base of the transistor Q 15 is supplied with the signal Va through a resistor R 16 .
  • a load resistor R 17 is connected to collectors of the transistors Q 14 and Q 15 .
  • the signal Vk to the third circuit 23 is taken from the collector joint of the transistors Q 14 and Q 15 .
  • the signals Vj and Va are a low level, the transistors Q 14 and Q 15 are turned off, resulting in the pulse signal Vk taking a high level, as shown in FIG. 4.
  • a stabilized voltage Vcc is supplied to the circuits 15 to 20 from a stabilized voltage supply terminal 25.
  • FIG. 6 includes the feedback circuit 14 and integrator 8 to describe the operation of the third circuit 6.
  • an S-R flip-flop (F/F) 36 is in the reset state. Accordingly, its output Q takes a low level and its inverted output Q takes a high level.
  • the high-level of the inverted output Q holds the output of a three-input NOR circuit 38 at a low level, so that another S-R flip-flop (F/F) 37 is in the reset state.
  • the inverted output Q of the S-R F/F 36 is also supplied to the base of a transistor Q 59 through a resistor R 62 to turn on the transistor Q 59 . Accordingly, a current I 7 from a constant-current source 33 flows through the transistor Q 59 and a capacitor C 3 is not charged. The capacitor C 3 constitutes the timer circuit 23.
  • the inverted output Q of the S-R F/F 36 is further supplied to the base of a transistor Q 33 through a resistor R 35 to turn on the transistor Q 33 and off a transistor Q 34 .
  • Resistors R 36 and R 37 are collector resistors.
  • a high level signal at the collector of the transistor Q 34 is supplied to the bases of transistors Q 45 and Q 35 through resistors R 39 and R 40 , respectively.
  • transistors Q 45 and Q 35 are turned on to hold the emitter potential of the transistors Q 44 and the emitter potentials of the transistors Q 36 and Q 37 at a high level through resistors R 54 , R 53 and R 38 , R 41 , respectively. As a result, the transistors Q 44 , Q 36 and Q 37 are cut off.
  • the low-level of the output Q of the S-R F/F 36 is supplied to the base of a transistor Q 31 through a resistor R 33 . Therefore, the transistor Q 31 is cut off and a transistor Q 32 is turned on.
  • Resistors R 32 and R 34 are collector resistors thereof.
  • Low-level collector output of the transistor Q 32 is supplied to bases of transistors Q 40 and Q 43 through resistors R 47 and R 48 , respectively. As a consequence, these transistors Q 40 , Q 43 are cut off, thereby activating transistors Q 38 , Q 39 and Q 42 .
  • the low-level of the output Q of the S-R F/F 37 is supplied through a resistor R 30 to a transistor Q 30 to turn off this transistor.
  • the high-level of the inverted output Q of F/F 37 is supplied to the base of a transistor Q 58 through a resistor R 61 , thus turning on the transistor Q 58 . Therefore, a current flows through a diode-connected transistor Q 57 through a resistor R 60 to bring a transistor Q 56 having a collector resistor R 59 into a saturation state. Since the collector of a transistor Q 55 is connected to the collector of the transistor Q 56 , the transistor Q 55 comes into the off state when the transistor Q 56 is saturated. As a result, a transistor Q 49 is held in the off state, thus deactivating transistors Q 50 to Q 54 which constitute a differential amplifier having the transistor Q 49 as a current source.
  • the transistors Q 38 , Q 39 and Q 42 become operable to produce the feedback signal Vc.
  • the transistors Q 38 and Q 39 are connected to each other in a differential fashion.
  • the base of transistor Q 39 is supplied with a bias voltage through resistors R 55 , R 56 and a diode-connected transistor Q 46 .
  • the base of the transistor Q 38 is supplied through a diode D 5 with a voltage across three diodes D 1 to D 3 connected in series. Since a current flows through the diodes D 1 to D 3 , a resistor R 31 and a switch 27, the diodes D 1 to D 3 produces forward voltage drops only when the switch 27 is closed. The switch 27 is opened and closed in response to the signal Vf from the current detector 12.
  • the switch 27 is opened when the current I OUT flowing through the ignition coil 4 takes the current level I OUT1 , and closed except for the above state.
  • the switch 27 is electronically constituted by the use of a transistor element.
  • the diodes D 1 to D 3 are biased. Consequently the voltage having a level of 2 ⁇ V F (V F representing a forward voltage drop across a diode) is supplied to the base of the transistor Q 38 .
  • the base of the transistor Q 39 is supplied with the bias voltage having a level almost equal to V F by the diode-connected transistor Q 46 . Therefore, the transistor Q 39 is cut off and the transistor Q 38 is turned on.
  • the collector of the transistor Q 39 is connected to the capacitor C 2 through a resistor R 43 , so that the capacitor C 2 is not discharged in this state.
  • the transistor Q 42 is in a conduction state, since it is biased by the diode-connected transistor Q 46 .
  • a transistor Q 42 has two collectors, in which its first collector is connected to the base to constitute a current mirror circuit. Since the transistor Q 42 is connected to the junction point between the first collector and the base of the transistor Q 41 , the current flowing through the transistor Q 42 is obtained from the second collector of the transistor Q 41 .
  • the second collector of the transistor is connected to the capacitor C 2 through a resistor R 43 . Accordingly, the capacitor C 2 is charged with the current I 1 flowing through the transistor Q 42 , when the transistor Q 39 is in an off-state.
  • the switch 27 When the output current I OUT reaches the current level I OUT1 and it comes into the current limiting state, the switch 27 is opened to turn the transistor Q 38 off. As a result, the transistor Q 39 is turned on to discharge the capacitor C 2 with the current I 2 flowing through the transistor Q 39 .
  • the voltage across the capacitor C 2 are supplied to the non-inverting (+) input terminal of the comparator 9 as the feedback signal Vc through an emitter-follower transistor Q 47 having an active load composed of a transistor Q 48 and a resistor R 57 .
  • the F/F 36 When the signal V k having a high level (see FIG. 4) is supplied from the second circuit 5 to the F/F 36, the F/F 36 is in the set state, so that its outputs Q and Q take a high level and a low level, respectively. Therefore, the transistors Q 38 , Q 39 and Q 42 are cut off, and the transistors Q 36 , Q 37 and Q 44 are turned on.
  • the low-level of the inverted output Q of the F/F 36 turns OFF the transistor Q 59 , so that the capacitor C 3 starts to be charged with the current I 7 from the constant-current source 33 through the resistor R 63 . That is, the timer circuit starts its clocking.
  • the low-level of the inverted output Q of the F/F 36 is also fed to the first input of the NOR circuit 38.
  • the second input of the NOR circuit 38 is supplied with the output of a comparator 35 which compares the charged level of the capacitor C 3 with a reference voltage V REF1 from a voltage source 40. Since the capacitor C 3 has just started to be charged, the output of the comparator 35 is then at a low level.
  • the third input of the NOR circuit 38 is supplied with the signal Va from the input circuit 7. The signal Va is at a low level just when the pulse signal V k is generated from the second circuit 5. Accordingly, the output of the NOR circuit 38 takes a high level, thereby turning the F/F 37 into the set state.
  • the set state of the F/F 37 turns the transistor Q 58 off, since the transistor Q 56 receives the Q output of the F/F 37. Consequently, the transistors Q 57 and Q 56 are also cut off, and the transistors Q 55 and Q 49 are turned on the activate the differential amplifier composed of the transistors Q 50 to Q 54 .
  • FIG. 6 also shows the schematic configuration of the integrator 8 in which a constant-current source 28 feeding the current I 1 , a switch 29, a resistor R 58 and the capacitor C 1 are connected in series.
  • a series circuit of a switch 30 and a constant-current source 32 feeding the current I 2 as well as a switch 31 are connected in parallel with a series circuit of the resistor R 58 and the capacitor C 1 , respectively.
  • the switches 29 and 30 are controlled in opening and closing thereof in response to the signal Va.
  • the switch 29 is closed (the switch 30 being opened) with a low level of the signal Va
  • the switch 30 is closed (the switch 29 being opened) with a high level of the signal Va.
  • the switch 31 is controlled by the output Ve of the AND circuit 10 and closed with a high level of the signal Ve.
  • the voltage across the capacitor C 1 serves a the signal Vb, as shown in FIG. 4.
  • the differential amplifier comprising the transistors Q 50 to Q 54 is activated.
  • the voltage level across the capacitor C 1 is supplied to the base of the transistor Q 50
  • the voltage level across the capacitor C 2 is supplied to the base of the transistor Q 51 through a diode D 6 . Therefore, the transistor Q 54 discharges the capacitor C 2 to make the base potentials of the transistors Q 50 and Q 51 equal to each other.
  • the capacitor C 1 is at the reference potential due to the on-state of the switch 31.
  • the capacitor C 2 is discharged by the transistor Q 54 to have a level higher than the reference potential by the forward voltage drop V F of the diode D 6 .
  • the signal Vk rises up to a high level
  • the level of the signal Vc falls down.
  • the signals Va and Ve are inverted to a low level, and therefore, the switch 29 is closed and the switches 31, 32 are opened. Consequently, the capacitor C 1 is charged with the current I 1 .
  • the high-level Q output of the F/F 37 is supplied to the transistor Q 30 to turn it on.
  • the collector of the transistor Q 30 is connected to the junction point between the base and the first collector of the transistor Q 41 . Therefore, the current fed from the second collector of the transistor Q 41 is increased significantly. Since the signal Va is at a low level, the switch 27 is closed. Also, the transistors Q 36 , Q 37 and Q 44 are under operation due to the output Q of the F/F 36. Therefore, the capacitor C 2 is charged with the increased current fed from the second collector of the transistor Q 41 . Further, the increased current is larger than the current I 1 from the constant-current source 28.
  • the charged levels of the capacitors C 1 and C 2 are compared with each other by the transistors Q 50 to Q 54 , and therefore, a part of the current from the second collector of the transistor Q 41 flows through the transistor Q 54 to make the base potentials of the transistors Q 50 and Q 51 equal to each other.
  • the capacitor C 2 is charged in such a way that its level becomes always higher than that of the capacitor C 1 by the forward voltage drop across the diode D 6 .
  • the switches 29 and 31 are, of course, composed of a semiconductor switch.
  • the switch 29 When the input signal Va is inverted from a low level to a high level, the switch 29 is opened and the switch 30 is closed. At this time point, the signal Ve at a high level is derived from the AND circuit 10, so that the switch 31 is closed to discharge the capacitor C 1 immediately.
  • the third input of the NOR circuit 38 takes a high level. Accordingly, a low-level signal is supplied to the set terminal S of F/F 37, and further the reset terminal R thereof is supplied with the signal Va at a high level. As a result, the F/F 37 comes into the reset state.
  • the high-level of the inverted output Q of the F/F 37 turns on the transistors Q 56 and Q 57 and cuts off the transistors Q 49 to Q 55 . This stops the level comparison operation by the transistors Q 50 to Q 54 . Further, the low-level of the output Q upon of the F/F 37 cuts off the transistor Q 30 , thereby obtaining the current I 3 from the second collector of the transistor Q 41 . At this time, since the current I OUT flowing through the ignition coil 4 is not under the current limiting state, the switch 27 remains closed. Therefore, the transistor Q 37 is in the off-state and Q 36 and Q 44 are in the on-state.
  • the capacitor C 2 Since the current I 3 flowing through the transistor Q 44 is supplied to the junction point between the first collector and the base of the transistor Q 41 , the capacitor C 2 is further charged with the current I 3 .
  • the output current I OUT reaches the current level I 1 to change the switch 27 to an open-state, the transistor Q 37 is turned on and Q 36 and Q 44 are cut off.
  • the capacitor C 2 is then discharged with the current I 4 flowing through the transistor Q 37 .
  • the currents I 1 and I 2 are larger than the currents I 3 and I 4 , respectively. That is, the charge/discharge time-constant of the capacitor C 2 is converted.
  • a comparator 34 Since the reference voltage V REF2 from a voltage source 39 is set higher than V REF1 , a comparator 34 does not generate the signal Vm of a high level simultaneously with the signal V l . Accordingly, the F/F 36 remains in the set state and the transistors Q 36 , Q 37 and Q 44 are still activated. In other words, the time-constant converting operation is still continued. Since the C 2 level control circuit 2, is under the stopped state in its operation, the voltage level of the feedback signal Vc is gradually lowered due to the negative feedback operation of the first circuit 2, as shown in FIG. 4.
  • the charging to the capacitor C 3 proceeds further.
  • the comparator 34 When the charged level of the capacitor C 3 exceeds the reference voltage V REF2 from the voltage source 39, the comparator 34 generates the high-level signal Vm (see FIG. 4).
  • the F/F 36 comes into the reset state.
  • the transistors Q 36 , Q 37 and Q 44 are cut off and Q 38 , Q 39 and Q 42 are activated.
  • the charge and discharge of the capacitor C 2 with the currents I 1 and I 2 are started to provide the normal charge/discharge time-constant.
  • the F/Fs 36 and 37, NOR circuit 38 and the comparators 34 and 35 in FIG. 6 can be constituted by the circuits similar to those of the F/F, NOR circuit and comparator shown in FIG. 5.
  • the feedback signal Vc is controlled to has a level higher than that of the signal Vb in response to the pulse signal V k .
  • the pulse width of the output signal Ve' is coincident with that of the input signal Va. The frequent generation of the undesired output signal Ve' is prevented.
  • the time-constant converted circuit 22 in the third circuit 6 may be omitted.
  • FIGS. 7 and 8 show other embodiments of the second circuit 5.
  • the embodiment illustrated in FIG. 7 employs two exclusive logical sum (EX-OR) circuits 40 and 41 and an S-R flip-flop (F/F) 41 in addition to the comparator 15 and the voltage source 16 in order to utilize the signal Ve' instead of the signal Va.
  • the signal Ve' is supplied to one input of the EX-OR circuit 40, and the other input thereof is supplied with the output Vg of the comparator 15 obtained by comparing the signal Vf with the comparison voltage V DET .
  • the output Vg of the comparator 15 is also supplied to the reset terminal R of the F/F 41, and the set terminal S thereof is supplied with the output Vn of the Ex-OR circuit 40.
  • the Q output of the F/F 41 and the output Vn of the EX-OR circuit 40 are supplied to two inputs of the EX-OR circuit 42, the output of which is taken out as the signal Vk.
  • the embodiment illustrated in FIG. 8 is intended to generate the signal Vk by utilizing only the signal Vf from the current detector 12. It includes a comparator 43, two exclusive logical sum (EX-OR) circuits 44 and 46, and an S-R flip-flop (F/F) 45 in addition to the comparator 15 and the reference voltage source 16.
  • the signal Vf is compared with the reference voltage V DET by the comparator 15 and further supplied to the non-inverting (+) input end of the comparator 43.
  • the inverting (-) input terminal of the comparator 43 is grounded.
  • the outputs Vg and Vp from the comparators 15 and 43 are supplied to the EX-OR circuit 44.
  • the output Vg of the EX-OR circuit 44 is supplied to the set terminal S of the F/F 45 and further to one input of the EX-OR circuit 46.
  • the output Vg of the comparator 15 is also supplied to the reset terminal R of the F/F 45, the Q output of which is supplied to the other input of the EX-OR circuit 46.
  • the present invention provides a circuit suitable for the ignition system for internal combustion engines.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Combustion & Propulsion (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Ignition Installations For Internal Combustion Engines (AREA)
  • Manipulation Of Pulses (AREA)
US06/590,662 1983-03-17 1984-03-19 Control circuit for controlling output pulse width using negative feedback signal Expired - Fee Related US4552118A (en)

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JP58044734A JPS59171219A (ja) 1983-03-17 1983-03-17 レベル検出回路

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Cited By (24)

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Publication number Priority date Publication date Assignee Title
US4674467A (en) * 1985-04-10 1987-06-23 Nippon Soken, Inc. Apparatus for controlling ignition in internal combustion engine
US4734842A (en) * 1986-05-20 1988-03-29 Siemens Aktiengesellschaft Signal converter
US4739743A (en) * 1986-01-28 1988-04-26 Mitsubishi Denki Kabushiki Kaisha Ignition control system for internal combustion engine
EP0280631A1 (de) * 1987-02-26 1988-08-31 Sgs-Thomson Microelectronics S.A. Zündanlage
US4848304A (en) * 1986-01-30 1989-07-18 Mitsubishi Denki Kabushiki Kaisha Ignition control device for internal combustion engine
EP0332728A1 (de) * 1988-03-17 1989-09-20 Robert Bosch Gmbh Steuerungskreis für ein Zündsystem mit Transistoren
US4977883A (en) * 1989-03-20 1990-12-18 Mitsubishi Denki Kabushiki Kaisha Ignition control apparatus for an internal combustion engine
US5213080A (en) * 1992-07-10 1993-05-25 Gas Research Institute Ignition timing control
EP0632199A3 (de) * 1993-07-02 1995-07-19 Daimler Benz Ag Verfahren zum Ansteuern einer Zündspule.
US5939797A (en) * 1996-11-18 1999-08-17 Honda Giken Kogyo Kabushiki Kaisha Ignition control system
EP1103720A3 (de) * 1999-11-29 2002-06-05 Volkswagen Aktiengesellschaft Verfahren und Vorrichtung zur Stromregelung einer Zündanlage für einen Verbrennungsmotor
US20070255517A1 (en) * 2006-05-01 2007-11-01 Ibm Corporation Method and apparatus for on-chip duty cycle measurement
US20070252629A1 (en) * 2006-05-01 2007-11-01 Ibm Corporation Method and apparatus for correcting the duty cycle of a digital signal
US20070266285A1 (en) * 2006-05-01 2007-11-15 Ibm Corporation Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode
WO2007132015A1 (en) * 2006-05-16 2007-11-22 International Business Machines Corporation Method and apparatus for measuring the duty cycle or relative duty cycle of a digital signal
US20070271051A1 (en) * 2006-05-01 2007-11-22 Ibm Corporation Method and apparatus for measuring the duty cycle of a digital signal
US20090112555A1 (en) * 2006-05-01 2009-04-30 International Business Machines Corporation Design Structure For A Duty Cycle Measurement Apparatus That Operates In A Calibration Mode And A Test Mode
US20090125857A1 (en) * 2007-11-12 2009-05-14 International Business Machines Corporation Design Structure for an Absolute Duty Cycle Measurement Circuit
US20090128133A1 (en) * 2007-11-20 2009-05-21 Boerstler David W Duty Cycle Measurement Method and Apparatus for Various Signals Throughout an Integrated Circuit Device
US20090138834A1 (en) * 2007-11-20 2009-05-28 International Business Machines Corporation Structure for a Duty Cycle Measurement Circuit
US7904264B2 (en) 2007-11-12 2011-03-08 International Business Machines Corporation Absolute duty cycle measurement
US20110148439A1 (en) * 2009-12-22 2011-06-23 Sanyo Electric Co., Ltd. Capacitance discrimination circuit and touch switch equipped with the same
US9006988B2 (en) 2010-10-22 2015-04-14 Delta Electronics, Inc. Method of controlling ignition circuit and ignition circuit using the same
CN111448380A (zh) * 2017-12-15 2020-07-24 罗伯特·博世有限公司 用于确定内燃机的曲轴的旋转方向的方法和设备

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DE3111856C2 (de) * 1981-03-26 1992-10-08 Telefunken electronic GmbH, 7100 Heilbronn Elektronisch geregeltes Zündsystem für eine Brennkraftmaschine
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US4153032A (en) * 1976-07-28 1979-05-08 Ducellier & Cie Ignition control device with monostable elements for providing a constant energy spark
US4174696A (en) * 1977-01-19 1979-11-20 Robert Bosch Gmbh Ignition system
US4248195A (en) * 1978-01-27 1981-02-03 Robert Bosch Gmbh Apparatus for controlling the duty factor of sequence of cyclically occurring pulses controlling flow through an impedance
US4298941A (en) * 1979-02-19 1981-11-03 Hitachi, Ltd. Method for controlling an internal combustion engine

Cited By (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4674467A (en) * 1985-04-10 1987-06-23 Nippon Soken, Inc. Apparatus for controlling ignition in internal combustion engine
US4739743A (en) * 1986-01-28 1988-04-26 Mitsubishi Denki Kabushiki Kaisha Ignition control system for internal combustion engine
US4848304A (en) * 1986-01-30 1989-07-18 Mitsubishi Denki Kabushiki Kaisha Ignition control device for internal combustion engine
US4734842A (en) * 1986-05-20 1988-03-29 Siemens Aktiengesellschaft Signal converter
EP0280631A1 (de) * 1987-02-26 1988-08-31 Sgs-Thomson Microelectronics S.A. Zündanlage
FR2611814A1 (fr) * 1987-02-26 1988-09-09 Thomson Semiconducteurs Dispositif d'allumage automobile
EP0332728A1 (de) * 1988-03-17 1989-09-20 Robert Bosch Gmbh Steuerungskreis für ein Zündsystem mit Transistoren
US4977883A (en) * 1989-03-20 1990-12-18 Mitsubishi Denki Kabushiki Kaisha Ignition control apparatus for an internal combustion engine
US5213080A (en) * 1992-07-10 1993-05-25 Gas Research Institute Ignition timing control
EP0632199A3 (de) * 1993-07-02 1995-07-19 Daimler Benz Ag Verfahren zum Ansteuern einer Zündspule.
US5939797A (en) * 1996-11-18 1999-08-17 Honda Giken Kogyo Kabushiki Kaisha Ignition control system
CN1067143C (zh) * 1996-11-18 2001-06-13 本田技研工业株式会社 点火控制系统
EP1103720A3 (de) * 1999-11-29 2002-06-05 Volkswagen Aktiengesellschaft Verfahren und Vorrichtung zur Stromregelung einer Zündanlage für einen Verbrennungsmotor
US7333905B2 (en) 2006-05-01 2008-02-19 International Business Machines Corporation Method and apparatus for measuring the duty cycle of a digital signal
US20070255517A1 (en) * 2006-05-01 2007-11-01 Ibm Corporation Method and apparatus for on-chip duty cycle measurement
US20070266285A1 (en) * 2006-05-01 2007-11-15 Ibm Corporation Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode
US7595675B2 (en) 2006-05-01 2009-09-29 International Business Machines Corporation Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode
US20070271068A1 (en) * 2006-05-01 2007-11-22 Ibm Corporation Method and Apparatus for Measuring the Relative Duty Cycle of a Clock Signal
US20070271051A1 (en) * 2006-05-01 2007-11-22 Ibm Corporation Method and apparatus for measuring the duty cycle of a digital signal
US7330061B2 (en) 2006-05-01 2008-02-12 International Business Machines Corporation Method and apparatus for correcting the duty cycle of a digital signal
US7617059B2 (en) 2006-05-01 2009-11-10 International Business Machines Corporation Method and apparatus for measuring the duty cycle of a digital signal
US7363178B2 (en) 2006-05-01 2008-04-22 International Business Machines Corporation Method and apparatus for measuring the relative duty cycle of a clock signal
US20080174345A1 (en) * 2006-05-01 2008-07-24 Ibm Corporation Method and apparatus for measuring the duty cycle of a digital signal
US7420400B2 (en) 2006-05-01 2008-09-02 International Business Machines Corporation Method and apparatus for on-chip duty cycle measurement
US20090112555A1 (en) * 2006-05-01 2009-04-30 International Business Machines Corporation Design Structure For A Duty Cycle Measurement Apparatus That Operates In A Calibration Mode And A Test Mode
US7646177B2 (en) 2006-05-01 2010-01-12 International Business Machines Corporation Design structure for a duty cycle measurement apparatus that operates in a calibration mode and a test mode
US20070252629A1 (en) * 2006-05-01 2007-11-01 Ibm Corporation Method and apparatus for correcting the duty cycle of a digital signal
CN101410719B (zh) * 2006-05-16 2012-01-18 国际商业机器公司 用于测量数字信号的占空比或相对占空比的方法和设备
WO2007132015A1 (en) * 2006-05-16 2007-11-22 International Business Machines Corporation Method and apparatus for measuring the duty cycle or relative duty cycle of a digital signal
US7904264B2 (en) 2007-11-12 2011-03-08 International Business Machines Corporation Absolute duty cycle measurement
US8032850B2 (en) 2007-11-12 2011-10-04 International Business Machines Corporation Structure for an absolute duty cycle measurement circuit
US20090125857A1 (en) * 2007-11-12 2009-05-14 International Business Machines Corporation Design Structure for an Absolute Duty Cycle Measurement Circuit
US20090138834A1 (en) * 2007-11-20 2009-05-28 International Business Machines Corporation Structure for a Duty Cycle Measurement Circuit
US7895005B2 (en) 2007-11-20 2011-02-22 International Business Machines Corporation Duty cycle measurement for various signals throughout an integrated circuit device
US20090128133A1 (en) * 2007-11-20 2009-05-21 Boerstler David W Duty Cycle Measurement Method and Apparatus for Various Signals Throughout an Integrated Circuit Device
US7917318B2 (en) 2007-11-20 2011-03-29 International Business Machines Corporation Structure for a duty cycle measurement circuit
US20110148439A1 (en) * 2009-12-22 2011-06-23 Sanyo Electric Co., Ltd. Capacitance discrimination circuit and touch switch equipped with the same
US8552747B2 (en) * 2009-12-22 2013-10-08 Semiconductor Components Industries, Llc Capacitance discrimination circuit and touch switch equipped with the same
US9006988B2 (en) 2010-10-22 2015-04-14 Delta Electronics, Inc. Method of controlling ignition circuit and ignition circuit using the same
CN111448380A (zh) * 2017-12-15 2020-07-24 罗伯特·博世有限公司 用于确定内燃机的曲轴的旋转方向的方法和设备

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DE3410020C2 (de) 1986-12-11
DE3410020A1 (de) 1984-10-25
JPS59171219A (ja) 1984-09-27

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