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US20220384409A1 - Semiconductor devices and methods for manufacturing the same - Google Patents

Semiconductor devices and methods for manufacturing the same Download PDF

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Publication number
US20220384409A1
US20220384409A1 US17/826,791 US202217826791A US2022384409A1 US 20220384409 A1 US20220384409 A1 US 20220384409A1 US 202217826791 A US202217826791 A US 202217826791A US 2022384409 A1 US2022384409 A1 US 2022384409A1
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Prior art keywords
chip
eic
pic
substrate
semiconductor device
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US17/826,791
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English (en)
Inventor
Bo Peng
Huaiyu Meng
Yichen Shen
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Hangzhou Guangzhiyuan Technology Co Ltd
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Hangzhou Guangzhiyuan Technology Co Ltd
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Assigned to Hangzhou Guangzhiyuan Technology Co., Ltd. reassignment Hangzhou Guangzhiyuan Technology Co., Ltd. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PENG, BO, SHEN, Yichen, MENG, Huaiyu
Publication of US20220384409A1 publication Critical patent/US20220384409A1/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06E—OPTICAL COMPUTING DEVICES; COMPUTING DEVICES USING OTHER RADIATIONS WITH SIMILAR PROPERTIES
    • G06E3/00—Devices not provided for in group G06E1/00, e.g. for processing analogue or hybrid data
    • G06E3/001—Analogue devices in which mathematical operations are carried out with the aid of optical or electro-optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H10W20/20—
    • H10W70/635—
    • H10W70/65—
    • H10W72/20—
    • H10W90/00—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H10W70/60—
    • H10W70/655—
    • H10W72/0198—
    • H10W72/07254—
    • H10W72/241—
    • H10W72/247—
    • H10W72/248—
    • H10W72/252—
    • H10W72/29—
    • H10W72/823—
    • H10W72/853—
    • H10W72/874—
    • H10W72/90—
    • H10W72/9413—
    • H10W72/942—
    • H10W74/00—
    • H10W74/016—
    • H10W74/141—
    • H10W74/142—
    • H10W90/20—
    • H10W90/22—
    • H10W90/722—
    • H10W90/724—

Definitions

  • the present invention relates to the field of photonic integrated circuits, and more particularly, to a semiconductor device and a manufacturing method thereof.
  • photonic computing uses light as the carrier of information, and realizes light transmission, processing, and calculation through optical devices/chips.
  • an electronic integrated circuit (EIC) chip and a photonic integrated circuit (PIC) chip need to be electrically connected to each other.
  • the wirings for connecting the two chips are long. Due to the resistance in the wiring, the voltage drop caused by the current flowing through the wiring is not negligible and leads to extra power consumption. Excessive voltage drop may also cause the system to fail to work properly.
  • both EIC chip and PIC chip in order to realize the transmission of a large amount of data and signals and the electrical connection, both EIC chip and PIC chip have a plurality of connection points and a plurality of wirings corresponding thereto, which further leads to undesirable voltage drop.
  • the PIC chip sometimes needs to be optically coupled with external devices, which greatly limits the overall integration of a semiconductor device.
  • the invention provides a semiconductor device and a manufacturing method thereof, which can effectively suppress the voltage drop, optimize the electrical connection between a PIC chip and an EIC chip, and optimize the package size.
  • embodiments of the present invention provide a semiconductor device comprising a substrate; a PIC chip; an EIC chip disposed between the PIC chip and the substrate; wherein the PIC chip is electrically connected to the EIC chip.
  • the PIC chip includes a PIC wiring structure
  • the EIC chip includes an EIC wiring structure
  • the semiconductor device further comprises an electrical connection path from the PIC chip to the substrate, which successively passes through the PIC wiring structure and the EIC wiring structure.
  • the semiconductor device further comprises a packaging material disposed in at least a portion of the periphery of the EIC chip, a via conductive structure disposed in the packaging material, and an electrical connection path from the PIC chip to the substrate. Wherein the electrical connection path passes through the via conductive structure.
  • the semiconductor device includes at least one structure of a PIC rewiring structure, a first bonding structure, a first EIC rewiring structure, a second EIC rewiring structure, a via conductive structure, and a second bonding structure, wherein the at least one structure is configured such that:
  • the electrical connection path from the PIC wiring structure to the EIC wiring structure successively passes through at least one of the PIC rewiring structure, the first bonding structure, the first EIC rewiring structure, and/or
  • the electrical connection path from the EIC wiring structure to a substrate wiring structure successively passes through at least one of the second EIC rewiring structure, the via conductive structure, and the second bonding structure.
  • the semiconductor device comprises at least two EIC chips including a first EIC chip and a second EIC chip, a packaging material disposed between the first EIC chip and the second EIC chip, and at least one via conductive structure disposed in the packaging material.
  • two or more via conductive structures are disposed around the first EIC chip, among which at least one via conductive structure whose wiring distance from the first EIC chip is not the farthest is connected to the first EIC chip.
  • the semiconductor device comprises a first bonding structure for connecting the EIC chip to the PIC chip and a connection structure for connecting the EIC chip to the substrate.
  • the connection structure includes a first segment electrically connected to the first bond structure, a second segment electrically connected to the first segment, and a second bonding structure for connecting the second segment to the substrate.
  • the first segment of the connection structure extends laterally from the connection point of the first bond structure on the EIC chip and beyond the EIC chip.
  • the second segment of the connecting structure extends longitudinally from the first segment of the connecting structure toward the substrate and terminates at the second bonding structure.
  • the semiconductor device further comprises a packaging material disposed in at least a portion of the periphery of the EIC chip surrounding the second segment of the connecting structure.
  • the second segment of the connection structure includes a via conductive structure formed in the packaging material.
  • the first segment connection structure includes a redistribution metal layer formed on the EIC chip and its packaging material.
  • the projected area of the PIC chip toward the substrate is greater than the sum of the projected areas of the at least one EIC chip toward the substrate.
  • the semiconductor device comprises a plurality of EIC chips arranged in a matrix, wherein the packaging material is disposed between adjacent EIC chips and surrounds the second segment of the connecting structure.
  • a plurality of the second segments are provided around the at least one EIC chip, among which the second segment whose wiring distance from the at least one EIC chip is not the farthest is connected to the at least one EIC chip.
  • the second segment with the shortest wiring distance is connected to the at least one EIC chip.
  • embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: providing a substrate, an EIC chip and a PIC chip; electrically connecting the EIC chip and the substrate; and electrically connecting the EIC chip and the PIC chip such that the EIC chip is disposed between the PIC chip and the substrate.
  • the method further comprises disposing a packaging material in at least a portion of the periphery of the EIC chip and providing a via conductive structure in the packaging material, wherein the electrical connection path from the PIC chip to the substrate passes through the via conductive structure.
  • the method comprises providing at least two EIC chips including a first EIC chip and a second EIC chip, disposing a packaging material between the first EIC chip and the second EIC chip, and providing at least one via conductive structure in the packaging material.
  • the EIC chip is disposed between the PIC chip and the substrate and the PIC chip is electrically connected to the EIC chip, such that the PIC chip can be electrically connected to the substrate through the EIC chip and the connection structure.
  • the wiring distance from the PIC chip to the substrate is shorten, such that the voltage drop due to long wiring distance can be reduced.
  • a plurality of smaller EIC chips can be used to replace the prior larger EIC chip, and at least one smaller EIC chip can be connected to the substrate through a connection structure located adjacent to it, thereby further shortening the electrical connection distance and further suppressing the voltage drop. Therefore, the performance of the semiconductor device can be improved.
  • FIG. 1 is a cross-sectional view exemplarily showing the structure of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view exemplarily showing a partial structure of a semiconductor device according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram illustrating a plan layout of a partial structure of a semiconductor device according to an embodiment of the present invention.
  • FIG. 4 is a cross-sectional view exemplarily showing the structure of a semiconductor device according to another embodiment of the present invention.
  • FIG. 5 is a flowchart exemplarily showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 1 exemplarily shows the structure of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 exemplarily shows a partial structure of a semiconductor device according to an embodiment of the present invention, omitting a PIC chip.
  • FIG. 3 exemplarily shows a plan layout of a partial structure of a semiconductor device according to an embodiment of the present invention, which omits a PIC chip, a surface cover layer, and a Redistribution Metal Layer (RDL).
  • RDL Redistribution Metal Layer
  • the semiconductor device includes a PIC chip 300 and an EIC chip 200 disposed on a substrate 100 , and the EIC chip 200 is located between the PIC chip 300 and the substrate 100 .
  • the EIC chip and the PIC chip may be set directly opposite to each other, or may not be completely opposite to each other.
  • one EIC chip 200 is disposed on a first surface of a single PIC chip 300 , which faces the substrate 100 .
  • the EIC chip 200 has a first surface facing the PIC chip 300 and a second surface facing the substrate 100 .
  • the EIC chip 200 is mounted on the substrate 100 through a connection structure 400 .
  • the EIC chip 200 is connected to the PIC chip 300 through a first bonding structure.
  • the first bonding structure may include a plurality of microbumps 201 formed of solder.
  • the plurality of microbumps 201 which are formed on a plurality of connection points 202 of the EIC chip 200 are connected to the connection points on the PIC chip 300 to bond the EIC chip and the PIC chip.
  • the first bonding structure may include other bonding structures such as solder balls.
  • the projected area of the PIC chip 300 toward the substrate 100 is larger than the projected area of the EIC chip 200 toward the substrate 100 , and a packaging material 500 such as a molding compound is provided at the periphery of the EIC chip.
  • the projected area of the PIC chip 300 may be equal to or smaller than that of the EIC chip 200 , and a packaging material 500 may also be provided at the periphery of the EIC chip.
  • the packaging material may be provided in at a portion of the periphery of the EIC chip, for example, on the side where the wiring distance from the EIC chip to the substrate is shorter or the shortest.
  • the connection structure 400 includes a first segment electrically connected to the first bond structure, a second segment electrically connected to the first segment, and a second bonding structure electrically connected to the second connecting structure.
  • the first segment of the connection structure includes a RDL layer 401 formed on the EIC chip 200 and its packaging material 500
  • the second segment of the connection structure includes a via conductive structure 402 formed in the packaging material 500
  • the second bonding structure includes a solder ball 403 for connecting the EIC chip 200 to the substrate 100 .
  • the electrical signals can be transmitted from the EIC chip to the substrate through the via conductive structure 402 adjacent to the EIC chip, such that the overall conductive connection distance is reduced.
  • the number of via conductive structure connected to an EIC chip at the periphery of the EIC chip can be one or more (for example, 2 or more). For example, 8, 6, 8, and 6 via conductive structures are arranged on the four sides of an EIC chip, respectively. In some cases, one or more certain sides of the EIC chip may not be provided with any via conductive structure connected thereto.
  • the RDL layer 401 extends laterally from the connection points connected to the plurality of microbumps 201 beyond the EIC chip 200 ; a plurality of via conductive structures 402 extend longitudinally from the RDL layer 401 toward the substrate 100 and terminate at a plurality of solder balls 403 ; the plurality of solder balls 403 are electrically connected to the wiring structures 101 disposed on or in the substrate 100 , or are further connected to external wirings and/or ports. Therefore, the wiring path of the PIC chip 300 of the present embodiment are built to the substrate 100 from the connection points of the PIC chip 300 through the micro-bumps 201 , the RDL layer 401 , the via conductive structures 402 and the solder balls 403 .
  • the wiring of the embodiment is simpler and shorter, such that the voltage drop can be reduced.
  • a plurality of openings are formed in the packaging material 500 , and conductive materials are formed in the openings, thereby forming the via conductive structures 402 that are connected to the substrate 100 through solder balls 403 .
  • the RDL layer 401 is formed on the surface of the packaging material 500 and the EIC chip 200 , and electrically connects the via conductive structures 402 to the EIC chip 200 and the PIC chip 300 .
  • a surface covering layer 600 is formed on the surface of the RDL layer 401 for protecting the RDL layer 401 . As shown in FIG.
  • the via conductive structures 402 can be arranged as close as possible to the EIC chip 200 to shorten the wiring line, the PIC chip 300 , the RDL layer 401 and the surface covering layer 600 are not shown in the figure.
  • the PIC chip 300 may include a PIC wiring structure (not shown), and the EIC chip 200 may include an EIC wiring structure (not shown).
  • the conductive path or electrical connection path from the PIC chip 300 to the substrate successively passes through the PIC wiring structure (PIC chip) and the EIC wiring structure (EIC chip), and may terminate at the substrate (wirings on the substrate) or further pass through the substrate to the other devices on the substrate.
  • the conductive path passes through the PIC wiring structure, the EIC wiring structure, and the via conductive structure 402 in sequence.
  • the conductive path from the PIC chip 300 to the substrate 100 may sequentially passes through the PIC wiring structure (PIC chip), a PIC rewiring structure, a first bonding structure, a first EIC rewiring structure, the EIC wiring structure (EIC chip), a second EIC rewiring structure, a via conductive structure, and a second bonding structure, wherein at least one of the first bonding structure, the PIC rewiring structure, the first EIC rewiring structure, the second EIC rewiring structure, and the second bonding structure is optional.
  • an additional bonding structure may be provided for connecting the above-mentioned wiring structures, rewiring structures, PIC chip, EIC chip, etc.
  • the first bonding structure such as the microbump 201 is used for connecting the PIC chip and the EIC chip
  • the second bonding structure such as the solder ball 403 is used for connecting the EIC chip 200 and the substrate 100 .
  • the aforementioned rewiring structures may include a RDL layer.
  • the first segment of the connection structure 400 between the EIC and the substrate includes the second EIC rewiring structure (for example, the RDL layer 401 ), and the second segment of the connection structure 400 includes the via conductive structure.
  • the first bonding structure is not necessary for electrically connecting the EIC chip 200 and the PIC chip 300 .
  • both chips can be bonded by diffusion approach.
  • Cu in the EIC wiring structure and Cu in the PIC wiring structure diffuse and bond to each other, such that the EIC chip and the PIC chip are bonded.
  • the RDL layer 401 may have 5 copper layers, and the thickness of each layer is about 7.5 um. Compared with the existing metal wire bonding on the PIC chip, the impedance of the RDL layer 401 is more than 24 times smaller.
  • the RDL layer 401 may be other structures, for example, the RDL layer 401 may have other number of conductor layers of other materials such as 4 or 5 layers, the thickness of each layer may be other values, and each layer can vary in thickness.
  • the second bonding structure may also be a bonding structure other than solder balls in the art, such as solder bumps.
  • FIG. 4 exemplarily shows the structure of a semiconductor device according to another embodiment of the present invention.
  • the semiconductor device includes a plurality of EIC chips 200 , a PIC chip 300 , and the substrate 100 , and the plurality of EIC chips 200 are located between the PIC chip 300 and the substrate 100 .
  • a plurality of EIC chips 200 are flip-chipped on the surface of a single PIC chip 300 facing the substrate 100 , and the plurality of EIC chips 200 are respectively mounted on the substrate 100 through the connection structure 400 .
  • the connection structure 400 is similar to that as described in the above embodiment, and will not be repeated here.
  • the difference between this embodiment and the embodiment shown in FIG. 1 lies in the number and layout of the EIC chips 200 .
  • the number of the EIC chips 200 may be 2, 3 or more.
  • the projected area of the PIC chip 300 facing the substrate 100 is greater than the sum of the projected areas of the plurality of EIC chips 200 facing the substrate.
  • the electrical signals can be transmitted from one of the plurality of EIC chips 200 to the substrate through the via conductive structure adjacent to the EIC chip, such that the overall conductive connection distance is reduced.
  • the plurality of EIC chips include a first EIC chip and a second EIC chip, wherein the via conductive structures may be arranged around each of the first EIC chip and the second EIC chip, so that the first and/or second EIC chips can be connected to the via conductive structures in close proximity, such that the electrical connection is optimized.
  • 16 via conductive structures are provided between the first and second EIC chips, among which 6 are connected to the first EIC chip and 10 are connected to the second EIC chip.
  • the plurality of EIC chips are arranged in the form of a matrix (not shown), and a packaging material may be provided between adjacent EIC chips and surrounds the second segment of the connection structure (such as via conductive structures).
  • a plurality of the second segments are provided around the at least one EIC chip among which the second segment whose wiring distance from the at least one EIC chip is not the farthest is connected to the at least one EIC chip.
  • the connection structure including the second segment with a relatively short wiring distance from the EIC chip is used for connection.
  • the second segment with the shortest wiring distance is connected to the EIC chip.
  • a semiconductor device comprises 9 EIC chips arranged in 3 ⁇ 3 matrix, a packaging material disposed between adjacent EIC chips, and one and/or more openings accommodating connection conductors provided in the packaging material.
  • one or more openings with the shorter or shortest wiring distance from the EIC chip can be connected to the EIC chip.
  • all EIC chips can be connected to the second segment with the shortest or relatively short wiring distance from them.
  • the arrangement of the EIC chips may be linear, for example, 2, 3 or 4 EIC chips are arranged in a line.
  • a plurality of EIC chips are used to replace one EIC chip that should be required by the semiconductor device according to the prior art, and some or all of the plurality of EIC chips are connected to the substrate through the connection structure located in the vicinity thereof, thereby shortening the electrical connection distance and reducing the voltage drop.
  • FIG. 5 exemplarily shows a flow of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • the method includes following steps:
  • the at least one EIC chip is connected to the PIC chip through a first bonding structure (such as solder balls, microbumps, and the like).
  • the connection structure includes a first segment (such as a RDL layer) electrically connected to the first bonding structure, a second segment (such as a via conductive structure) electrically connected to the first segment, and a second bonding structure (such as solder balls) electrically connected to the second segment.
  • the at least one EIC chip is connected to the substrate through the second bonding structure.
  • the method further includes disposing a packaging material at at least a part of the periphery of the at least one EIC chip; forming a redistribution metal layer (RDL) on the at least one EIC chip and its packaging material, wherein the first segment of the connection structure includes the RDL layer; forming a via conductive structure in the packaging material, wherein the second segment of the connection structure includes the via conductive structure.
  • RDL redistribution metal layer
  • the projected area of the PIC chip toward the substrate is greater than the sum of the projected areas of the at least one EIC chip toward the substrate. In alternative embodiments, for a single EIC chip, the projected area of the PIC chip toward the substrate may be equal to or smaller than the projected area of the EIC chip toward the substrate.
  • a plurality of EIC chips may be arranged in a matrix.
  • a plurality of second segments are provided around the at least one EIC chip among which the second segment whose wiring distance from the at least one EIC chip is not the farthest (i.e., the second segment is relatively close to the at least one EIC chip) is connected to the at least one EIC chip.
  • the second segment with the shortest wiring distance from the at least one EIC chip is connected to the at least one EIC chip. It can be seen that the wiring of the PIC chip is optimized by using the above-mentioned connection structure. Specifically, the embodiments of the present invention use a simple wiring structure to shorten the wiring distance and reduce the voltage drop.
  • a plurality of EIC chips may be arranged in a linear arrangement.
  • two EIC chips are arranged in a row or column.
  • a method for manufacturing a semiconductor device comprises: providing a substrate, an EIC chip and a PIC chip; electrically connecting the EIC chip and the substrate; electrically connecting the EIC chip and the PIC chip such that the EIC chip is located between the PIC chip and the substrate.
  • a packaging material is provided at at least a part of the periphery of the EIC chip, a via conductive structure is disposed in the packaging material, and the electrical connection path from the PIC chip to the substrate passes through the via conductive structure.
  • at least two EIC chips may be provided and the at least two EIC chips include a first EIC chip and a second EIC chip.
  • a packaging material is provided between the first EIC chip and the second EIC chip and at least one via conductive structure is provided in the packaging material.
  • connection structure 400 may also use other suitable electrical connection structures known in the art.

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  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
US17/826,791 2021-05-31 2022-05-27 Semiconductor devices and methods for manufacturing the same Pending US20220384409A1 (en)

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CN202110598491.4A CN113035858B (zh) 2021-05-31 2021-05-31 半导体装置及其制造方法

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US11726383B2 (en) * 2020-10-14 2023-08-15 California Institute Of Technology Modular hybrid optical phased arrays

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