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US20190103414A1 - Embedded sonos with a high-k metal gate and manufacturing methods of the same - Google Patents

Embedded sonos with a high-k metal gate and manufacturing methods of the same Download PDF

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Publication number
US20190103414A1
US20190103414A1 US15/820,138 US201715820138A US2019103414A1 US 20190103414 A1 US20190103414 A1 US 20190103414A1 US 201715820138 A US201715820138 A US 201715820138A US 2019103414 A1 US2019103414 A1 US 2019103414A1
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Prior art keywords
layer
gate
oxide
mos
dielectric
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US15/820,138
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Krishnaswamy Ramkumar
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Longitude Flash Memory Solutions Ltd
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Cypress Semiconductor Corp
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Priority to US15/820,138 priority Critical patent/US20190103414A1/en
Assigned to CYPRESS SEMICONDUCTOR CORPORATION reassignment CYPRESS SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RAMKUMAR, KRISHNASWAMY
Priority to TW107128732A priority patent/TWI779080B/zh
Priority to EP18864320.9A priority patent/EP3692576A4/en
Priority to KR1020207012459A priority patent/KR102631491B1/ko
Priority to CN201880072893.7A priority patent/CN111801801B/zh
Priority to PCT/US2018/050939 priority patent/WO2019070383A1/en
Priority to JP2020519345A priority patent/JP2020536394A/ja
Publication of US20190103414A1 publication Critical patent/US20190103414A1/en
Assigned to LONGITUDE FLASH MEMORY SOLUTIONS LTD. reassignment LONGITUDE FLASH MEMORY SOLUTIONS LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CYPRESS SEMICONDUCTOR CORPORATION
Assigned to CYPRESS SEMICONDUCTOR CORPORATION, SPANSION LLC reassignment CYPRESS SEMICONDUCTOR CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC.
Priority to US16/541,765 priority patent/US11641745B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H01L27/11573—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L27/11568—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10P14/6304—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H10P50/283—

Definitions

  • MOSFET metal-oxide-semiconductor field-effect transistors
  • NVM non-volatile memory
  • MOS transistors are typically fabricated using a standard or baseline complementary-metal-oxide-semiconductor (CMOS) process flow, involving the formation and patterning of conducting, semiconducting and dielectric materials.
  • CMOS complementary-metal-oxide-semiconductor
  • forming a gate oxide or dielectric of a MOS transistor may significantly degrade performance of a previously formed charge-trapping gate stack by altering a thickness or composition of the charge-trapping layer(s).
  • this integration may also impact the baseline CMOS process flow, and generally require a substantial number of mask sets and process steps, which add to the expense of fabricating the devices and may reduce yield of working devices.
  • NVM transistors may be important for the integrated fabrication process to be able to control the thickness of top or blocking dielectric of NVM transistors, for example, in order to meet requirements such as desirable threshold voltages Vts and/or equivalent oxide thickness (EOT) while satisfying gate oxide thickness (physical or electrical) targets of MOS transistors, especially if those MOS transistors are high voltage (HV) or input/output (I/O) transistors.
  • Vts threshold voltages
  • EOT equivalent oxide thickness
  • HV high voltage
  • I/O input/output
  • HKMG stacks may switch using a thin high-K dielectric additionally or alternatively to the silicon dioxide or silicon oxynitride layer and a metal gate instead of a polysilicon gate.
  • HKMG stacks may improve leakage and performances of MOS transistors, and data retention of SONOS transistors. Therefore, there are needs to incorporate SONOS into HKMG CMOS process flow.
  • the introduction of metal gates to SONOS transistors may transform the device to metal-oxide-nitride-oxide-semiconductor (MONOS). It will be the understanding that the two terms, viz. SONOS and MONOS are used interchangeably throughout this patent document.
  • FIG. 3 is a flowchart illustrating another embodiment of a method for fabricating a memory cell including an embedded SONOS based NVM transistor and MOS transistors of an interim memory cell illustrated in FIG. 2L ;
  • FIGS. 4A-4D are representative diagrams illustrating cross-sectional views of a portion of a memory cell during fabrication of the memory cell according to the method of FIG. 3 ;
  • FIG. 5 is a flowchart illustrating another embodiment of a method for fabricating a memory cell including an embedded SONOS based NVM transistor and MOS transistors of an interim memory cell illustrated in FIG. 2L ;
  • FIGS. 6A-6E are representative diagrams illustrating cross-sectional views of a portion of a memory cell during fabrication of the memory cell according to the method of FIG. 5 ;
  • FIG. 7 is a flowchart illustrating an embodiment of subsequent steps to the embodiments in FIGS. 1, 3, and 5 for fabricating a memory cell or array including an embedded SONOS based NVM transistor and MOS transistors;
  • FIGS. 8A-8I are representative diagrams illustrating cross-sectional views of a portion of a memory cell during fabrication of the memory cell according to the method of FIG. 7 ;
  • FIG. 8J is a representative diagram illustrating a cross-sectional view of a portion of a finished memory cell including an embedded SONOS based NVM transistor and MOS transistors fabricated according to the method of FIGS. 1, 3, 5, and 7 ;
  • FIG. 9 is a representative block diagram illustrating one embodiment of embedded SONOS or MONOS based NVM device 800 , as fabricated in FIGS. 2A-2L and 8A-8I .
  • Embodiments of a memory cell including an embedded non-volatile memory (NVM) transistor and metal-oxide-semiconductor (MOS) transistors having a high-K metal gate (HKMG) stack, and methods of fabricating the same are described herein with reference to figures. However, particular embodiments may be practiced without one or more of these specific details, or in combination with other known methods, materials, and apparatuses in related art. In the following description, numerous specific details are set forth, such as specific materials, dimensions, concentrations, and processes parameters etc. to provide a thorough understanding of the subject matter. In other instances, well-known semiconductor design and fabrication techniques have not been described in particular detail to avoid unnecessarily obscuring the subject matter.
  • the terms “over”, “under”, “between”, and “on” as used herein refer to a relative position of one layer with respect to other layers.
  • one layer deposited or disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer deposited or disposed between layers may be directly in contact with the layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in contact with that second layer.
  • the relative position of one layer with respect to other layers is provided assuming operations deposit, modify and remove films relative to a starting substrate without consideration of the absolute orientation of the substrate.
  • the NVM transistor may include memory transistors or devices implemented related to Silicon-Oxide-Nitride-Oxide-Silicon (SONOS), Metal-Oxide-Nitride-Oxide-Silicon (MONOS) or floating gate technology.
  • SONOS Silicon-Oxide-Nitride-Oxide-Silicon
  • MONOS Metal-Oxide-Nitride-Oxide-Silicon
  • FIGS. 1, 3, 5, and 7 are flowcharts illustrating embodiments of a method or process flow for fabricating the memory cell or array in various stages and alternative methods.
  • FIGS. 1, 3, 5, and 7 are block diagrams illustrating cross-sectional views of a portion of a memory cell during fabrication of the memory cell according to the method of FIGS. 1, 3, 5, and 7 , respectively.
  • FIG. 8J is a representative diagram illustrating a cross-sectional view of a portion of an embodiment of the finished memory cell or array.
  • a semiconductor device disclosed herein may include a non-volatile memory (NVM) transistor including a charge-trapping layer and a blocking dielectric, a field-effect transistor (FET) of a first type including a first gate dielectric having a first thickness, a FET of a second type including a second gate dielectric having a second thickness, and a FET of a third type including a third gate dielectric having a third thickness.
  • NVM non-volatile memory
  • FET field-effect transistor
  • first type including a first gate dielectric having a first thickness
  • FET of a second type including a second gate dielectric having a second thickness
  • a FET of a third type including a third gate dielectric having a third thickness.
  • each of the first, second, and third gate dielectric may include a high dielectric constant (high-K) dielectric layer. The first thickness is greater than the second thickness, and the second thickness is greater than the third thickness.
  • the FET of the first type may be a high voltage metal-oxide-semiconductor (HV_MOS) transistor
  • the FET of the second type may be an input/output metal-oxide-semiconductor (I/O_MOS) transistor
  • the FET of the third type may be a low voltage metal-oxide-semiconductor (LV_MOS) transistor.
  • the blocking dielectric of the NVM transistor may include the high-K dielectric layer disposed overlying a blocking oxide.
  • the NVM transistor may be disposed in a first region and the FETs of the first, second, and third types in a second region, in which the first and second regions are both disposed in one single semiconductor die.
  • a multilayer metal gate may be disposed overlying each of the first, second, and third gate dielectric, in which the multilayer metal gate may include a thick metal layer disposed over a gate metal layer.
  • a multilayer metal gate may be disposed overlying the blocking dielectric of the NVM transistor, in which the multilayer metal gate may include a thick metal layer disposed over a gate metal layer.
  • the NVM transistor may have a polysilicon gate disposed overlying the blocking dielectric.
  • the gate metal layer therein may include low work function metal.
  • the low work function metal includes at least one of titanium, lanthanum, aluminum, and compounds or alloys thereof.
  • the gate metal layer therein may include high work function metal.
  • the high work function metal includes at least one of aluminum, titanium, and compounds or alloys thereof.
  • the NVM transistor is a metal-oxide-nitride-oxide-semiconductor (MONOS) transistor.
  • MONOS metal-oxide-nitride-oxide-semiconductor
  • the gate metal layer therein may include high work function metal.
  • the high work function metal includes at least one of aluminum, titanium, and compounds or alloys thereof.
  • the gate metal layer therein may include low work function metal.
  • the gate metal layer therein may include high work function metal.
  • the first thickness of the first gate dielectric in the HV_MOS transistor is in an approximate range of 110 ⁇ to 160 ⁇ , and the HV_MOS transistor is configured to operate in a voltage range of 4.5 V to 12 V for at least program or erase operations of the NVM transistor.
  • the charge-trapping layer may have a first charge-trapping layer that is oxygen-rich, a second (top) charge-trapping layer disposed over the first (bottom) charge-trapping layer that is silicon-rich and oxygen-lean relative to the first charge-trapping layer, and an anti-tunneling oxide layer disposed between the first and second charge-trapping layers.
  • the second charge-trapping layer may have a majority of charge traps in the charge-trapping layer.
  • a memory device disclosed herein may have a substrate disposed within a single semiconductor die, a plurality of non-volatile memory (NVM) transistors formed in a first region of the substrate, and a plurality of metal-oxide-semiconductor (MOS) transistors formed in a second region of the substrate.
  • NVM non-volatile memory
  • MOS metal-oxide-semiconductor
  • a system disclosed herein may include a system-on-chip (SOC) device, a plurality of logic devices, and an embedded non-volatile memory (NVM) device disposed within one single semiconductor die.
  • the embedded NVM device may include a plurality of metal-oxide-nitride-oxide-semiconductor (MONOS) transistors, in which at least one MONOS transistor includes a first metal gate layer overlying a first high dielectric constant (high-K) dielectric layer
  • the SOC device and the plurality of logic devices may include high voltage (HV) metal-oxide-semiconductor (MOS) transistors, input/output (I/O) MOS transistors, and low voltage (LV) MOS transistors, in which the gate dielectric of each of the HV MOS, I/O MOS, and LV MOS transistors includes a second high-K dielectric layer, and wherein the gate dielectric of the HV MOS transistors are thick
  • in-situ steam generation (ISSG) or radical oxidation process may not be ideal for the gate oxidation for both top or blocking oxide layer of the NVM transistors and gate oxide layer for the HV or I/O_MOS transistors.
  • ISG in-situ steam generation
  • radical oxidation process may not be ideal for the gate oxidation for both top or blocking oxide layer of the NVM transistors and gate oxide layer for the HV or I/O_MOS transistors.
  • top oxide grown on the ONO stack may be exposed to the ISSG process for too long and end up being too thick.
  • gate oxides of the HV or I/O_MOS transistors may be grown by either a furnace process or a rapid thermal oxidation (RTO) process.
  • embodiments depicted herein may be directed to fabrication processes that ensure that the ONO stack of the NVM transistors meets the thickness and reliability requirements without degradation of the ONO stack performance, due to the HKMG process flow and thick gate layer oxidation of the HV and/or I/O_MOS transistors in an embedded system.
  • the process begins with forming a number of isolation structures or shallow trench isolation (STI) 202 in a wafer or substrate 204 (step 102 ).
  • the isolation structures 202 isolate the memory cell being formed from memory cells formed in adjoining areas (not shown) of the substrate 204 .
  • isolation structures 202 may be incorporated to isolate the NVM transistor(s) being formed in a first region 206 of the substrate 204 from one or more of the MOS transistors including HV_MOS, I/O_MOS, and LV_MOS, being formed in a second region 208 . As illustrated in FIG.
  • isolation structures 202 may be formed to isolate HV_MOS, I/O_MOS, and LV_MOS from one another.
  • the isolation structures 202 may include a dielectric material, such as oxide or nitride, and may be formed by any conventional technique, including but not limited to STI or local oxidation of silicon (LOCOS).
  • the substrate 204 may be a bulk substrate composed of any single crystal material suitable for semiconductor device fabrication, or may include a top epitaxial layer of a suitable material formed on a substrate.
  • suitable materials for substrate 204 include, but are not limited to, silicon, germanium, silicon-germanium or a Group III-V compound semiconductor material.
  • pad oxide 209 may be formed over a surface 216 of the substrate 204 in both the first region 206 and the second region 208 .
  • pad oxide 209 may be silicon dioxide (SiO 2 ) having a thickness of from about 10 nanometers (nm) to about 20 nm or other thicknesses and may be grown by a thermal oxidation process or in-situ steam generation (ISSG) process, or other oxidation or deposition processes known in the art. It will be the understanding that pad oxide 209 may not be necessary, or formed in some embodiments.
  • dopants are then implanted into substrate 204 through pad oxide 209 (if present) to form wells in which the NVM transistor(s) and/or the MOS transistors may be formed, and channels for the MOS transistors (step 104 ).
  • isolation structures 202 may be formed anywhere in substrate 204 as required, and shall not be limited to the ones shown in the figures.
  • the dopants implanted may be of any type and concentration, and may be implanted at any energy, including energies necessary to form wells or deep wells for the NVM transistors and/or the MOS transistors, and to form channels for the MOS transistors.
  • dopants of an appropriate ion species are implanted to form a deep N-well 210 in the second region 208 over or in LV_MOS transistor 212 , in which a P-type or P-channel transistor, may be formed.
  • wells or deep wells may also be formed for the NVM transistor 226 and/or HV_MOS transistor 214 , and/or I/O_MOS transistor 215 .
  • implantation may also be used to form channels 218 , in all three of the MOS transistors 214 , 212 , 215 at the same time, or at separate times using standard lithographic techniques, including a patterned photoresist layer to mask one of the channels 218 for the MOS transistors 214 , 212 , 215 .
  • a patterned tunnel mask 220 is formed on or overlying pad oxide 209 layer, ions (represented by arrows 222 ) of an appropriate type, energy, and concentration are implanted through a window or opening in tunnel mask 220 to form channel 224 for NVM transistor 226 in the first region 206 , and tunnel mask 220 and pad oxide 209 layer in at least the second region 208 removed (step 106 ).
  • Tunnel mask 220 may include a photoresist layer, or a hard mask formed, from a patterned nitride or silicon-nitride layer.
  • multiple channels 224 may be formed concurrently, individually, or in groups.
  • a shallow doped channel is implanted with arsenic at an energy about 20 keV and a dose of from about 5e11 cm ⁇ 2 to about 1e13 cm ⁇ 2 at channel 224 .
  • BF 2 may be implanted to form an N-channel NVM transistor, or arsenic or phosphorous implanted to form a P-channel NVM transistor.
  • channel 224 for NVM transistor 226 may also be formed concurrently with channels 218 of the MOS transistors 214 , 212 , 215 .
  • channel(s) 224 of N-channel NVM transistor(s) and P-channel NVM transistor(s) may be formed concurrently, or separately.
  • pad oxide 209 in the window or opening in the tunnel mask 220 may be removed, for example in a wet clean process using a 10:1 buffered oxide etch (BOE) containing a surfactant.
  • BOE buffered oxide etch
  • the wet clean process can be performed using a 20:1 BOE wet etch, a 50:1 hydrofluoric (HF) wet etch, a pad etch, or any other similar hydrofluoric-based wet etching chemistry.
  • tunnel mask 220 includes photoresist material may be ashed or stripped using oxygen plasma.
  • hard tunnel mask 220 may be removed using a wet or dry etch process known in the art.
  • surface 216 of substrate 204 in the first region 206 is cleaned or pre-cleaned, a number of dielectric layers, such as oxide-nitride-oxide or ONO layers or oxide-nitride-oxide-nitride-oxide or ONONO layers, formed or deposited (step 108 ). Subsequently, a mask is formed on or overlying the dielectric layers, and the dielectric layers are etched to form NV gate stack 236 in first region 206 (step 110 ).
  • the preclean may be a wet or dry process.
  • SC1 is typically performed using a 1:1:5 solution of ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 O) at 30° C. to 80° C. for about 10 minutes.
  • SC2 is a short immersion in a 1:1:10 solution of HCl, H 2 O 2 and H 2 O at about 30° C. to 80° C.
  • the dielectric or NV gate stack deposition begins with the formation of tunnel dielectric 228 over at least channel 224 of NVM transistor 226 in the first region 206 of substrate 204 , and may spread over to second region 208 of substrate 204 where MOS transistors 212 , 214 , 215 are formed.
  • the tunnel dielectric 228 may be any material and have any thickness suitable to allow charge carriers to tunnel into an overlying charge-trapping layer under an applied gate bias while maintaining a suitable barrier to leakage when NVM transistor 226 is unbiased.
  • tunnel dielectric 228 may be silicon dioxide, silicon oxy-nitride, or a combination thereof and may be grown by a thermal oxidation process, using ISSG or radical oxidation.
  • a silicon dioxide tunnel dielectric 228 may be thermally grown in a thermal oxidation process.
  • a layer of silicon dioxide may be grown utilizing dry oxidation at 700° C.-800° C. in an oxygen containing gas or atmosphere, such as oxygen (O 2 ) gas.
  • the thermal oxidation process is carried out for a duration approximately in the range of 20 to 150 minutes to effect growth of a tunnel dielectric 228 having a relatively uniform thickness of from about 1.0 nanometers (nm) to about 3.0 nm by oxidation and consumption of the exposed surface of substrate. It will be understood that such a range is merely illustrative and is not meant to be limiting.
  • a silicon dioxide tunnel dielectric 228 may be grown in a radical oxidation process involving flowing hydrogen (H 2 ) and oxygen (O 2 ) gas into a processing chamber at a ratio to one another of approximately 1:1 without an ignition event, such as forming of a plasma, which would otherwise typically be used to pyrolyze the H 2 and O 2 to form steam.
  • the H 2 and O 2 are permitted to react at a temperature approximately in the range of about 900° C. to about 1100° C. at a pressure approximately in the range of about 0.5 Torr to about 10 Torr to form radicals, such as, an OH radical, an HO 2 radical or an O diradical, at the surface of substrate.
  • the radical oxidation process is carried out for a duration approximately in the approximate range of about 1 to about 10 minutes to effect growth of a tunnel dielectric 228 having a thickness of from about 1.0 nanometers (nm) to about 4.0 nm by oxidation and consumption of the exposed surface of substrate. It will be understood that in FIG. 2E and subsequent figures the thickness of tunnel dielectric 228 may be exaggerated for the purposes of clarity. In one embodiment, tunnel dielectric 228 grown in a radical oxidation process may be both denser and composed of substantially fewer hydrogen atoms per cm 3 than a tunnel dielectric formed by wet oxidation techniques, even at a reduced thickness.
  • the radical oxidation process is carried out in a batch-processing chamber or furnace capable of processing multiple substrates to provide a high quality tunnel dielectric 228 without impacting the throughput (substrates/hr.) requirements that a fabrication facility may require.
  • tunnel dielectric layer 228 is deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) and is composed of a dielectric layer which may include, but is not limited to silicon dioxide, silicon oxy-nitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • tunnel dielectric 228 may be a bi-layer dielectric region including a bottom layer of a material such as, but not limited to, silicon dioxide or silicon oxy-nitride and a top layer of a material which may include, but is not limited to silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide.
  • a material such as, but not limited to, silicon dioxide or silicon oxy-nitride
  • a top layer of a material which may include, but is not limited to silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide.
  • a charge-trapping layer is formed on or overlying the tunnel dielectric 228 .
  • the charge-trapping layer may be a multi-layer charge-trapping layer 230 comprising multiple layers including at least a lower or first charge-trapping layer 230 a which is physically closer to the tunnel dielectric 228 , and an upper or second charge-trapping layer 230 b that is oxygen-lean relative to the first charge-trapping layer, and comprises a majority of a charge traps distributed in multi-layer charge-trapping layer 230 .
  • the first charge-trapping layer 230 a of multi-layer charge-trapping layer 230 may include a silicon nitride (Si 3 N 4 ), silicon-rich silicon nitride or a silicon oxy-nitride (SiO x N y (HO)) layer.
  • the first charge-trapping layer 230 a may include a silicon oxynitride layer having a thickness of between about 2.0 nm and about 6.0 nm formed by a CVD process using dichlorosilane (DCS)/ammonia (NH 3 ) and nitrous oxide (N 2 O)/NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer.
  • DCS dichlorosilane
  • NH 3 ammonia
  • N 2 O nitrous oxide
  • the second charge-trapping layer 230 b of the multi-layer charge-trapping layer 230 is then formed, either directly or indirectly, over the first charge-trapping layer 230 a .
  • the second charge-trapping layer 230 b may include a silicon nitride and silicon oxy-nitride layer having a stoichiometric ratio of oxygen, nitrogen and/or silicon that is different from that of the first charge-trapping layer 230 a .
  • the second charge-trapping layer 230 b may include a silicon oxynitride layer having a thickness of between about 2.0 nm and about 8.0 nm, and may be formed or deposited by a CVD process using a process gas including DCS/NH 3 and N 2 O/NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top nitride layer.
  • the stoichiometric composition of oxygen, nitrogen and/or silicon of first and second charge-trapping layers 230 a and 230 b may be identical or approximately equal to one another.
  • the multi-layer charge-trapping layer 230 is a split charge-trapping layer, further including a thin, middle oxide layer 230 c separating the first (lower) and second (upper) charge-trapping layers 230 a and 230 b .
  • the middle oxide layer 230 c substantially reduces the probability of electron charge that accumulates at the boundaries of the second charge-trapping layer 230 b during programming from tunneling into the first charge-trapping layer 230 a , resulting in lower leakage current than for the conventional memory devices.
  • the middle oxide layer 230 c may be formed by oxidizing to a chosen depth of the first charge-trapping layer 230 a using thermal or radical oxidation. Radical oxidation may be performed, for example, at a temperature of 1000-1100° C. using a single substrate tool, or 800-900° C. using a batch reactor tool. A mixture of H 2 and O 2 gasses may be introduced to a process chamber at a ratio of approximately 1:1 and 10-15 Torr.
  • the radical oxidation process is without an ignition event, such as forming of plasma, which would otherwise typically be used to pyrolyze the H 2 and O 2 to form steam.
  • the H 2 and O 2 is permitted to react at a surface of the first charge-trapping layer 230 a to form radicals, such as, an OH radical, an HO 2 radical or an O diradical, to form the middle oxide layer 230 c.
  • oxygen-rich and “silicon-rich” are relative to a stoichiometric silicon nitride, or “nitride,” commonly employed in the art having a composition of (Si 3 N 4 ) and with a refractive index (RI) of approximately 2.0.
  • nitride commonly employed in the art having a composition of (Si 3 N 4 ) and with a refractive index (RI) of approximately 2.0.
  • RI refractive index
  • films described herein as “silicon-rich” entail a shift from stoichiometric silicon nitride toward a higher weight % of silicon with less oxygen than an “oxygen-rich” film.
  • a silicon-rich silicon oxynitride film is therefore more like silicon and the RI is increased toward the 3.5 RI of pure silicon.
  • the number of dielectric layers further includes cap layer 232 formed on or overlying charge-trapping layer 230 or second charge-trapping layer 230 b .
  • cap layer 232 is a multi-layer cap layer including at least a lower or first cap layer 232 a overlying the charge-trapping layer 230 , and a second cap layer 232 b overlying the first cap layer 232 a.
  • first cap layer 232 a may include a high-temperature-oxide (HTO), such as silicon oxide (SiO 2 ), having a thickness of between 2.0 nm and 4.0 nm deposited using a low pressure chemical vapor deposition (LPCVD) thermal oxidation process.
  • HTO high-temperature-oxide
  • the oxidation process may include exposing the substrate 204 to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as O 2 or N 2 O in a deposition chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 900° C. to about 1000° C.
  • the oxidation process is performed in-situ in the same process chamber as used to form second charge-trapping layer 230 b , and immediately following the formation of second charge-trapping layer 230 b.
  • second cap layer 232 b may include a silicon nitride, a silicon-rich silicon nitride or a silicon-rich silicon oxynitride layer having a thickness of between 2.0 nm and 4.0 nm formed by a CVD process using N 2 O/NH 3 and DCS/NH 3 gas mixtures.
  • a sacrificial oxide layer 234 is formed on or overlying cap layer 232 .
  • sacrificial oxide layer 234 may include a high-temperature-oxide (HTO) layer grown by a thermal oxidation process or radical oxidation, and having a thickness of between 2.0 nm and 4.0 nm.
  • HTO high-temperature-oxide
  • sacrificial oxide layer 234 may be formed or deposited by a chemical vapor deposition process in a low pressure chemical vapor deposition (LPCVD) chamber.
  • LPCVD low pressure chemical vapor deposition
  • sacrificial oxide layer 234 may be deposited by a CVD process using a process gas including gas mixtures of silane or DCS and an oxygen containing gas, such as O 2 or N 2 O, in ratios and at flow rates tailored to provide a silicon dioxide (SiO 2 ) sacrificial oxide layer 234 .
  • a process gas including gas mixtures of silane or DCS and an oxygen containing gas, such as O 2 or N 2 O, in ratios and at flow rates tailored to provide a silicon dioxide (SiO 2 ) sacrificial oxide layer 234 .
  • a patterned mask layer 280 is formed on or overlying the sacrificial oxide layer 234 , and referring to FIG. 2F , the sacrificial oxide layer 234 , cap layer 232 and charge-trapping layer 230 , and tunnel dielectric layer 228 disposed outside of the first region 206 are etched or patterned to form NV gate stack 236 .
  • NV gate stack 236 may be disposed substantially overlying channel 224 of NVM transistor 226 in first region 206 . The etching or patterning process may further remove various dielectric layers of NV gate stack 236 from second region 208 of substrate 204 (step 110 ).
  • the patterned mask layer 280 may include a photoresist layer patterned using standard lithographic techniques, and the NV gate stack 236 layers in second region 208 may be etched or removed using a dry etch process including one or more separate steps to stop on a surface of the tunnel dielectric 228 or pad oxide 209 .
  • the etching may be configured to remove dielectric layers in NV gate stack in STIs 202 divot by introducing an isotropic component, and be stopped in second region 208 when a minimum of approximately 45 ⁇ of pad oxide 209 remaining.
  • sacrificial oxide layer 234 and a top portion or substantially all of second cap layer 232 b in the multi-layer cap layer 232 are removed from NV gate stack 236 in a highly selective cleaning process (step 112 ).
  • This cleaning process further removes any oxide, such as oxide in tunnel dielectric 228 and/or pad oxide 209 , remaining in the first region 206 beyond NV gate stack 236 , and in second region 208 to prepare substrate 204 for HV gate oxide 252 layer growth.
  • pad oxide 209 may not be removed entirely or at all (dotted line in FIG. 2G ).
  • sacrificial oxide layer 234 and second cap layer 232 b may be removed in a wet clean process using a 10:1 buffered oxide etch (BOE) containing a surfactant.
  • BOE buffered oxide etch
  • the wet clean process can be performed using a 20:1 BOE wet etch, a 50:1 hydrofluoric (HF) wet etch, a pad etch, or any other similar hydrofluoric-based wet etching chemistry.
  • HV gate oxide 252 layer is formed over substrate 204 (step 114 ), either directly or indirectly.
  • the process starts when pad oxide 209 is completely or partially removed in a pad oxide preclean process.
  • HV gate oxide 252 layer is formed by a dry rapid thermal oxidation (RTO) process, a conventional or furnace oxidation process, a chemical vapor deposition process (CVD), or other non-radical oxide forming processes known in the art, or a combination thereof.
  • RTO dry rapid thermal oxidation
  • CVD chemical vapor deposition process
  • wet furnace oxidation may not be recommended, as explained in later sections.
  • the oxidation process starts with dry RTO performed in a batch or single wafer processing chamber with or without an ignition event such as plasma.
  • the device is subjected to a rapid thermal oxidation process involving flowing oxygen (O 2 ) gas into a processing chamber.
  • the O 2 gas is permitted to react at a temperature approximately in the range of 1000-1100° C. at a pressure approximately in the range of 0.5-5 Torr. to form HV gate oxide 252 layer.
  • HV gate oxide 252 layer may be grown, by oxidizing silicon wafer 204 , on at least a portion of the surface 216 of wafer 204 .
  • RTO process may be substituted with a rapid molecular oxidation which is a non-radical oxidation process.
  • HV gate oxide 252 layer however may not be formed by a wet rapid and radical oxidation process, such as in-situ steam generation (ISSG) because such radical oxidation processes may affect or oxidize cap layers 232 a and/or 232 b and second charge-trapping layer 230 b of NV gate stack 226 in the first region 206 .
  • ISSG in-situ steam generation
  • RTO or conventional furnace oxidation processes may be substituted by processes such as chemical vapor deposition (CVD), or other non-radical oxidation processes performed in a batch or single wafer processing chamber with or without an ignition event such as plasma as long as oxide will be grown or deposited to form HV gate oxide 252 layer in the second region 208 .
  • CVD chemical vapor deposition
  • an ignition event such as plasma as long as oxide will be grown or deposited to form HV gate oxide 252 layer in the second region 208 .
  • by controlling operation parameters in the HV gate oxide 252 layer formation targeted thickness of HV gate oxide 252 layer may be achieved.
  • the parameters may include time duration, temperature, pressure, reactants etc. of the RTO, furnace oxidation, and CVD processes.
  • HV gate oxide 252 layer remains in the finished device as HV gate oxide 252 of HV_MOS transistor 214 .
  • desirable thickness of HV gate oxide 252 layer may be targeted to be approximately between 100 ⁇ acute over ( ⁇ ) ⁇ to 200 ⁇ acute over ( ⁇ ) ⁇ , or other thicknesses. It will be understood that such a range is merely illustrative and is not meant to be limiting.
  • HV gate oxide 252 layer may be formed, in the processes described in FIG. 2H , to be thicker than the desirable thickness.
  • HV gate oxide 252 layer may be removed in later processes, to achieve the desirable or final thickness of HV gate oxide 252 of HV_MOS transistor 214 . As previously explained, the process of forming HV gate oxide 252 layer may have very little to substantially no effect on NV gate stack 236 in the first region 206 .
  • a patterned mask layer 254 may be formed on or overlying at least NV gate stack 236 in the first region 206 and HV gate oxide 252 layer over channel 218 of HV_MOS 214 in the second region 208 (step 116 ).
  • the patterned mask layer 254 may include a photoresist layer patterned using standard lithographic techniques, a hard mask layer, or other techniques known in the art.
  • HV gate oxide 252 layer overlying at least channels 218 of I/O_MOS 215 and LV_MOS 212 in the second region 208 of substrate 204 is removed (step 116 ).
  • substrate surface 216 in I/O_MOS 215 and LV_MOS 212 areas may be exposed.
  • HV gate oxide 252 layer may be removed in a wet clean process using a 10:1 buffered oxide etch (BOE) containing a surfactant.
  • BOE buffered oxide etch
  • the wet clean process can be performed using a 20:1 BOE wet etch, a 50:1 hydrofluoric (HF) wet etch, or any other similar hydrofluoric-based wet etching chemistry.
  • HV gate oxide 252 layer may be removed using a plasma etch process.
  • an oxidation process is performed to oxidize the remaining portion of second cap layer 232 b and/or the first cap layer 232 a of multi-layer cap layer 232 , and optionally, a portion of second charge-trapping layer 230 b to form blocking oxide layer 260 overlying second charge-trapping layer 230 b (step 118 ).
  • the oxidation process is adapted to oxidize or consume first cap layer 232 a , or the remaining portion of second cap layer 232 b , or optionally a portion of second charge-trapping layer 230 b to form the blocking oxide layer 260 in the first region while simultaneously oxidizing at least a portion of substrate surface 216 overlaying channels 218 of I/O_MOS 215 and LV_MOS 212 to form I/O gate oxide 256 layer in the second region.
  • the oxidation process may also grow a layer of oxide at or around channel 218 of HV_MOS 214 to increase thickness of HV gate oxide 252 ′ layer.
  • the oxidation process may include in-situ-steam-generation (ISSG), or other radical oxidation processes performed in a batch or single substrate processing chamber with or without an ignition event such as plasma.
  • SISG in-situ-steam-generation
  • blocking oxide layer 260 and I/O gate oxide 256 layer may be grown in a radical oxidation process involving flowing hydrogen (H 2 ) and oxygen (O 2 ) gas into a processing chamber at a ratio to one another of approximately 1:1, or 10:1 for ISSG, without an ignition event, such as forming of a plasma, which would otherwise typically be used to pyrolyze the H 2 and O 2 to form steam.
  • the H 2 and O 2 are permitted to react at a temperature approximately in the range of 700-800° C., or 800-1100° C.
  • radicals such as, an OH radical, an HO 2 radical or an O diradical radicals at a surface of remaining second cap layer 232 b or first cap layer 232 a .
  • the radical oxidation process may be carried out for a duration approximately in the range of 10-15 minutes to effect growth of blocking oxide 260 layer by oxidation and consumption of the multi-layer cap layer 232 and optionally a portion of the second charge-trapping layer 230 b having a thickness of from about 3 nm to about 4.5 nm, and I/O gate oxide 256 layer having a thickness of from about 3 nm to about 7 nm.
  • targeted thickness of I/O gate oxide 256 layer may be achieved.
  • the parameters may include time duration, temperature, pressure, reactants etc. of the ISSG or other radical oxidation processes.
  • at least a portion of I/O gate oxide 256 layer remains in the finished device as I/O gate oxide 256 of I/O_MOS transistor 215 .
  • desirable thickness of I/O gate oxide 252 layer may be targeted to be approximately between 30 ⁇ acute over ( ⁇ ) ⁇ to 70 ⁇ acute over ( ⁇ ) ⁇ , or other thicknesses. It will be understood that such a range is merely an example and is not meant to be limiting.
  • I/O gate oxide 256 layer may be formed, in the processes described in FIG. 2J , to be thicker than the desirable thickness. Excessive I/O gate oxide 256 layer may be removed in later processes, to achieve the desirable or final thickness of I/O gate oxide 256 of I/O_MOS transistor 215 .
  • a patterned mask layer 258 may be formed on or overlying at least NV gate stack 236 in the first region 206 , HV gate oxide 252 ′ layer over channel 218 of HV_MOS 214 , and I/O gate oxide 256 layer over channel 218 of I/O_MOS 215 in the second region 208 (step 120 ).
  • the patterned mask layer 258 may include a photoresist layer patterned using standard lithographic techniques, a hard mask layer or other techniques known in the art.
  • the same radical oxidation process may also add thickness to I/O gate oxide 256 ′ layer at or around I/O_MOS 215 area, HV gate oxide 252 ′′ layer at or around HV_MOS 214 area, and blocking oxide 260 ′ layer of NV gate stack 236 .
  • targeted thickness of LV gate oxide 262 layer may be achieved.
  • the parameters may include time duration, temperature, pressure, reactants etc. of the ISSG or other radical oxidation processes. As will be explained in later sections, at least a portion of LV gate oxide 262 layer remains in the finished device as LV gate oxide 262 of LV_MOS transistor 212 .
  • LV gate oxide 262 layer may be formed by RTO or conventional furnace oxidation. In such cases, thicknesses of blocking oxide 260 layer of NV gate stack 236 may not be affected. In some embodiments a thin high dielectric constant or high-k dielectric material can be used in place of the silicon dioxide.
  • the high-k dielectric material may include, but is not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide deposited by, for example, atomic layer deposition (ALD), physical vapor deposition (PVD), a chemical vapor deposition (CVD), a low pressure CVD (LPCVD) or a plasma enhanced CVD (PECVD) process.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • LPCVD low pressure CVD
  • PECVD plasma enhanced CVD
  • forming LV gate oxide 262 layer may also encompass the formation of a nitrogen-rich silicon oxide film by providing a nitridizing atmosphere to substrate 204 .
  • nitrogen-rich may be understood to mean a peak nitrogen concentration of between approximately 0.5 to 3.5 atomic percent (at %) or higher.
  • nitridizing atmosphere may be understood to mean an atmosphere that provides for the formation of nitrogen-rich silicon oxide films.
  • providing the nitridizing atmosphere to the substrate 204 may encompass introducing nitrous oxide (N 2 O) into the torch region at a first temperature.
  • this first temperature may be selected to be sufficiently high to promote an exothermic reaction which forms the nitridizing atmosphere.
  • nitrogen-rich oxide film may also be formed in I/O gate oxide 256 ′ layer, HV gate oxide 252 ′′ layer, and/or blocking oxide 260 ′ layer as they are also exposed to the “nitridizing atmosphere” during step 122 .
  • Nitrogen-rich or nitrided silicon oxide films may provide a barrier to diffusion of dopants such as boron, in subsequent fabrication processes. Hence threshold voltage degradation of transistors formed using nitrogen-rich silicon oxide gate dielectrics may be reduced. Additionally, such nitrided silicon oxide films may have improved hot carrier resistance and dielectric integrity.
  • HV gate oxide 252 ′′ is thicker than I/O gate oxide 256 ′
  • I/O gate oxide 256 ′ is thicker than LV gate oxide 262 .
  • the fabrication process may progress to high-K dielectric formation and metal gate formation (HKMG process flow) that are described in FIG. 7 .
  • FIG. 3 is a flow chart that describes a first alternative embodiment 300 to fabricate the embedded SONOS based NVM device, as best illustrated in FIG. 2L .
  • the fabrication process begins in a similar manner as the embodiment described in FIGS. 1 and 2A-2E (steps 102 - 108 ).
  • tunnel dielectric 228 layer, first and second charge-trapping layers 230 a and 230 b , first and second cap layers 232 a and 232 b , sacrificial oxide layer 234 are sequentially formed overlying substrate 204 in the first and second regions 206 and 208 of substrate 204 . Referring to FIGS.
  • sacrificial nitride layer 402 is formed overlying sacrificial oxide layer 234 (step 302 ).
  • sacrificial nitride layer 402 is formed by conventional process, such as CVD using N 2 O/NH 3 and DCS/NH 3 gas mixtures or PVD, to achieve a thickness of from about 50 ⁇ -200 ⁇ .
  • a patterned mask layer 404 is formed on or overlying the sacrificial nitride layer 402 , and referring to FIG. 4B , sacrificial nitride layer 402 , sacrificial oxide layer 234 , multi-layer cap layer 232 and multi-layer charge-trapping layer 230 , and tunnel dielectric layer 228 are etched or patterned to form NV gate stack 236 .
  • NV gate stack 236 is disposed at least overlying channel 224 of NVM transistor 226 in the first region 206 . The etching or patterning process may further remove various dielectric layers of NV gate stack 236 from the second region 208 of substrate 204 (step 304 ).
  • the patterned mask layer 404 may include a photoresist layer patterned using standard lithographic techniques, and the NV gate stack 236 layers in second region 208 may be etched or removed using a dry etch process including one or more separate steps to stop on a surface of the tunnel dielectric 228 or pad oxide 209 .
  • a cleaning process is performed to removes any oxide, such as oxide in tunnel dielectric 228 and/or pad oxide 209 , remaining in the first region 206 beyond NV gate stack 236 , and in second region 208 to prepare substrate 204 for HV gate oxide growth (step 306 ).
  • pad oxide 109 is not remove entirely or at all (shown as dotted line in FIG. 4B ).
  • residual tunnel dielectric 228 and/or pad oxide 209 may be removed in a wet clean process using a 10:1 buffered oxide etch (BOE) containing a surfactant.
  • BOE buffered oxide etch
  • the wet clean process can be performed using a 20:1 BOE wet etch, a 50:1 hydrofluoric (HF) wet etch, a pad etch, or any other similar hydrofluoric-based wet etching chemistry.
  • a 20:1 BOE wet etch a 50:1 hydrofluoric (HF) wet etch
  • a pad etch or any other similar hydrofluoric-based wet etching chemistry.
  • HV gate oxide 252 layer is formed over substrate 204 (step 306 ), either directly or indirectly.
  • the process starts when pad oxide 209 is completely or partially removed in a pad oxide preclean process.
  • HV gate oxide 252 layer is formed by a rapid thermal dry oxidation (RTO) process, a conventional or furnace oxidation process, a chemical vapor deposition process (CVD), or other non-radical oxide forming processes known in the art, or a combination thereof.
  • RTO rapid thermal dry oxidation
  • CVD chemical vapor deposition process
  • HV gate oxide 252 layer may be grown to a thickness of from about 100 ⁇ -200 ⁇ .
  • remaining pad oxide 209 after the pre-clean process may become part of the later grown HV gate oxide 252 layer.
  • tunnel dielectric 228 may have an unexpectedly thick structure which may adversely affect the operations of the eventual NVM transistor 226 .
  • the electrical performance of NVM transistor 226 such as programming/erasing by tunneling, may be degraded.
  • moisture in STIs 202 oxide may also creep in under NV gate stack 236 and increase the tunnel dielectric 228 thickness.
  • Both these mechanisms may lead to significant increase in tunnel dielectric 228 thickness, resulting in degradation of the tunneling of electrons/holes during programming/erasing, and the Program/Erase Vts and Vt window of the eventual NVM transistor 206 .
  • the relatively thick sacrificial nitride 402 (50 ⁇ -200 ⁇ ) disposed at the top of NV gate stack 236 may help minimize or eliminate the encroachment of oxidizing species, such as H 2 O, in or around tunnel dielectric 228 , and therefore prevent any degradation of the electrical characteristics of the eventual NVM transistor 226 .
  • sacrificial nitride 402 is removed from NV gate stack 236 (step 308 ).
  • sacrificial nitride 402 may be removed by wet etch using hot phosphoric acid.
  • the sacrificial nitride 402 etch is extremely selective to oxide, and may remove very small amount of oxide from NV gate stack 236 and HV gate oxide 252 layer.
  • the fabrication process may continue on to remove the sacrificial oxide 234 and at least a top portion of second cap layer 232 b , as best illustrated in FIG. 4D or FIG. 2G (step 112 ). Subsequently, the fabrication process may follow the sequence, steps 116 - 122 , as shown in FIG. 1 to complete the triple gate embodiment of embedded SONOS based NVM device in FIG. 2L .
  • FIG. 5 is a flow chart that describes a second alternative embodiment 500 to fabricate the embedded SONOS based NVM device, as best illustrated in FIG. 2L .
  • the fabrication process begins in a similar manner as the embodiment described in FIGS. 1 and 2A-2B (steps 102 - 104 ).
  • the main difference of this embodiment is that HV gate oxide 252 layer is formed prior to the formation of dielectric layers of NV gate stack 236 .
  • HV gate oxide 252 layer is formed on substrate 204 (step 602 ), either directly or indirectly.
  • the process starts when pad oxide 209 is completely removed in a pad oxide preclean process.
  • the pad oxide preclean may involve, for example a wet clean process using a 10:1 buffered oxide etch (BOE) containing a surfactant.
  • BOE buffered oxide etch
  • the wet clean process can be performed using a 20:1 BOE wet etch, a 50:1 hydrofluoric (HF) wet etch, a pad etch, or any other similar hydrofluoric-based wet etching chemistry.
  • HV gate oxide 252 layer may be formed by a rapid thermal dry oxidation (RTO) process, a conventional or furnace oxidation process, a rapid and radical wet oxidation process such as in-situ steam generation (ISSG), a chemical vapor deposition process (CVD), or other oxide forming processes known in the art, or a combination thereof.
  • RTO rapid thermal dry oxidation
  • ISSG in-situ steam generation
  • CVD chemical vapor deposition process
  • other oxide forming processes known in the art or a combination thereof.
  • radical oxidation processes such as ISSG, may be employed as it will not oxidize nitride in NV gate stack 236 , as in step 114 of FIG. 1 or step 306 of FIG. 3 .
  • the oxidation process starts with dry RTO performed in a batch or single substrate processing chamber with or without an ignition event such as plasma.
  • the device is subjected to a rapid thermal oxidation process involving flowing oxygen (O 2 ) gas into a processing chamber.
  • the O 2 gas is permitted to react at a temperature approximately in the range of 1000-1100° C. at a pressure approximately in the range of 0.5-5 Torr. to form HV gate oxide 252 layer.
  • HV gate oxide 252 layer is grown, by oxidizing silicon substrate 204 , on at least a portion of the surface 216 of substrate 204 .
  • RTO process may be substituted with a rapid molecular oxidation (dry or wet) which is a non-radical oxidation process.
  • HV gate oxide 252 layer is formed by a wet rapid and radical oxidation process, such as in-situ steam generation (ISSG). The wet rapid and radical oxidation may be performed in a batch or single substrate processing chamber with or without an ignition event such as plasma.
  • HV gate oxide 252 layer may be grown in a wet radical oxidation process involving flowing hydrogen (H 2 ) and oxygen (O 2 ) gas into a processing chamber at a ratio to one another of approximately 1:1 without an ignition event, such as forming of a plasma, which would otherwise typically be used to pyrolyze the H 2 and O 2 to form steam.
  • the H 2 and O 2 are permitted to react at a temperature approximately in the range of 1000-1100° C. at a pressure approximately in the range of 0.5-10 Torr. to form radicals, such as, an OH radical, an HO 2 radical or an O diradical radicals.
  • the oxidation process is carried out for a duration approximately in the range of 5-10 minutes for a single substrate using an ISSG process, or 30-120 minutes for a batch furnace process to effect growth of HV gate oxide 252 layer. During the period, HV gate oxide 252 layer is grown in both the first and second regions 206 and 208 .
  • wet rapid and radical oxidation may be substituted by processes such as chemical vapor deposition (CVD), or other radical oxidation processes performed in a batch or single substrate processing chamber with or without an ignition event such as plasma as long as oxide will be grown or deposited to form HV gate oxide 252 layer.
  • CVD chemical vapor deposition
  • targeted thickness of HV gate oxide 252 layer may be achieved.
  • the parameters may include time duration, temperature, pressure, reactants etc. of the RTO, ISSG, furnace oxidation, and CVD processes.
  • HV gate oxide 252 layer remains in the finished device as HV gate oxide 252 of HV_MOS transistor 214 .
  • desirable thickness of HV gate oxide 252 layer may be targeted to be approximately between 100 ⁇ acute over ( ⁇ ) ⁇ -200 ⁇ acute over ( ⁇ ) ⁇ , or other thicknesses. It will be understood that such a range is merely illustrative and is not meant to be limiting.
  • HV gate oxide 252 layer may be formed, in the processes described in FIG. 6A , to be thicker or thinner than the desirable thickness. Excessive or inadequate HV gate oxide 252 layer may be removed or added in later processes to achieve the desirable or final thickness of HV gate oxide 252 of HV_MOS transistor 214 .
  • HV gate oxide 252 layer may be formed adjacent to at least a bottom portion of pad oxide 209 and substrate 204 .
  • pad oxide 209 is not completely removed during the pad oxide preclean process, as previously described.
  • the pad oxide preclean process is omitted.
  • the pad oxide preclean process is carried out but does not remove the entirety of pad oxide 209 .
  • HV gate oxide 252 layer may then be formed in the aforementioned processes at least over the remaining or bottom layer of pad oxide 209 . In both embodiments, remaining pad oxide 209 becomes a part of the finished HV gate oxide 252 layer.
  • operation parameters of the pad oxide preclean process and the gate oxide formation process may be configured to achieve the combined thickness of HV gate oxide 252 layer.
  • the combined thickness of HV gate oxide 252 layer may be greater or less than the desirable or final gate thickness, and excessive HV gate oxide 252 layer may be removed or added in later processes.
  • pad oxide 209 and HV gate oxide 252 layer are formed separately and individually, they may be different chemically, in stoichiometric composition and ratio, and/or physically. Moreover, there may be an interface (not shown) between pad oxide 209 and the later grown/deposited HV gate oxide 252 layer in the combined structure.
  • a patterned tunnel mask 220 is formed on or overlying HV gate oxide 252 layer, ions (represented by arrows 222 ) of an appropriate, energy and concentration are implanted through a window or opening in tunnel mask 220 to form a channel 224 for NVM transistor 226 in first region 206 , and tunnel mask 220 and HV gate oxide 252 layer in at least the window removed (step 604 ).
  • Tunnel mask 220 may include a photoresist layer, or a hard mask formed, from a patterned nitride or silicon-nitride layer. In the embodiment that multiple NVM transistors 226 are present in first region 206 , multiple channels 224 may be formed simultaneously.
  • channel 224 for NVM transistor 226 may be a deep indium doped channel implanted with indium (In) at an energy of from about 50 kilo-electron volts (keV) to about 500 keV, and a dose of from about 5e11 cm ⁇ 2 to about 1e13 cm ⁇ 2 to form an n-channel NVM transistor 226 .
  • implanting indium to form channel 224 of NVM transistor 226 improves the threshold voltage (V T ) uniformity of the finished NVM transistor from a sigma of V T from about 150 millivolts (mV) to about 70-80 mV.
  • a shallow doped channel is implanted with arsenic at an energy about 20 keV and a dose of from about 5e11 cm ⁇ 2 to about 1e13 cm ⁇ 2 at channel 224 .
  • BF 2 may be implanted to form an N-channel NVM transistor, or arsenic or phosphorous implanted to form a P-channel NVM transistor.
  • channel for NVM transistor 226 may also be formed concurrently with channels 218 of the MOS transistors 212 , 214 , 215 .
  • channel(s) 224 of N-channel NVM transistor(s) and P-channel NVM transistor(s) may be formed simultaneously, or separately.
  • HV gate oxide 252 layer in the window or opening in the tunnel mask 220 may be removed, for example in a wet clean process using a 10:1 buffered oxide etch (BOE) containing a surfactant.
  • BOE buffered oxide etch
  • the wet clean process can be performed using a 20:1 BOE wet etch, a 50:1 hydrofluoric (HF) wet etch, a pad etch, or any other similar hydrofluoric-based wet etching chemistry.
  • tunnel mask 220 includes photoresist material may be ashed or stripped using oxygen plasma.
  • hard tunnel mask 220 may be removed using a wet or dry etch process.
  • the surface 216 of wafer 204 is cleaned or precleaned, a number of dielectric layers formed or deposited, a mask formed on or overlying the dielectric layers, and the dielectric layers etched to form a NV gate stack 236 in first region 206 (step 108 ).
  • the preclean may be a wet or dry process. In one embodiment, it may be a wet process using HF or standard cleans (SC1) and (SC2), and is highly selective to the material of wafer 204 .
  • SC1 is typically performed using a 1:1:5 solution of ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 O) at 30° C. to 80° C. for about 10 minutes.
  • SC2 is a short immersion in a 1:1:10 solution of HCl, H 2 O 2 and H 2 O at about 30° C. to 80° C.
  • a number dielectric layers including tunnel dielectric 228 , multi-layer charge-trapping layer 230 , multi-layer cap layer 232 , sacrificial oxide 234 may be disposed in the first and second regions 206 and 208 (step 108 ).
  • tunnel dielectric 228 is formed over HV gate oxide 252 layer, instead of pad oxide 209 in the second region 208 .
  • a mask 280 may be formed on or overlying the dielectric layers, and the dielectric layers may then be etched to form NV gate stack 236 in the first region 206 (step 110 ′).
  • the process step is very similar to step 110 in FIG. 1 .
  • the patterning step may stop at a top surface of HV gate oxide 252 layer, which was already formed at least in the second region 208 , instead of pad oxide 209 .
  • HV gate oxide 252 layer will become at least a portion of HV gate oxide 252 of the eventual HV_MOS transistor 214 , as illustrated in FIG. 8J .
  • the fabrication process may continue on to remove the sacrificial oxide 234 and at least a top portion of second cap layer 232 b , as best illustrated in FIG. 2G (step 112 ). Subsequently, the fabrication process may follow the sequence, steps 116 - 122 , as shown in FIG. 1 to complete the triple gate embodiment of embedded SONOS based NVM device in FIG. 2L .
  • FIG. 7 is a flowchart illustrating an embodiment of subsequent steps to the embodiments in FIGS. 1, 3, and 5 for continuing fabrication of a memory cell or array including an embedded SONOS or MONOS based NVM transistor and MOS transistors.
  • fabrication steps 702 to 720 describe the formation of high-K dielectric layer and metal gates for NVM transistor 226 and/or MOS transistors 214 , 215 , and 212 of NVM device 800 .
  • the embodiments disclosed in FIGS. 1, 3, and 5 are some of the fabrication methods to yield the embodiment of embedded NVM transistor with a triple gate structure (MOS transistors), as best illustrated in FIG. 2L . It will be the understanding that embodiments disclosed in FIGS. 7 and 8A-8J are applicable to same or similar structures as illustrated in FIG. 2L , and are not limited to the fabrication methods disclosed in FIGS. 1, 3, and 5 .
  • a high dielectric constant or high-K dielectric material or layer 802 is formed or deposited on or over NV gate stack 236 of NVM transistor 206 , in first region 206 and in second region 208 (step 702 ).
  • the deposition step may concurrently form a multilayer blocking dielectric in NVM transistor 226 , multilayer gate dielectric in MOS transistors 214 , 215 , and 212 .
  • the multilayer blocking dielectric may include high-K dielectric layer 802 and blocking oxide layer 260 ′ in NVM transistor 206 .
  • the multilayer gate dielectric may include high-k dielectric layer 802 and gate oxide 252 ′′, 256 ′ and 262 in HV_MOS transistor 214 , I/O_MOS transistor 215 , and LV_MOS transistor 212 , respectively.
  • the high-K dielectric layer 802 may include, but is not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide deposited to a physical thickness between about 3.0 nm and about 8.0 nm or other thicknesses by, for example, atomic layer deposition (ALD), physical vapor deposition (PVD), a chemical vapor deposition (CVD), a low pressure CVD (LPCVD) or a plasma enhanced CVD (PECVD) process.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • LPCVD low pressure CVD
  • PECVD plasma enhanced CVD
  • high-K dielectric layer 802 may increase the overall thickness of multilayer blocking dielectric (blocking oxide 260 ′ layer plus high-K dielectric layer 802 ) of NVM transistor 226 .
  • the additional thickness, physical and/or electrical may affect adversely or degrade the performance of NVM transistor 226 .
  • blocking oxide 260 layer may be primarily formed concurrently with I/O gate oxide 256 of I/O_MOS 215 .
  • cap layer 232 may be a pure nitride layer and may contain approximately 0% oxygen.
  • one or more etching or wet clean processes may be performed on blocking oxide 260 ′ layer, HV gate oxide 252 ′′ layer, I/O gate oxide 256 ′ layer, or LV gate oxide 262 layer to achieve respective desired gate dielectric (gate oxide layer plus high-K dielectric layer 802 ) thickness(es).
  • high-K dielectric layer 802 is deposited overlying NV stack 236 of NVM transistor 226 , and then removed.
  • Transistors, in which high-K metal gate to be formed in first and second regions 206 and 208 may be protected by a mask (not shown in FIG. 8A ) during the high-K dielectric layer 802 removal.
  • a polysilicon or poly gate layer 803 is deposited or formed over substantially the entire surface of the substrate 204 in both the first and second regions 206 and 208 , and all layers and structures formed thereon (step 704 ).
  • polysilicon gate layer 803 may be formed by chemical vapor deposition (CVD) to a thickness of from about 30 nm to about 100 nm, or other appropriate thicknesses.
  • CVD chemical vapor deposition
  • polysilicon gate layer 803 may be formed by other deposition methods or fabrication methods known in the art.
  • a thin layer of titanium nitride (not shown in this figure) is deposited over high-K dielectric layer 802 , and poly gate layer 803 may be deposited overlying the thin titanium nitride layer.
  • the titanium nitride deposition is optional, and may facilitate subsequent poly gate layer patterning or removal.
  • polysilicon layer 803 may be deposited on blocking dielectric layer 206 ′ of NVM transistor 226 instead.
  • a patterned photoresist mask (not shown) formed using standard lithographic techniques and polysilicon gate layer 803 is etched to stop on surfaces of the high-K dielectric layer 802 , thereby forming dummy or sacrificial polysilicon gates 804 of NVM transistor 226 and MOS transistors 214 , 215 , and 212 (step 706 ).
  • polysilicon gate layer 803 may be etched using standard polysilicon etch chemistries, such as CHF 3 or C 2 H 2 or HBr/O 2 which are highly selective to the underlying high-K dielectric layer 802 .
  • a first spacer layer is deposited and etched to form first sidewall spacers or offset spacers 808 adjacent to dummy or sacrificial polysilicon gates 804 of MOS transistors 212 , 215 , 214 , and NVM transistor 226 (step 706 ).
  • the first spacer layer may include silicon oxide or silicon nitride, deposited to a thickness of from about 10 nm to about 30 nm, using any known CVD technique as described herein.
  • one or more lightly-doped drain (LDD) extensions may be implanted adjacent to and extend under first sidewall spacers 808 of one or more of MOS transistors 212 , 214 , 215 (step 706 ).
  • MOS LDDs are formed by implanting an appropriate ion species at an appropriate energy to an appropriate concentration.
  • drain extensions of P-type LV_MOS transistor 212 , or any other P-type MOS transistors in the second region 208 may be formed by forming a photoresist mask through which selected transistors are exposed and implanting boron ions (BF 2 ) at an energy of from about 10 to about 100 kilo-electron volts (keV), and a dose of from about 1e12 cm ⁇ 2 to about 5e14 cm ⁇ 2 through the photoresist mask (not shown).
  • boron ions boron ions
  • pocket or halo implants for P-type LV_MOS transistor 212 or other P-type MOS transistors may be done through the same photoresist mask, by implanting Arsenic or Phosphorus at energy of 20 to 70 kilo-electron volts (KeV) and a dose of 2e12 cm ⁇ 2 to about 5e12 cm ⁇ 2 .
  • Arsenic or Phosphorus at energy of 20 to 70 kilo-electron volts (KeV) and a dose of 2e12 cm ⁇ 2 to about 5e12 cm ⁇ 2 .
  • MOS LDDs of N-type transistors such as N-type I/O_MOS transistor 215 and HV_MOS transistor 214 may be formed by implanting arsenic or phosphorus at energy of from about 10 to about 100 kilo-electron volts (keV), and a dose of from about 1e12 m ⁇ 2 to about 5e14 cm ⁇ 2 , also through an appropriately patterned photoresist mask.
  • Halo or pocket implants for the N-type MOS transistors may also be done through this mask using Boron (BF 2 ) at energy of 5 to about 50 kilo-electron volts and a dose of 1e12 cm ⁇ 2 to 5e12 cm ⁇ 2 .
  • BF 2 Boron
  • polysilicon etch (step 706 ) may be stopped at high-K dielectric layer 802 .
  • ONO layers are removed from the second region 208 . However, there may be ONO layers remaining in the first region 206 , especially between NVM transistors 226 .
  • step 702 After high-K dielectric layer 802 deposition (step 702 ), polysilicon gate layer 803 deposition (step 704 ) and dummy polysilicon gate 804 patterning (step 706 ), there may still be high-K dielectric and ONO materials remaining at least in the source/drain areas of NVM transistors 226 .
  • these remaining films in between NVM transistors 226 need to be removed so that the low energy NVM LDD implants (in subsequent step 706 ) may reach the required depths. Otherwise, in some embodiments, the junctions may be too shallow with insufficient doping which may degrade NVM transistor 226 performance.
  • remaining high-K dielectric layer 802 and ONO films in at least the first region 206 may be removed using the same photoresist mask (not shown) that is used for the NVM LDD implants 820 in subsequent step 708 .
  • the NVM LDD mask is set up and used to open NVM transistors 226 to implants.
  • dry or wet etch may be done to remove remaining high-K dielectric layer 802 and remaining ONO film. The etch may stop at the tunnel oxide 228 of NVM transistors 226 , or all the way to the substrate surface 216 . In some embodiments, the dry or wet etch may also be used to remove any remaining high-K dielectric layer 802 or ONO film beyond NVM transistors 226 in the second region 208 .
  • NVM LDD mask (not shown) formed over the substrate 204 , lightly-doped drain extensions 811 are implanted, adjacent to the NVM transistor 206 , SONOS pocket or halo implants extending partially into the channel region 224 under the gate stack 236 of NVM transistor 226 implanted.
  • the NVM LDD implants 811 and first sidewall spacers 808 for NVM transistor 226 may be formed using techniques substantially the same as those described above with respect to the MOS LDD implants and first sidewall spacers 808 .
  • NVM LDD implants 811 may be formed by an angled implant of, for example, arsenic or phosphorous at an energy of from about 5 to about 25 kilo-electron volts (keV), and a dose of from about 5e12 cm ⁇ 2 to about 2e14 cm ⁇ 2 .
  • pocket or halo implants may be formed by implanting (BF 2 ) with energy of 10 to 30 kilo-electron volts and a dose of 1e12 cm ⁇ 2 to 3e12 cm ⁇ 2 .
  • second spacer layer is deposited and etched to form second sidewall spacers 810 adjacent to first sidewall spacers 808 , of the NVM transistor 226 and MOS transistors 212 , 214 , and 215 (step 710 ).
  • source and drain implants are performed to form source and drain regions 830 for all transistors and a silicide process performed (step 710 ).
  • a hard mask HM
  • a silicon-germanium (SiGe) layer 813 may be deposited and etched, and the hard mask removed to form a strain inducing layer over the S/D regions of P-type LV_MOS 212 , or other P-type transistors in first and second regions.
  • silicide regions 812 may be formed on exposed source and drain regions 830 .
  • silicide regions 812 may also be formed over one or more dummy polysilicon gate 804 in the first and second regions 206 and 208 .
  • the silicide process may be any commonly employed in the art, typically including a pre-clean etch, cobalt or nickel metal deposition, anneal and wet strip.
  • rapid thermal annealing RTA
  • a cleaning process may be performed to remove any remaining tunnel oxide layer 228 and/or pad oxide layer 209 on substrate surface 216 beyond the formed transistors in the first and second regions 206 and 208 .
  • the method further includes forming a stress inducing liner or layer 814 , such as a stress inducing nitride layer, and depositing an interlevel dielectric (ILD) layer 816 over substantially the entire surface 216 of substrate 204 and all layers and structures formed thereon, and the ILD layer 816 planarized, for example, using a chemical mechanical polishing (CMP) process (step 712 ).
  • a stress inducing liner or layer 814 such as a stress inducing nitride layer
  • ILD interlevel dielectric
  • the stress inducing layer 814 may include, a compressive or tensile nitride layer formed using a plasma enhanced chemical vapor deposition (PECVD) or a Bis-TertiaryButylAmino Silane (BTBAS) nitride layer, deposited or grown to a thickness of from about 30 nm to about 70 nm or other thicknesses, using any known technique including chemical vapor deposition.
  • the ILD layer 816 may include, for example, silicon oxide, deposited or grown to a thickness of from about 0.5 ⁇ m to about 1.0 ⁇ m or other thicknesses, using any known CVD technique as described above.
  • a chemical mechanical planarization (CMP) process may be performed to expose dummy polysilicon gates 804 in NVM transistor 226 in the first region 206 , and MOS transistors 212 , 214 , and 215 in the second region 208 .
  • CMP chemical mechanical planarization
  • a single CMP process is performed to exposed all targeted dummy polysilicon gates 804 . Due to the possible difference in heights, different transistors may have different thicknesses of remaining dummy poly gates 804 after the CMP process step. In another embodiment, due to the potential difference in heights of various transistors, multiple CMP processes may be employed such that all targeted dummy polysilicon gates 804 are exposed.
  • dummy polysilicon gates 804 are removed (step 714 ).
  • dummy polysilicon gates 804 may be removed using standard polysilicon etch methods that are known in the art, which are highly selective to the material of high-K dielectric layer 802 , ILD layer 816 , stress inducing liner 814 , first and second sidewall spacers 808 and 810 .
  • one or more dummy polysilicon gate 804 in NVM transistor 226 and/or MOS transistors 212 , 214 , and 215 may not be removed, in cases wherein a polysilicon gate is preferred over a metal gate.
  • the polysilicon etch may stop at the thin titanium nitride layer (not shown) instead.
  • metal layers 818 of multi-layer metal gates are formed, (step 716 ).
  • the multi-layer metal gates may replace the removed dummy polysilicon gates 804 .
  • first or P+ metal layer 818 a (high work function metal) is deposited over substantially the entire surface of the substrate 204 and all layers and structures formed thereon, a patterned photoresist mask (not shown) formed using standard lithographic techniques and the P+ metal layer etched to remove first or P+ metal layer from N-type NVM transistor(s) in the first region 206 and N-type MOS transistors 212 , 214 , and 215 in the second region 208 , stop on surfaces of the high-K dielectric layer 802 , thereby forming high work function gate 818 a for any P-type NVM transistor(s) and P-type MOS transistor(s), such as P-type LV_MOS transistor 212 in FIG.
  • the P+ metal layer 818 a may include aluminum, titanium or compounds or alloys thereof, deposited to a thickness of from about 20 nm to about 100 nm or other thicknesses, using physical or chemical vapor deposition. In one embodiment, P+ metal layer 818 a may be formed overlying high-K dielectric layers 802 , and optionally on sidewalls, of the openings previously occupied by dummy polysilicon gates 804 . P+ metal layer 818 a formed over N-type MOS transistors may then be removed.
  • second or N+ metal layer 818 b (low work function) is deposited over substantially the entire surface of the substrate 204 , including the previously formed P+ metal layer 818 a , such as around P-type LV_MOS 212 .
  • a patterned photoresist mask (not shown) is then formed and the N+ metal layer 818 b etched to form a non-high or low work function metal gate 818 b for any N-type transistors in the first and second regions 206 and 208 , such as N-type NVM transistor 226 , HV_MOS transistor 214 , and I/O_MOS transistor 215 as best shown in FIG. 8I .
  • N+ metal layer 818 b may be formed overlying high-K dielectric layers 802 , and optionally on sidewalls, of the openings previously occupied by dummy polysilicon gates 804 .
  • the N+ metal layer 818 b may include titanium, lanthanum, aluminum, or compounds or alloys thereof, deposited to a thickness of from about 20 nm to about 100 nm or other thicknesses, using physical or chemical vapor deposition.
  • any N-type transistor may include a low work function metal layer, such as N+ metal layer 818 b
  • any P-type transistor may include a high work function metal layer, such as P+ metal layer 818 a , overlying their respective high-K dielectric layers 802 .
  • N-type NVM transistor 226 may include high work function metal layer, such as P+ metal layer 818 a instead.
  • the incorporation of the high work function metal layer in N-type NVM transistor 226 may provide improved erase performance to the device as it may avoid erase saturation.
  • P+ or N+ metal layer 818 a or 818 b may be deposited overlying the thin titanium nitride layer. Since the titanium nitride layer is very thin, it may not affect the property of the finished metal gates significantly.
  • the sequence of forming and patterning of P+ metal layer 818 a and N+ metal layer 818 b may be reversed.
  • a layer of tantalum nitride is deposited overlying the thin layer of titanium nitride (if present).
  • the thin layer of titanium nitride and tantalum nitride will form a bottom barrier metal layer.
  • the bottom barrier metal layer disposed between P+ or N+ metal layer 818 a or 818 b and high-K dielectric layer 802 is optional.
  • thick gate metal layer is deposited, etched and may be followed by planarization using a CMP process or multiple CMP processes to form thick metal gates 820 , completing the formation of multilayer metal gates for the NVM transistor 226 and all of the MOS transistors 212 , 214 , and 215 (step 718 ).
  • thick gate metal layer may include a conformal layer of aluminum, titanium, titanium-nitride, tungsten or compounds or alloys thereof, overlying its respective P+ metal layer 818 a or N+ metal layer 818 b .
  • Thick gate metal layer 820 may be deposited to a thickness of from about 0.1 ⁇ m to about 0.5 ⁇ m or other thicknesses, using physical or chemical vapor deposition, or other deposition methods known in the art. Due to the potential difference in heights of various transistors and the CMP process steps, there may be difference in finished thick metal gate 820 .
  • NVM transistor 226 may also be referred to as Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) transistor because of the presence of multilayer metal gate (first or second metal layer 818 a or 818 b and thick gate metal layer 820 ). It will be the understanding that SONOS and MONOS are used interchangeably throughout the entire patent document.
  • a second ILD layer 822 may be deposited and contacts (not shown) formed to the source/drain regions and gates for the NVM transistor and all of the MOS transistors.
  • the second ILD layer 822 may include, for example, silicon oxide or silicon nitride, deposited or grown to a thickness of from about 0.5 ⁇ m to about 1 ⁇ m or other thicknesses, using any known CVD as described above.
  • a stress inducing structure 822 in or on the surface 216 of the substrate 204 proximal to, and preferably surrounding, a region of the substrate in which the channel 224 of NVM transistor 226 is formed will reduce the band gap, and, depending on the type of strain, increases carrier mobility. For example, tensile strain, in which inter-atomic distances in the crystal lattice of the substrate 204 are stretched, increases the mobility of electrons, making N-type transistors faster. Compressive strain, in which those distances are shortened, produces a similar effect in P-type transistors by increasing the mobility of holes. Both of these strain induced factors, i.e., reduced band gap and increased carrier mobility, will result in faster and more efficient programming of NVM transistor 226 .
  • the stress inducing structure 822 may also be formed over one or more of the MOS transistor (HV, I/O, or LV_MOS) to induce strain in the channel(s) 218 of the MOS transistor(s) 212 , 214 , 215 .
  • the MOS transistor HV, I/O, or LV_MOS
  • HV_MOS 214 may require a relatively thick HV gate dielectric layer (HV gate oxide 252 ′′ plus high-K dielectric layer 802 ) that may have a combined thickness of from about 110 ⁇ -160 ⁇ .
  • the final thickness of HV gate oxide 252 ′′ may be achieved by the RTO or furnace oxidation process in step 114 (illustrated in FIG. 2H ). Subsequently, the thickness of HV gate oxide 252 ′′ may be further enhanced possibly by dual oxidation process in step 118 (illustrated in FIG. 2K ), and by the subsequent LV gate oxide formation in step 122 (illustrated in FIG. 2J ), and modified by wet cleaning process(es).
  • I/O gate dielectric layer (I/O gate oxide 256 ′ plus high-K dielectric layer 802 ) may include a thickness of about 30 ⁇ -70 ⁇ , to operate potentially of I/O voltages in a range of 1.6 V-3.6 V. As previously described, the final thickness of I/O gate oxide 256 ′ is achieved by the dual oxidation process in step 118 (illustrated in FIG.
  • FIG. 9 is a representative block diagram illustrating embedded SONOS or MONOS based NVM device 800 , as fabricated in FIGS. 1 to 8I .
  • embedded SONOS or MONOS based NVM device 800 is formed in a single semiconductor die or substrate 900 .
  • the semiconductor die or substrate 900 is at least divided into the first region 206 for NVM transistors 226 and the second region 208 for MOS transistors 212 , 214 , 215 .
  • 2T memory gate/select gate
  • the second region 208 may be further divided into HV_MOS area 902 , I/O_MOS area 904 , and LV_MOS area 906 .
  • there may be system-on-chip (SOC) devices, such as micro-controllers, touch screen controllers, and smart cards, logic devices, microprocessor, other semiconductor based devices in the second region 208 .
  • SOC system-on-chip
  • embedded SONOS or MONOS based NVM device 800 may include other devices, such as processors, power circuits, etc.
  • the first and second regions 206 and 208 may be overlapping, and the HV_MOS area 902 , I/O_MOS area 904 , and LV_MOS area 906 may be overlapping.
  • first region 206 and the HV_MOS area 902 , I/O_MOS area 904 , and LV_MOS area 906 may be located in any area of single substrate 900 , and may be made up of various different regions.
  • HV_MOS 214 may be provided with a high voltage in a range of 4.5 V-12 V in order to program and/or erase NVM transistors in the first region.
  • I/O_MOS may be coupled to I/O interface and provided with an operation voltage in a range of 1.6 V-3.6 V.
  • LV_MOS 212 may be provided with an operation voltage in a range of 0.8 V-1.4 V for various operations and connections.

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