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US20190013214A1 - Package structure and manufacturing method thereof - Google Patents

Package structure and manufacturing method thereof Download PDF

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Publication number
US20190013214A1
US20190013214A1 US15/644,831 US201715644831A US2019013214A1 US 20190013214 A1 US20190013214 A1 US 20190013214A1 US 201715644831 A US201715644831 A US 201715644831A US 2019013214 A1 US2019013214 A1 US 2019013214A1
Authority
US
United States
Prior art keywords
die
encapsulant
semiconductor die
package structure
structure according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/644,831
Other languages
English (en)
Inventor
Han-Wen LIN
Hung-Hsin Hsu
Shang-Yu Chang Chien
Nan-Chun Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Powertech Technology Inc
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to US15/644,831 priority Critical patent/US20190013214A1/en
Assigned to POWERTECH TECHNOLOGY INC. reassignment POWERTECH TECHNOLOGY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSU, HUNG-HSIN, CHANG CHIEN, SHANG-YU, LIN, HAN-WEN, LIN, NAN-CHUN
Priority to TW106130583A priority patent/TWI662635B/zh
Priority to CN201710845069.8A priority patent/CN109243981B/zh
Publication of US20190013214A1 publication Critical patent/US20190013214A1/en
Priority to US16/724,387 priority patent/US10796931B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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Definitions

  • the present invention generally relates to a package structure, in particular, to a manufacturing method of a package structure using sacrificial structures for wire bonding.
  • the invention provides a package structure and a manufacturing method thereof, which uses sacrificial structures to fix the location of a wire for wire bonding.
  • the method effectively reduces the size and manufacturing cost of the package, and overcomes the issue of wafer or panel warpage.
  • the invention provides a manufacturing method of a package structure.
  • the method includes at least the following steps.
  • a carrier is provided.
  • a semiconductor die and a sacrificial structure are disposed on the carrier.
  • the semiconductor die is electrically connected to bonding pads on the sacrificial structure through a plurality of conductive wires.
  • As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires.
  • the carrier is debonded, and the sacrificial structure is removed through a thinning process to reveal the bonding pads or the conductive wires.
  • a redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.
  • the invention further provides a package structure including an encapsulant, a stacked die, a plurality of bonding pads, a plurality of conductive wires, and a redistribution layer.
  • the encapsulant has a top surface and a bottom surface opposite to the top surface.
  • the stacked die is embedded in the encapsulant.
  • the bonding pads are embedded in the encapsulant, wherein the bonding pads are exposed on a top surface of the encapsulant.
  • the conductive wires are embedded in the encapsulant, wherein the stacked die is electrically connected to the bonding pads through the conductive wires.
  • the redistribution layer is disposed on the stacked die and on the top surface of the encapsulant, wherein the redistribution layer is electrically connected to the stacked die through the bonding pads and the conductive wires.
  • a sacrificial structure is used to fix the position of the conductive wires.
  • the precise location of the wire or weld may be provided for further connection.
  • a thickness of the semiconductor die may be effectively controlled during the thinning process, thus an overall size of the package structure may be reduced.
  • an area ratio between the dies and the encapsulant is decreased.
  • the issue of wafer or panel warpage may be resolved.
  • the simplicity of the manufacturing process of the package structure may be realized, thereby reducing the manufacturing cost.
  • FIG. 1A to FIG. 1G are schematic cross-sectional views illustrating a manufacturing method of a package structure according to an embodiment of the invention.
  • FIG. 2A to FIG. 2G are schematic cross-sectional views illustrating a manufacturing method of a package structure according to an embodiment of the invention.
  • FIG. 1A to FIG. 1G are schematic cross-sectional views illustrating a manufacturing method of a package structure according to an embodiment of the invention.
  • a carrier 102 is provided.
  • the carrier 102 may be a glass substrate or a glass supporting board.
  • other suitable substrate material may be adapted as the carrier 102 as long as the material is able to withstand the subsequent processes while carrying the package structure formed thereon.
  • the sacrificial structures 104 B are disposed on the carrier 102 .
  • the sacrificial structures 104 B are, for example, a sacrificial layer to be removed in a subsequent process.
  • a material of the sacrificial layer is not particularly limited, as long as it can be removed through a thinning process described thereafter.
  • the sacrificial structures 104 B are disposed on the carrier 102 through an adhesive layer 103 located on the carrier 102 .
  • the adhesive layer 103 may be a die attach film or formed from adhesive materials including an epoxy resin.
  • the adhesive layer 103 may be formed by methods such as coating, inkjet printing, film attaching or other suitable methods for providing a structural support to eliminate the need for mechanical clamping between the sacrificial structures 104 B and the carrier 102 .
  • the semiconductor die 104 A is disposed on the carrier 102 , and located on the sacrificial structures 104 B.
  • the semiconductor die 104 A is, for example stacked dies that comprise at least a bottom semiconductor die and a top semiconductor die stacked on top of each other.
  • the semiconductor die 104 A includes a first semiconductor die 104 A- 1 , a second semiconductor die 104 A- 2 and a third semiconductor die 104 A- 3 stacked on top of each other.
  • the first semiconductor die 104 A- 1 serve as the bottom semiconductor die
  • the third semiconductor die 104 A- 3 serve as the top semiconductor die
  • the second semiconductor die 104 A- 2 is sandwiched therebetween.
  • the number of stacked dies in the semiconductor die 104 A is not particularly limited.
  • a die attach film (DAF; not illustrated) may be disposed between each of the stacked dies to enhance their adhesion.
  • the semiconductor die 104 A is, for example, an ASIC (Application-Specific Integrated Circuit).
  • ASIC Application-Specific Integrated Circuit
  • Other suitable active devices may also be utilized as the semiconductor die 104 A.
  • a width W 2 of the sacrificial structure 104 B is greater than a width W 1 of the semiconductor die 104 A.
  • the width W 2 of the sacrificial structure 104 B is greater than a width of each of the semiconductor dies ( 104 A- 1 , 104 A- 2 and 104 A- 3 ).
  • the semiconductor die 104 A or the stacked dies each have a first surface Y 1 facing the carrier 102 and a second surface Y 2 facing away from the carrier 102 .
  • bonding pads 105 are provided on the sacrificial structures 104 B, and provided on the second surfaces Y 2 of the semiconductor die 104 A (stacked dies).
  • the bonding pads 105 are, for example, aluminum pads or any other suitable material used for wire bonding. In some embodiments, the bonding pads 105 can be embedded within the sacrificial structures 104 B.
  • a plurality of conductive wires 106 is provided to electrically connect the bonding pads 105 of the semiconductor die 104 A to the bonding pads 105 of the sacrificial structures 104 B.
  • the conductive wires 106 are, for example, used for wire bonding, and have a curved three-dimensional structure.
  • the conductive wires 106 are formed after stacking several dies in a group. For example, for multi-die stacking, the conductive wires 106 are used to provide electrical connection after two to four dies are stacked. For instance, in the embodiment shown in FIG.
  • the conductive wires 106 are used to electrically connect the bonding pads 105 on the stacked semiconductor dies ( 104 A- 1 and 104 A- 2 ) to the bonding pads 105 on the sacrificial structure 104 B. The process is repeated until all dies are stacked and the electrical connection is established. In some alternative embodiments, the conductive wires 106 are formed after all dies ( 104 A- 1 , 104 A- 2 and 104 A- 3 ) are stacked.
  • an encapsulant 108 is formed on the carrier 102 to encapsulate the semiconductor die 104 A, the sacrificial structure 104 B and the conductive wires 106 .
  • the semiconductor die 104 A, the sacrificial structures 104 B and the conductive wires 106 are completely encapsulated by the encapsulant 108 .
  • the encapsulant 108 may be a molding compound formed by molding processes.
  • the encapsulant 108 may be formed by an insulating material such as epoxy or other suitable resins. In general, when an area ratio of a die to an encapsulant is low, a problem of wafer or panel warpage may occur.
  • an area ratio of the dies (sacrificial structure as dummy die plus the semiconductor die) to the encapsulant 108 is increased. As such, an issue of wafer or panel warpage may be resolved.
  • the carrier 102 is debonded. That is, the carrier 102 is separated from the encapsulant 108 , the semiconductor die 104 A, and sacrificial structures 104 B.
  • a de-bonding layer (not illustrated) may be disposed on the carrier 102 before disposing the dies ( 104 A/ 104 B) on the carrier 102 .
  • the de-bonding layer is, for example, a light to heat conversion (LTHC) release layer or other suitable release layers.
  • connection terminals CT of the conductive wires 106 are exposed.
  • connection terminals CT may refer to end portions of the conductive wires 106 that are available for further connection.
  • the connection terminals CT can be the bonding pads 105 or studs of the conductive wires 106 that are used for further connection. That is, the connection terminals CT are generally treated as “connection points” that connect the conductive wires 106 to a redistribution layer 110 formed thereafter.
  • the bonding pads 105 or studs of the conductive wires 106 may have a surface area greater than an area of the cross section of the conductive wires 106 .
  • the thinning process may be performed through mechanical grinding, chemical mechanical polishing (CMP), or other suitable processes.
  • CMP chemical mechanical polishing
  • the connection terminals CT of the revealed conductive wires 106 are coplanar with a first surface S 1 of the semiconductor die 104 A.
  • the thinning process may remove portions of the semiconductor die 104 A to form a thinned semiconductor die 104 A.
  • a portion of the first semiconductor die 104 A- 1 (or bottom semiconductor die) is partially removed by the thinning process, so that the connection terminals CT (of the conductive wires 106 ) are coplanar with the first surface S of the first semiconductor die 104 A- 1 (bottom semiconductor die).
  • a thickness of the first semiconductor die 104 A- 1 is reduced.
  • the first semiconductor die 104 A- 1 have a thickness of T 1 before the thinning process
  • a thickness of the first semiconductor die 104 A- 1 reduces to T 2 after the thinning process.
  • the thickness of the semiconductor die 104 may be reduced during the thinning process.
  • the thickness of the semiconductor die 104 A does not change after the thinning process.
  • the thickness of the semiconductor die 104 A may be adjusted based on requirement during the thinning process.
  • the bonding pads 105 on the sacrificial structures 104 B are removed by the thinning process to reveal the conductive wires 106 underneath. That is, the end portions of the conductive wires 106 are treated as the connection terminals CT.
  • the bonding pads 105 on the sacrificial structures 104 B remain after the thinning process.
  • the thinning process is performed to reveal the bonding pads 105 on the sacrificial structures 104 B, and the revealed portions of the bonding pads 105 serve as the connection terminals CT.
  • the sacrificial structures 104 B may be completely removed by the thinning process or residual amounts of the sacrificial structures 104 B may remain after the thinning process.
  • a redistribution layer 110 is formed on the semiconductor die 104 A and the encapsulant 108 .
  • the redistribution layer 110 may include a plurality of conductive elements 110 A and a plurality of dielectric layers 110 B alternately formed and stacked on top of each other. As illustrated in FIG. 1E , the redistribution layer 110 includes four dielectric layers 110 B. However, the number of the dielectric layer 110 B is not limited and may be adjusted based on circuit design.
  • the conductive elements 110 A may include a plurality of trace layers and a plurality of interconnect structures connecting the trace layers.
  • the redistribution layer 110 is formed on the first surface S 1 of the semiconductor die 104 A (stacked die).
  • the redistribution layer 110 is electrically connected to the semiconductor die 104 A through the conductive wires 106 at the connection terminals CT.
  • the conductive wires 106 are electrically connected to the conductive elements 110 A of the redistribution layer 110 through the connection terminals CT.
  • Conductive terminals 118 are then formed on the redistribution layer 110 , and being electrically connected to the conductive elements 110 A.
  • the conductive terminals 118 may be a plurality of under-ball metallurgy (UBM) patterns for ball mount or connection pads for mounting of passive components.
  • UBM under-ball metallurgy
  • a plurality of conductive balls 120 are placed onto the conductive terminals 118 , and one or more passive components 115 may be mounted on the conductive terminals 118 .
  • the conductive terminals 118 and the conductive balls 120 may, for example, be formed by a ball placement process and a reflow process.
  • the passive components 115 may be mounted on the conductive terminals 118 through a soldering process. Examples of the passive components 115 include capacitors, resistors, inductors, fuses, or antennas. However, they construe no limitation in the invention.
  • a dicing or singulation process is performed on the package structure illustrated in FIG. 1F to render a plurality of individual packages 100 as shown in FIG. 1G .
  • the dicing process is, for example, performed at the dicing line DL for singulation of the individual packages 100 .
  • FIG. 2A to FIG. 2G are schematic cross-sectional views illustrating a manufacturing method of a package structure according to an embodiment of the invention.
  • the embodiments shown in FIG. 2A to FIG. 2G are similar to the embodiments shown in FIG. 1A to FIG. 1G , therefore, the same reference numerals are used to refer to the same or like parts, and their detailed descriptions are omitted herein.
  • the difference between the embodiments shown in FIG. 2A to FIG. 2G and the embodiments shown in FIG. 1A to FIG. 1G is in the position/design of the sacrificial structures 104 B.
  • the semiconductor die 104 A and at least one sacrificial structure 104 B are disposed on the carrier 102 .
  • a plurality of the sacrificial structures 104 B are disposed on the carrier 102 to surround the semiconductor die 104 A.
  • the semiconductor die 104 A and the sacrificial structures 104 B are disposed on a same plane and on a same surface 102 A of the carrier 102 .
  • a width (W 2 /W 3 ) of the sacrificial structures 102 B is smaller than a width W 1 of the semiconductor die 104 A.
  • the plurality of sacrificial structures 102 B may have different widths W 2 and W 3 .
  • both of the widths W 2 and W 3 are smaller than the width W 1 of the semiconductor die 104 A.
  • a thickness K 2 of the sacrificial structures 104 B is smaller than a thickness K 1 of the semiconductor dies 104 A.
  • the thickness K 1 of the semiconductor dies 104 A refers to the thickness of the first semiconductor die 104 A- 1 (bottom semiconductor die) of the stacked dies.
  • the sacrificial structures 104 B is also a sacrificial layer that is removed thereafter.
  • a thickness difference X 1 between the semiconductor die 104 A and the sacrificial structures 104 B (K 1 -K 2 ) will determine a thickness of a thinned semiconductor die 104 A formed thereafter.
  • bonding pads 105 may be formed on the semiconductor dies 104 A and the sacrificial structures 104 B to allow for wire bonding.
  • the wire bonding process is, for example, performed after the stacking of several dies in a group, or performed after stacking of all of the dies.
  • passive components 115 may be disposed on the sacrificial structures 104 B.
  • the passive components 115 may be adjacent to the bonding pads 105 and may be disposed on the same surface of the sacrificial structures 104 B.
  • a plurality of conductive wires 106 is provided to electrically connect the bonding pads 105 of the semiconductor die 104 A to the bonding pads 105 of the sacrificial structures 104 B.
  • an encapsulant 108 is formed on the carrier 102 to encapsulate the semiconductor die 104 A, the sacrificial structure 104 B and the conductive wires 106 .
  • the encapsulant 108 further encapsulates the passive components 115 .
  • the semiconductor die 104 A, the sacrificial structures 104 B, the conductive wires 106 and the passive components 115 are completely encapsulated by the encapsulant 108 . As shown in FIG.
  • the carrier 102 are debonded. That is, the carrier 102 is separated from the encapsulant 108 , the semiconductor die 104 A, and sacrificial structures 104 B.
  • a de-bonding layer (not illustrated) may be disposed on the carrier 102 before disposing the dies ( 104 A/ 104 B) on the carrier 102 .
  • the de-bonding layer is, for example, a light to heat conversion (LTHC) release layer or other suitable release layers.
  • connection terminals CT can be the end portions (or studs) of the conductive wires 106 . That is, the thinning process is performed to reveal/expose the end portions of the conductive wires 106 .
  • connection terminals CT are generally treated as “connection points” that connect the conductive wires 106 to a redistribution layer 110 formed thereafter. Therefore, the connection terminals CT will apply to all embodiments, and its position may be altered depending on which portion is revealed (wires/pads) for connection.
  • connection terminals CT of the bonding pads 105 are coplanar with a first surface S 1 of the semiconductor die 104 A.
  • a portion of the first semiconductor die 104 A- 1 (or bottom semiconductor die) is removed by the thinning process, so that the connection terminals CT are coplanar with the first surface S 1 of the first semiconductor die 104 A- 1 (bottom semiconductor die).
  • a thickness 104 T of the thinned semiconductor die (first semiconductor die 104 A- 1 ) will correspond to a thickness difference X 1 (see FIG. 2A ) between the semiconductor die 104 A (first semiconductor die 104 A- 1 ) and the sacrificial structure 104 B before the thinning process.
  • a redistribution layer 110 is formed on the semiconductor die 104 A and the encapsulant 108 .
  • the redistribution layer 110 of FIG. 2E is similar to the redistribution layer 110 of FIG. 1E , hence its detailed description is omitted herein.
  • the redistribution layer 110 is electrically connected to the semiconductor die 104 A through the conductive wires 106 at the connection terminals CT.
  • the conductive wires 106 are electrically connected to the conductive elements 110 A of the redistribution layer 110 through the connection terminals CT (of bonding pads 105 ).
  • Conductive terminals 118 are then formed on the redistribution layer 110 , and being electrically connected to the conductive elements 110 A.
  • a plurality of conductive balls 120 are placed onto the conductive terminals 118 .
  • the conductive terminals 118 and the conductive balls 120 may, for example, be formed by a ball placement process and a reflow process.
  • a dicing or singulation process is performed on the package structure illustrated in FIG. 2F to render a plurality of individual packages 100 ′ as shown in FIG. 2G .
  • the dicing process is, for example, performed at the dicing line DL for singulation of the individual packages 100 ′.
  • the individual packages 100 ′ includes an encapsulant 108 , a stacked die 104 A, a plurality of bonding pads 105 , a plurality of conductive wires 106 , a redistribution layer 110 and a plurality of conductive balls 120 .
  • the encapsulant 108 has a top surface 108 A and a bottom surface 108 B opposite to the top surface 108 A.
  • the stack die 104 A is embedded in the encapsulant 108 .
  • the bonding pads 105 are embedded in the encapsulant 108 , wherein connection terminals CT of the bonding pads 105 are exposed on a top surface 108 A of the encapsulant 108 .
  • the conductive wires 106 are embedded in the encapsulant 108 , wherein the stacked die 104 A is electrically connected to the bonding pads 105 through the conductive wires.
  • the redistribution layer 110 is disposed on the stacked die 104 A and on the top surface 108 A of the encapsulant 108 , wherein the redistribution layer 110 is electrically connected to the stacked die 104 A through the bonding pads 105 and the conductive wires 106 .
  • the stacked die (semiconductor die 104 A) has a first surface S 1 exposed through the encapsulant 108 .
  • the connection terminals CT of the bonding pads 105 are coplanar with the first surface S 1 of the stacked die 104 A and the top surface 108 A of the encapsulant 108 .
  • the stacked die 104 A may include a first die (first semiconductor die) 104 A- 1 , a second die (second semiconductor die) 104 A- 2 and a third die (third semiconductor die) 104 A- 3 .
  • the first die 104 A- 1 has the first surface S 1 exposed through the encapsulant 108 .
  • the second die 104 A- 2 is stacked on the first die 104 A- 1 opposite to a side of the first surface S 1 .
  • the second die 104 A- 2 cover portions of the first die 104 A- 1 , and other portions of the first die 104 A- 1 not covered by the second die 104 A- 2 contain die pads DP (bonding pads 105 ).
  • the die pads DP of the first die 104 A- 1 are electrically connected to the bonding pads 105 through the conductive wires 106 .
  • the third die 104 A- 3 is stacked on the second die 104 A- 2 , the third die 104 A- 3 cover portions of the second die 104 A- 2 , and other portions of the second die 104 A- 2 not covered by the third die 104 A- 3 contain die pads DP, the die pads DP of the second die 104 A- 2 are electrically connected to the bonding pads 105 through the conductive wires 106 .
  • the individual packages 100 ′ further includes at least one passive component 115 embedded in the encapsulant 108 .
  • the passive components 115 may be disposed on the redistribution layer 110 .
  • the encapsulant 108 has a first thickness 108 T
  • the redistribution layer 110 has a second thickness 110 T smaller than the first thickness 108 T. That is, the encapsulant 108 provides a first rigidity, and the redistribution layer 110 provides a second rigidity, wherein the first rigidity is greater than the second rigidity.
  • the bonding pads 105 are arranged with a first pitch P and the conductive balls 120 are arranged with a second pitch P 2 , the second pitch P 2 is greater than the first pitch P 1 . That is, the individual packages 100 ′ are directed to fan-out packages.
  • the first pitch P and the second pitch P 2 is calculated based on a center position of the bonding pads 105 and the conductive balls 120 .
  • the sacrificial structures are used to fix the position of the conductive wires.
  • the precise location of the wire or weld may be provided for further connection.
  • a thickness of the semiconductor die may be effectively controlled during the thinning process, thus an overall size of the package structure may be reduced.
  • an area ratio between the dies and the encapsulant is decreased.
  • the issue of wafer or panel warpage may be resolved. Accordingly, the simplicity of the manufacturing process of the package structure may be realized, thereby reducing the overall manufacturing cost.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US15/644,831 2017-07-10 2017-07-10 Package structure and manufacturing method thereof Abandoned US20190013214A1 (en)

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CN201710845069.8A CN109243981B (zh) 2017-07-10 2017-09-19 封装结构及其制造方法
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TW201909293A (zh) 2019-03-01
US10796931B2 (en) 2020-10-06

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