[go: up one dir, main page]

US20180075885A1 - Semiconductor device and system performing calibration operation - Google Patents

Semiconductor device and system performing calibration operation Download PDF

Info

Publication number
US20180075885A1
US20180075885A1 US15/417,518 US201715417518A US2018075885A1 US 20180075885 A1 US20180075885 A1 US 20180075885A1 US 201715417518 A US201715417518 A US 201715417518A US 2018075885 A1 US2018075885 A1 US 2018075885A1
Authority
US
United States
Prior art keywords
pull
calibration
output circuit
coupled
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/417,518
Other languages
English (en)
Inventor
Hae Kang Jung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JUNG, HAE KANG
Publication of US20180075885A1 publication Critical patent/US20180075885A1/en
Priority to US16/201,430 priority Critical patent/US10522203B2/en
Priority to US16/201,639 priority patent/US10354703B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Definitions

  • Various embodiments generally relate to a semiconductor technology, and, more particularly, to a semiconductor device and system performing a calibration operation.
  • An electronic apparatus may include a large number of electronic components.
  • a computer system may include many semiconductor devices, which are semiconductor based electronic components. These semiconductor devices may transmit data in synchronization with a clock, and may perform serial communication. As semiconductor devices operate with low signal voltages and high operating frequencies, electronic signals are subject to the influence of noise, and impedance mismatching between semiconductor devices communicating with each other may lead to signal distortion.
  • a semiconductor device may include an on-die termination circuit performing impedance matching for signal integrity purposes. Moreover, the semiconductor device may perform an impedance calibration with respect to termination resistance according to PVT variations for the purpose of precise impedance matching.
  • a memory device may be coupled to an external reference resistor, and calibrates the impedance value of a termination resistor by performing a calibration operation by using the external reference resistor. This is generally referred to as a ZQ calibration operation.
  • a semiconductor device may include a calibration circuit and an output circuit.
  • the calibration circuit may perform a calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in a controller.
  • the output circuit may be coupled to the signal transmission line.
  • a resistance value of the output circuit may be set based on a result of the calibration operation.
  • a semiconductor system may include a first semiconductor device and a second semiconductor device.
  • the first semiconductor device may include an output circuit coupled to a signal transmission line.
  • the second semiconductor device may include an output circuit coupled to the signal transmission line and a calibration circuit configured to perform a calibration operation by being coupled, through the signal transmission line, to a reference resistor provided in the first semiconductor device.
  • a resistance value of the output circuit of the second semiconductor device may be set based on a result of the calibration operation.
  • a semiconductor system may include a first semiconductor device and a second semiconductor device.
  • the first semiconductor device may be coupled to a signal transmission line, and may include an output circuit including a plurality of pull-up resistor legs and a plurality of pull-down resistor legs.
  • the second semiconductor device may include an output circuit and a calibration circuit.
  • the output circuit may be coupled to the signal transmission line, and may include a plurality of pull-up resistor legs and a plurality of pull-down resistor legs.
  • the calibration circuit may be coupled to the signal transmission line, and may perform a calibration operation to set resistance values of the plurality of pull-up resistor legs and the plurality of pull-down resistor legs of the output circuit of the second semiconductor device.
  • a method of operating a semiconductor system including a controller and a memory device coupled to each other through a signal transmission line may include performing a calibration operation of the controller by being coupled with an external reference resistor, and setting a resistance value of a controller output circuit which is coupled to the signal transmission line, based on a result of the calibration operation of the controller.
  • the method may include performing a calibration operation of the memory device by being coupled to the controller output circuit through the signal transmission line and by being coupled to a reference resistor provided from the controller output circuit, and setting a resistance value of a memory output circuit coupled to the signal transmission line, based on a result of the calibration operation of the memory device.
  • a semiconductor system may include a controller, a first memory device, and a second memory device.
  • the controller may be coupled to first and second signal transmission lines.
  • the first memory device may be coupled to the first and second signal transmission lines, and may include a first memory calibration circuit.
  • the second memory device may be coupled to the first and second signal transmission lines, and may include a second memory calibration circuit.
  • the first memory calibration circuit may perform a calibration operation by being coupled to the first signal transmission line based on a first chip calibration select signal
  • the second memory calibration circuit may perform a calibration operation by being coupled to the second signal transmission line based on a second chip calibration select signal.
  • a semiconductor system may include a controller and a memory device.
  • the controller may include a controller calibration circuit performing a calibration operation by being coupled to an external reference resistor.
  • the memory device may include a memory calibration circuit performing a calibration operation by being coupled to the external reference resistor.
  • FIG. 1 is a diagram schematically illustrating an example configuration of a semiconductor system in accordance with an embodiment.
  • FIG. 2 is a diagram illustrating an example configuration of a semiconductor system in accordance with an embodiment.
  • FIG. 3 is an example of a flow chart showing operations of the semiconductor system in accordance with an embodiment.
  • FIGS. 4 a and 4 b are diagrams showing operations of the semiconductor system in accordance with an embodiment.
  • FIG. 5 is a diagram illustrating an example configuration of a semiconductor system in accordance with an embodiment.
  • FIGS. 6 a and 6 b are diagrams showing operations of the semiconductor system in accordance with an embodiment.
  • FIG. 7 is a diagram illustrating an example configuration of a semiconductor system in accordance with an embodiment.
  • FIG. 8 is a diagram illustrating an example configuration of a semiconductor system in accordance with an embodiment.
  • FIG. 1 is a diagram illustrating an example configuration of a semiconductor system 1 in accordance with an embodiment.
  • the semiconductor system 1 in accordance with an embodiment may include a first semiconductor device 110 and a second semiconductor device 120 .
  • the first semiconductor device 110 and the second semiconductor device 120 may be electronic components that communicate with each other.
  • the first semiconductor device 110 may be a master device
  • the second semiconductor device 120 may be a slave device that is controlled by the first semiconductor device 110 .
  • the first semiconductor device 110 may be a host device such as a processor or a controller, and may include one or more of a central processing unit (CPU), a graphic processing unit (GPU), a multimedia processor (MMP), a digital signal processor (DSP), and a memory controller.
  • CPU central processing unit
  • GPU graphic processing unit
  • MMP multimedia processor
  • DSP digital signal processor
  • the first semiconductor device 110 may be realized in the form of a system-on-chip by integrating various electronic components including processor chips having various functions, such as application processors (AP), into a single chip. Also, the first semiconductor device 110 may be an interface chip for communicating with the second semiconductor device 120 .
  • the second semiconductor device 120 may be a memory device that includes one or more of a volatile memory and a nonvolatile memory.
  • Examples of the volatile memory may include a static RAM (SRAM), a dynamic RAM (DRAM), and a synchronous DRAM (SDRAM), and examples of the nonvolatile memory may include a read only memory (ROM), a programmable ROM (PROM), an electrically erasable and programmable ROM (EEPROM), an electrically programmable ROM (EPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM).
  • the second semiconductor device 120 may be an interface chip for communicating with the first semiconductor device 110 .
  • the first and second semiconductor devices 110 and 120 may be coupled to each other through a signal transmission line 130 .
  • the first semiconductor device 110 may include a pad 111 , and the pad 111 may be coupled to the signal transmission line 130 .
  • the second semiconductor device 120 may include a pad 121 , and the pad 121 may be coupled to the signal transmission line 130 .
  • the signal transmission line 130 may be channels, links, or buses.
  • the signal transmission line 130 may transmit any signal that may be used in a general semiconductor system, such as data, a clock, an address, or a command.
  • the first semiconductor device 110 may include an output circuit (TX) 112 and a reception circuit (RX) 113 .
  • the output circuit 112 may generate an output signal according to an internal signal of the first semiconductor device 110 , and may transmit the output signal to the second semiconductor device 120 through the signal transmission line 130 .
  • the reception circuit 113 may receive a signal transmitted from the second semiconductor device 120 through the signal transmission line 130 , and may generate an internal signal.
  • the second semiconductor device 120 may include an output circuit (TX) 122 and a reception circuit (RX) 123 .
  • the output circuit 122 may generate an output signal according to an internal signal of the second semiconductor device 120 , and may transmit the output signal to the first semiconductor device 110 through the signal transmission line 130 .
  • the reception circuit 123 may receive a signal transmitted from the first semiconductor device 110 through the signal transmission line 130 , and may generate an internal signal.
  • the output circuits 112 and 122 of the first and second semiconductor devices 110 and 120 may set their resistance values through impedance calibration operations (e.g., ZQ calibration). Each of the first and second semiconductor devices 110 and 120 may further include calibration circuits (not illustrated), which performs impedance calibration operations to set the resistance values of the output circuits 112 and 122 .
  • the calibration circuit of the first semiconductor device 110 may perform the calibration operation by being coupled to an external reference resistor.
  • the calibration circuit of the second semiconductor device 120 may perform the calibration operation without being coupled to an external reference resistor. Instead, the calibration circuit of the second semiconductor device 120 may perform the calibration operation by being coupled to the first semiconductor device 110 through the signal transmission line 130 .
  • the output circuit 112 of the first semiconductor device 110 may provide a reference resistance through the signal transmission line 130 .
  • the calibration circuit of the second semiconductor device 120 may use a resistance element of the output circuit 112 of the first semiconductor device 110 , which is coupled to the second semiconductor device 120 through the signal transmission line 130 , as a reference resistance element.
  • FIG. 2 is a diagram illustrating an example configuration of a semiconductor system 2 in accordance with an embodiment.
  • the semiconductor system 2 may include a first semiconductor device and a second semiconductor device.
  • the semiconductor system 2 may include a controller 210 and a memory device 220 .
  • the controller 210 may be an example of the first semiconductor device
  • the memory device 220 may be an example of the second semiconductor device.
  • the controller 210 and the memory device 220 may communicate with each other through a signal transmission line.
  • the signal transmission line may be, for example, a data transmission line 230 .
  • the controller 210 and the memory device 220 may perform data communication through the data transmission line 230 .
  • the controller 210 controls the memory device 220 such that the memory device 220 may perform various operations.
  • the controller 210 may include a pad, and the pad may be a data pad 211 .
  • the controller 210 may be coupled to the data transmission line 230 through the data pad 211 .
  • the controller 210 may include a controller calibration circuit 212 and a controller output circuit, and the controller output circuit may be, for example, a controller data output circuit 213 .
  • the controller calibration circuit 212 may be coupled to an external reference resistor ZQ through a resistor pad 214 .
  • One end of the external reference resistor ZQ may be coupled to the controller calibration circuit 212 through the resistor pad 214 , and the other end of the external reference resistor ZQ may be coupled to a high voltage such as a power supply voltage or a low voltage such as a ground voltage.
  • the controller calibration circuit 212 may perform a calibration operation (e.g., impedance calibration operation) by using the external reference resistor ZQ.
  • the controller calibration circuit 212 may set the resistance value of the controller data output circuit 213 based on the result of the calibration operation.
  • the controller calibration circuit 212 may generate a first pull-up code PC 1 and a first pull-down code NC 1 by performing the calibration operation.
  • the controller data output circuit 213 may generate output data to be transmitted through the data transmission line 230 , from the internal data of the controller 210 .
  • the resistance value of the controller data output circuit 213 may be set based on the result of the calibration operation of the controller calibration circuit 212 .
  • the controller data output circuit 213 may include a plurality of pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 and a plurality of pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 .
  • Each of the plurality of pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 may be coupled to the power supply voltage at one end thereof, and, at the other end thereof, may be coupled to the data transmission line 230 through the data pad 211 .
  • Each of the plurality of pull-down resistor legs PDL 11 , PDL 12 and PDL 13 may be coupled to the ground voltage at one end thereof, and, at the other end thereof, may be coupled to the data transmission line 230 through the data pad 211 .
  • Each of the plurality of pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 and the plurality of pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 may function as a termination resistor of the controller data output circuit 213 .
  • the resistance values of the plurality of pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 and the plurality of pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 may be set, respectively, based on the calibration operation of the controller calibration circuit 212 .
  • the controller data output circuit 213 may receive the first pull-up code PC 1 and the first pull-down code NC 1 .
  • the resistance values of the plurality of pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 may be set based on the first pull-up code PC 1
  • the resistance values of the plurality of pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 may be set based on the first pull-down code NC 1 .
  • each of the pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 and the pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 may be set to the resistance value of 60 ohms, 120 ohms or 240 ohms.
  • the controller 210 may provide a reference resistance for the calibration operation of the memory device 220 , through the data transmission line 230 .
  • the controller data output circuit 213 may provide a reference resistance to the memory device 220 through the data transmission line 230 .
  • the memory device 220 may use a resistance element of the controller data output circuit 213 , which is coupled to the memory device 220 through the data transmission line 230 , as a reference resistance element.
  • the controller 210 may couple at least one of the plurality of pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 and the plurality of pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 to the data transmission line 230 , based on a calibration select signal CALSEL.
  • the calibration select signal CALSEL may be generated based on a calibration signal, which may be transmitted from the controller 210 to the memory device 220 for the calibration operation of the memory device 220 .
  • At least one of the plurality of pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 and the plurality of pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 may be turned on based on the calibration select signal CALSEL, and the turned-on resistor leg may be coupled to the data transmission line 230 .
  • the turned-on resistor leg may be provided as a reference resistor for the calibration operation of the memory device 220 .
  • the memory device 220 may include a pad, and the pad may be a data pad 221 .
  • the memory device 220 may be coupled to the data transmission line 230 through the data pad 221 .
  • the memory device 220 may include a memory calibration circuit 222 and a memory output circuit.
  • the memory output circuit may be, for example, a memory data output circuit 223 .
  • the memory calibration circuit 222 may perform the calibration operation based on the reference resistance provided from the controller 210 through the data transmission line 230 . Instead of having a resistor pad such as the resistor pad 214 , the memory device 220 may use the reference resistance of the controller 210 .
  • the memory calibration circuit 222 may perform the calibration operation by using the reference resistance provided from the controller 210 through the data transmission line 230 , instead of being coupled to an external reference resistor through a resistor pad.
  • the memory calibration circuit 222 may set the resistance value of the memory data output circuit 223 based on the result of the calibration operation.
  • the memory calibration circuit 222 may generate a second pull-up code PC 2 and a second pull-down code NC 2 by performing the calibration operation.
  • the memory data output circuit 223 may generate output data to be transmitted to the controller 210 through the data transmission line 230 , from the internal data of the memory device 220 .
  • the resistance value of the memory data output circuit 223 may be set based on the result of the calibration operation of the memory calibration circuit 222 .
  • the memory data output circuit 223 may include a plurality of pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 and a plurality of pull-down resistor legs PDL 21 , PDL 22 , and PDL 23 .
  • Each of the plurality of pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 may be coupled to a terminal of the power supply voltage at one end thereof, and, at the other end thereof, may be coupled to the data transmission line 230 through the data pad 221 .
  • Each of the plurality of pull-down resistor legs PDL 21 , PDL 22 and PDL 23 may be coupled to a terminal of the ground voltage, and, at the other end thereof, may be coupled to the data transmission line 230 through the data pad 221 .
  • Each of the plurality of pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 and the plurality of pull-down resistor legs PDL 21 , PDL 22 , and PDL 23 may function as the termination resistor of the memory data output circuit 223 .
  • the resistance values of the plurality of pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 and the plurality of pull-down resistor legs PDL 21 , PDL 22 , and PDL 23 may be set, respectively, based on the result of the calibration operation.
  • the memory data output circuit 223 may receive the second pull-up code PC 2 and the second pull-down code NC 2 .
  • the resistance values of the plurality of pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 may be set based on the second pull-up code PC 2 .
  • the resistance values of the plurality of pull-down resistor legs PDL 21 , PDL 22 , and PDL 23 may be set based on the second pull-down code NC 2 .
  • each of the plurality of pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 and the plurality of pull-down resistor legs PDL 21 , PDL 22 , and PDL 23 may be set to the resistance value of 60 ohms, 120 ohms or 240 ohms.
  • the memory device 220 may perform the calibration operation by using the reference resistance provided from the controller 210 through the data transmission line 230 , instead of using an external reference resistor. Since the memory device 220 does not need to include a resistor pad, therefore, the manufacturing cost may be reduced. Moreover, by using a resistor pad as a power pad, operation performance may be improved.
  • FIG. 3 is an example of a flow chart showing operations of the semiconductor system 2 in accordance with an embodiment
  • FIGS. 4 a and 4 b are diagrams showing operation methods of the semiconductor system 2 in accordance with an embodiment. The operation method of the semiconductor system 2 in accordance with an embodiment will be described below with reference to FIGS. 2 to 4 b .
  • the controller 210 may perform a calibration operation (S 301 ).
  • the controller calibration circuit 212 may generate the first pull-up code PC 1 and the first pull-down code NC 1 by using a resistance value of the external reference resistor ZQ (S 302 ).
  • the pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 of the controller data output circuit 213 may be set to predetermined resistance values based on the first pull-up code PC 1
  • the pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 of the controller data output circuit 213 may be set to predetermined resistance values based on the first pull-down code NC 1 (S 303 ).
  • the controller 210 may prepare the calibration operation of the memory device 220 (S 304 ). Thereafter, the controller 210 may generate a calibration signal, and the memory device 220 may perform the calibration operation based on the calibration signal. Also, the calibration select signal CALSEL may be generated based on the calibration signal (S 305 ).
  • the controller 210 may turn on one of the pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 of the controller data output circuit 213 , based on the calibration select signal CALSEL. For example, the controller 210 may turn on the first pull-down resistor leg PDL 11 , and then the first pull-down resistor leg PDL 11 may be coupled to the data transmission line 230 (S 306 ).
  • the memory device 220 may perform the calibration operation based on the calibration signal (S 307 ).
  • the memory calibration circuit 222 may use, as a reference resistor, the pull-down resistor leg PDL 11 coupled through the data transmission line 230 .
  • the memory calibration circuit 222 may include a reference resistor leg RL, a replica pull-up resistor leg RPUL, a replica pull-down resistor leg RPDL, a first comparator 411 , and a second comparator 412 .
  • the reference resistor leg RL may be, for example, a pull-up resistor leg.
  • the reference resistor leg RL may be coupled to the pull-down resistor leg PDL 11 through the data transmission line 230 .
  • the first comparator 411 may generate the second pull-down code NC 2 by comparing the voltage level of the data transmission line 230 , which is determined based on the resistance ratio of the pull-down resistor leg PDL 11 and the reference resistor leg RL, with the level of a calibration reference voltage VCAL.
  • the calibration reference voltage VCAL may be a voltage that has a predetermined level for the calibration operation.
  • the second comparator 412 may generate the second pull-up code PC 2 by comparing the level of the calibration reference voltage VCAL with a voltage level determined based on the resistance ratio of the replica pull-up resistor leg RPUL and the replica pull-down resistor leg RPDL.
  • the memory calibration circuit 222 may set first the second pull-up code PC 2 , and may then set the second pull-down code NC 2 based on the set second pull-up code PC 2 (S 308 ). If the second pull-up code PC 2 and the second pull-down code NC 2 are generated, the pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 of the memory data output circuit 223 may set their resistance values based on the second pull-up code PC 2 , and the pull-down resistor legs PDL 21 , PDL 22 and PDL 23 of the memory data output circuit 223 may set their resistance values based on the second pull-down code NC 2 (S 309 ).
  • the controller 210 may turn on one of the pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 of the controller data output circuit 213 , based on the calibration select signal CALSEL. For example, the controller 210 may turn on the first pull-up resistor leg PUL 11 , and then the first pull-up resistor leg PUL 11 may be coupled to the data transmission line 230 .
  • the memory calibration circuit 222 may use, as a reference resistor, the pull-up resistor leg PUL 11 coupled through the data transmission line 230 . In FIG.
  • the memory calibration circuit 222 may include a reference resistor leg RL, a replica pull-up resistor leg RPUL, a replica pull-down resistor leg RPDL, a first comparator 421 , and a second comparator 422 .
  • the reference resistor leg RL may be coupled to the pull-up resistor leg PUL 11 through the data transmission line 230 .
  • the reference resistor leg RL may be a pull-down resistor leg.
  • the first comparator 421 may generate the second pull-down code NC 2 by comparing the voltage level of the data transmission line 230 , which is determined based on the resistance ratio of the pull-up resistor leg PUL 11 and the reference resistor leg RL, with the level of a calibration reference voltage VCAL.
  • the resistance value of the replica pull-down resistor leg RPDL may be set.
  • the second comparator 422 may generate the second pull-up code PC 2 by comparing the level of the calibration reference voltage VCAL with a voltage level determined based on the resistance ratio of the replica pull-up resistor leg RPUL and the replica pull-down resistor leg RPDL.
  • the memory calibration circuit 222 may set first the second pull-down code NC 2 , and may then set the second pull-up code PC 2 based on the set second pull-down code NC 2 (S 308 ).
  • the pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 of the memory data output circuit 223 may set their resistance values based on the second pull-up code PC 2
  • the pull-down resistor legs PDL 21 , PDL 22 , and PDL 23 of the memory data output circuit 223 may set their resistance values based on the second pull-down code NC 2 (S 309 ).
  • the resistor leg turned on based on the calibration select signal CALSEL may remain turned on until the calibration operation of the memory device 220 is completed (S 311 ). If the resistance value setting (e.g., calibration) of the memory data output circuit 223 is completed, the controller 210 turns off the turned-on resistor leg (S 312 ), and the calibration operation of the semiconductor system 2 may end.
  • FIG. 5 is a diagram illustrating an example configuration of a semiconductor system 5 in accordance with an embodiment.
  • the semiconductor system 5 may include a controller 510 and a memory device 520 .
  • the controller 510 may include a controller calibration circuit 512 and a controller data output circuit 513 .
  • the controller calibration circuit 512 may be coupled to an external reference resistor ZQ through a resistor pad 514 , and may perform a calibration operation by using the external reference resistor ZQ.
  • the controller calibration circuit 512 may generate a first pull-up code PC 1 and a first pull-down code NC 1 through the calibration operation.
  • the controller data output circuit 513 may be coupled to a data transmission line 530 through a data pad 511 .
  • the controller data output circuit 513 may include a plurality of pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 and a plurality of pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 .
  • the resistance values of the plurality of pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 may be set based on the first pull-up code PC 1
  • the resistance values of the plurality of pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 may be set based on the first pull-down code NC 1 .
  • the controller 510 may turn on at least one of the plurality of pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 and the plurality of pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 , based on a first calibration select signal CALSEL 1 .
  • the turned-on resistor leg may be coupled to the data transmission line 230 .
  • the turned-on resistor leg may be provided as a reference resistor for the calibration operation of the memory device 520 .
  • the memory device 520 may include a memory calibration circuit 522 and a memory data output circuit 523 .
  • the memory calibration circuit 522 may perform the calibration operation by using the reference resistance provided from the controller 510 through the data transmission line 530 .
  • the memory calibration circuit 522 may generate a second pull-up code PC 2 and a second pull-down code NC 2 through the calibration operation.
  • the memory data output circuit 523 may include a plurality of pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 and a plurality of pull-down resistor legs PDL 21 , PDL 22 , and PDL 23 .
  • the resistance values of the plurality of pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 may be set based on the second pull-up code PC 2 , and the resistance values of the plurality of pull-down resistor legs PDL 21 , PDL 22 , and PDL 23 may be set based on the second pull-down code NC 2 .
  • the memory device 520 may turn on at least one of the plurality of pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 and the plurality of pull-down resistor legs PDL 21 , PDL 22 , and PDL 23 , based on a second calibration select signal CALSEL 2 .
  • the turned-on resistor leg may be coupled to the data transmission line 230 .
  • the memory calibration circuit 522 may perform the calibration operation by using the turned-on resistor leg of the controller data output circuit 513 and the turned-on resistor leg of the memory data output circuit 523 , which are coupled through the data transmission line 530 .
  • the first and second calibration select signals CALSEL 1 and CALSEL 2 may be generated from a calibration signal generated in the controller 210 , for the calibration operation of the memory device 520 .
  • FIGS. 6 a and 6 b are diagrams showing the operation method of the semiconductor system 5 in accordance with an embodiment. The operation of the semiconductor system 5 in accordance with an embodiment will be described below with reference to FIGS. 5 to 6 b .
  • the controller 510 may perform a calibration operation.
  • the controller calibration circuit 512 may generate the first pull-up code PC 1 and the first pull-down code NC 1 by using a resistance value of the external reference resistor ZQ.
  • the pull-up resistor legs PUL 11 , PUL 12 , and PUL 13 of the controller data output circuit 513 may be set to predetermined resistance values based on the first pull-up code PC 1
  • the pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 of the controller data output circuit 513 may be set to predetermined resistance values based on the first pull-down code NC 1 .
  • the controller 510 may generate a calibration signal
  • the memory device 520 may perform the calibration operation based on the calibration signal.
  • the first and second calibration select signals CALSEL 1 and CALSEL 2 may be generated.
  • the controller 510 may turn on at least one of the pull-down resistor legs PDL 11 , PDL 12 , and PDL 13 of the controller data output circuit 513 , based on the first calibration select signal CALSEL 1 .
  • the memory device 520 may turn on at least one of the plurality of pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 of the memory data output circuit 523 , based on the second calibration select signal CALSEL 2 .
  • the first pull-down resistor leg PDL 11 of the controller data output circuit 513 may be turned on based on the first calibration select signal CALSEL 1
  • the first pull-up resistor leg PUL 21 of the memory data output circuit 523 may be turned on based on the second calibration select signal CALSEL 2
  • the memory calibration circuit 522 may include a replica pull-up resistor leg RPUL, a replica pull-down resistor leg RPDL, a first comparator 611 , and a second comparator 612 . Since the memory device 520 performs the calibration operation by using the resistor leg of the memory data output circuit 523 , the memory calibration circuit 522 does not need to include the reference resistor leg RL unlike the memory calibration circuit 222 illustrated in FIGS. 4 a and 4 b , and thus may help reducing the overall size of the memory device 520 .
  • the first comparator 611 may be coupled to the data transmission line 530 , and may generate the second pull-down code NC 2 by comparing the level of a calibration reference voltage VCAL with a voltage level determined based on the resistance ratio of the pull-down resistor leg PDL 11 and the pull-up resistor leg PUL 21 .
  • the second comparator 612 may generate the second pull-up code PC 2 by comparing the level of the calibration reference voltage VCAL with a voltage level determined based on the resistance ratio of the replica pull-up resistor leg RPUL and the replica pull-down resistor leg RPDL.
  • the memory calibration circuit 522 may set first the second pull-up code PC 2 and then set the second pull-down code NC 2 .
  • the pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 of the memory data output circuit 523 may be set to predetermined resistance values, based on the second pull-up code PC 2
  • the pull-down resistor legs PDL 21 , PDL 22 , and PDL 23 of the memory data output circuit 223 may be set to the predetermined resistance values, based on the second pull-down code NC 2 .
  • FIG. 6 b illustrates an example where the first pull-up resistor leg PUL 11 of the controller data output circuit 513 is turned on based on the first calibration select signal CALSEL 1 and the first pull-down resistor leg PDL 21 of the memory data output circuit 523 is turned on based on the second calibration select signal CALSEL 2 .
  • the memory calibration circuit 522 may include a replica pull-up resistor leg RPUL, a replica pull-down resistor leg RPDL, a first comparator 621 , and a second comparator 622 .
  • the first comparator 621 may be coupled to the data transmission line 530 , and may generate the second pull-down code NC 2 by comparing the level of a calibration reference voltage VCAL with a voltage level determined based on the resistance ratio of the pull-up resistor leg PUL 11 and the pull-down resistor leg PDL 21 .
  • the resistance value of the replica pull-down resistor leg RPDL may be set according to the second pull-down code NC 2 .
  • the second comparator 622 may generate the second pull-up code PC 2 by comparing the level of the calibration reference voltage VCAL with a voltage level determined based on the resistance ratio of the replica pull-up resistor leg RPUL and the replica pull-down resistor leg RPDL.
  • the pull-up resistor legs PUL 21 , PUL 22 , and PUL 23 of the memory data output circuit 523 may be set to predetermined resistance values, based on the second pull-up code PC 2
  • the pull-down resistor legs PDL 21 , PDL 22 , and PDL 23 of the memory data output circuit 223 may be set to the predetermined resistance values, based on the second pull-down code NC 2 .
  • FIG. 7 is a diagram illustrating an example configuration of a semiconductor system 7 in accordance with an embodiment.
  • the semiconductor system 7 may include a controller 710 , a first memory device 720 , and a second memory device 730 .
  • the first and second memory devices 720 and 730 may be integrated into a single memory device or one memory module.
  • the controller 710 may be coupled in common to the first and second memory devices 720 and 730 through data transmission lines 741 and 742 .
  • the controller 710 may be coupled to the first data transmission line 741 through a first data pad 714 , and may be coupled to the second data transmission line 742 through a second data pad 716 .
  • the first memory device 720 may be coupled to the first data transmission line 741 through a first data pad 724 , and may be coupled to the second data transmission line 742 through a second data pad 726 .
  • the second memory device 730 may be coupled to the first data transmission line 741 through a first data pad 734 , and may be coupled to the second data transmission line 742 through a second data pad 736 .
  • the controller 710 may include a controller calibration circuit 711 , a first controller data output circuit 713 , and a second controller data output circuit 715 .
  • the controller calibration circuit 711 may be coupled to an external reference resistor ZQ through a resistor pad 712 .
  • the controller calibration circuit 711 may perform a calibration operation by being coupled to the external reference resistor ZQ.
  • the controller calibration circuit 711 may generate a first pull-up code PC 1 and a first pull-down code NC 1 .
  • the first controller data output circuit 713 may be coupled to the first data transmission line 741 through the first data pad 714 .
  • the first controller data output circuit 713 may include a plurality of pull-up resistor legs and a plurality of pull-down resistor legs.
  • the resistance values of the plurality of pull-up resistor legs may be set based on the first pull-up code PC 1 , and the resistance values of the plurality of pull-down resistor legs may be set based on the first pull-down code NC 1 .
  • the second controller data output circuit 715 may be coupled to the second data transmission line 742 through the second data pad 716 .
  • the second controller data output circuit 715 may include a plurality of pull-up resistor legs and a plurality of pull-down resistor legs.
  • the resistance values of the plurality of pull-up resistor legs may be set based on the first pull-up code PC 1
  • the resistance values of the plurality of pull-down resistor legs may be set based on the first pull-down code NC 1 .
  • the controller 710 may turn on at least one of the plurality of pull-up resistor legs and the plurality of pull-down resistor legs of the first controller data output circuit 713 , based on a calibration select signal CALSEL.
  • the controller 710 may turn on at least one of the plurality of pull-up resistor legs and the plurality of pull-down resistor legs of the second controller data output circuit 715 , based on the calibration select signal CALSEL.
  • the turned-on resistor leg of the first controller data output circuit 713 may be coupled to the first data transmission line 741 , and may be provided as a reference resistor for the calibration operation of the first and second memory devices 720 and 730 .
  • the turned-on resistor leg of the second controller data output circuit 715 may be coupled to the second data transmission line 742 , and may be provided as a reference resistor for the calibration operation of the first and second memory devices 720 and 730 .
  • the first memory device 720 may include a first memory calibration circuit 721 , a first memory data output circuit 723 , and a second memory data output circuit 725 .
  • the first memory calibration circuit 721 may perform the calibration operation of the first memory device 720 .
  • the first memory calibration circuit 721 may generate a second pull-up code PC 2 and a second pull-down code NC 2 through the calibration operation.
  • the first memory data output circuit 723 may be coupled to the first data transmission line 741 through the first data pad 724 .
  • the first memory data output circuit 723 may include a plurality of pull-up resistor legs and a plurality of pull-down resistor legs.
  • the resistance values of the plurality of pull-up resistor legs may be set based on the second pull-up code PC 2 , and the resistance values of the plurality of pull-down resistor legs may be set based on the second pull-down code NC 2 .
  • the second memory data output circuit 725 may be coupled to the second data transmission line 742 through the second data pad 726 .
  • the second memory data output circuit 725 may include a plurality of pull-up resistor legs and a plurality of pull-down resistor legs.
  • the resistance values of the plurality of pull-up resistor legs may be set based on the second pull-up code PC 2
  • the resistance values of the plurality of pull-down resistor legs may be set based on the second pull-down code NC 2 .
  • the second memory device 730 may include a second memory calibration circuit 731 , a third memory data output circuit 733 , and a fourth memory data output circuit 735 .
  • the second memory calibration circuit 731 may perform the calibration operation of the second memory device 730 .
  • the second memory calibration circuit 731 may generate a third pull-up code PC 3 and a third pull-down code NC 3 through the calibration operation.
  • the third memory data output circuit 733 may be coupled to the first data transmission line 741 through the first data pad 734 .
  • the third memory data output circuit 733 may include a plurality of pull-up resistor legs and a plurality of pull-down resistor legs.
  • the resistance values of the plurality of pull-up resistor legs may be set based on the third pull-up code PC 3 , and the resistance values of the plurality of pull-down resistor legs may be set based on the third pull-down code NC 3 .
  • the fourth memory data output circuit 735 may be coupled to the second data transmission line 742 through the second data pad 736 .
  • the fourth memory data output circuit 735 may include a plurality of pull-up resistor legs and a plurality of pull-down resistor legs.
  • the resistance values of the plurality of pull-up resistor legs may be set based on the third pull-up code PC 3
  • the resistance values of the plurality of pull-down resistor legs may be set based on the third pull-down code NC 3 .
  • the first memory device 720 may turn on at least one of the pluralities of resistor legs of the first memory data output circuit 723 , based on a first chip calibration select signal CSCALSEL 1 .
  • the first memory device 720 may turn on at least one of the pluralities of resistor legs of the second memory data output circuit 725 , based on a second chip calibration select signal CSCALSEL 2 .
  • the first and second chip calibration select signals CSCALSEL 1 and CSCALSEL 2 may be generated based on a chip select signal, which is used to select the first and second memory devices 720 and 730 , and the calibration select signal CALSEL.
  • the first memory device 720 may turn on at least one resistor leg of the first memory data output circuit 723 , based on the first chip calibration select signal CSCALSEL 1 , and the turned-on resistor leg may be coupled to the first data transmission line 741 .
  • the second chip calibration select signal CSCALSEL 2 may be disabled, and all the resistor legs of the second memory data output circuit 725 may be turned off.
  • the second memory device 730 may turn on at least one of the pluralities of resistor legs of the third memory data output circuit 733 , based on the first chip calibration select signal CSCALSEL 1 .
  • the second memory device 730 may turn on at least one of the pluralities of resistor legs of the fourth memory data output circuit 735 , based on the second chip calibration select signal CSCALSEL 2 .
  • the first chip calibration select signal CSCALSEL 1 may be disabled, and all the resistor legs of the third memory data output circuit 733 may be turned off.
  • the second memory device 730 may turn on at least one of the pluralities of resistor legs of the fourth memory data output circuit 735 , based on the second chip calibration select signal CSCALSEL 2 .
  • the turned-on resistor leg may be coupled to the second data transmission line 742 .
  • the turned-on resistor leg in the first memory data output circuit 723 of the first memory device 720 may be coupled to the turned-on resistor leg in the first controller data output circuit 713 , through the first data transmission line 741 .
  • the first memory calibration circuit 721 may perform the impedance calibration operation by comparing the resistance value of the turned-on resistor leg of the first controller data output circuit 713 and the resistance value of the turned-on resistor leg of the first memory data output circuit 723 .
  • the turned-on resistor leg in the fourth memory data output circuit 735 of the second memory device 730 may be coupled to the turned-on resistor leg in the second controller data output circuit 715 , through the second data transmission line 742 .
  • the second memory calibration circuit 731 may perform the impedance calibration operation by comparing the resistance value of the turned-on resistor leg of the second controller data output circuit 715 with the resistance value of the turned-on resistor leg of the fourth memory data output circuit 735 . Based on the first and second chip calibration select signals CSCALSEL 1 and CSCALSEL 2 generated based on the chip select signal and the calibration select signal CALSEL, the first memory device 720 and the second memory device 730 may be coupled to the first and second data transmission lines 741 and 742 .
  • the first memory device 720 may be coupled to the reference resistor provided from the controller 710 through the first data transmission line 741
  • the second memory device 730 may be coupled to the reference resistor provided from the controller 710 through the second data transmission line 742 .
  • the calibration operations of the first and second memory devices 720 and 730 may be performed simultaneously.
  • Various embodiments of the present disclosure may apply even when a semiconductor system includes three or more memory devices.
  • the respective memory devices may be coupled to different data transmission lines, and the calibration operations of a plurality of memory devices may be performed simultaneously.
  • FIG. 8 is a diagram illustrating an example configuration of a semiconductor system 8 in accordance with an embodiment.
  • the semiconductor system 8 may include a controller 810 and a memory device 820 .
  • the controller 810 may include a controller calibration circuit 812 and a controller data output circuit 813 .
  • the controller calibration circuit 812 may be coupled to an external reference resistor ZQ through a resistor pad 814 , and may perform the calibration operation of the controller 810 .
  • the controller calibration circuit 812 may be coupled to the external reference resistor ZQ based on a first calibration signal CALCOM 1 , and may generate a first pull-up code PC 1 and a first pull-down code NC 1 by using the external reference resistor ZQ.
  • the controller data output circuit 813 may be coupled to a data transmission line 830 through a data pad 811 .
  • the controller data output circuit 813 may include a plurality of pull-up resistor legs and a plurality of pull-down resistor legs.
  • the resistance values of the plurality of pull-up resistor legs may be set based on the first pull-up code PC 1
  • the resistance values of the plurality of pull-down resistor legs may be set based on the first pull-down code NC 1 .
  • the memory device 820 may include a memory calibration circuit 822 and a memory data output circuit 823 .
  • the memory calibration circuit 822 may be coupled to the external reference resistor ZQ through a resistor pad 824 , and may perform the calibration operation of the memory device 820 .
  • the memory calibration circuit 822 may be coupled to the external reference resistor ZQ based on a second calibration signal CALCOM 2 , and may generate a second pull-up code PC 2 and a second pull-down code NC 2 by using the external reference resistor ZQ.
  • the memory data output circuit 823 may be coupled to the data transmission line 830 through a data pad 821 .
  • the memory data output circuit 823 may include a plurality of pull-up resistor legs and a plurality of pull-down resistor legs. The resistance values of the plurality of pull-up resistor legs may be set based on the second pull-up code PC 2 , and the resistance values of the plurality of pull-down resistor legs may be set based on the second pull-down code NC
  • the controller 810 may generate the first and second calibration signals CALCOM 1 and CALCOM 2 for the calibration operations of the controller 810 and the memory device 820 .
  • the enable periods of the first and second calibration signals CALCOM 1 and CALCOM 2 may not overlap each other.
  • the controller calibration circuit 812 may be coupled to the external reference resistor ZQ and perform the calibration operation of the controller 810 .
  • the controller calibration circuit 812 may generate the first pull-up code PC 1 and the first pull-down code NC 1 through the calibration operation.
  • the controller data output circuit 813 may set its resistance values based on the first pull-up code PC 1 and the first pull-down code NC 1 .
  • the memory calibration circuit 822 may be coupled to the external reference resistor ZQ and perform the calibration operation of the memory device 820 .
  • the memory calibration circuit 822 may generate the second pull-up code PC 2 and the second pull-down code NC 2 through the calibration operation.
  • the memory data output circuit 823 may set its resistance values based on the second pull-up code PC 2 and the second pull-down code NC 2 .
  • Various embodiments of the present disclosure may be applied in a similar manner even in the case where a semiconductor system includes a plurality of memory devices.
  • the two or more memory devices may be coupled sequentially to an external reference resistor and perform calibration operations.

Landscapes

  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
US15/417,518 2016-09-12 2017-01-27 Semiconductor device and system performing calibration operation Abandoned US20180075885A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/201,430 US10522203B2 (en) 2016-09-12 2018-11-27 Semiconductor device and system performing calibration operation
US16/201,639 US10354703B2 (en) 2016-09-12 2018-11-27 Semiconductor device and system performing calibration operation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020160117096 2016-09-12
KR1020160117096A KR20180029347A (ko) 2016-09-12 2016-09-12 캘리브레이션 동작을 수행하는 반도체 장치 및 시스템

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US16/201,639 Division US10354703B2 (en) 2016-09-12 2018-11-27 Semiconductor device and system performing calibration operation
US16/201,430 Division US10522203B2 (en) 2016-09-12 2018-11-27 Semiconductor device and system performing calibration operation

Publications (1)

Publication Number Publication Date
US20180075885A1 true US20180075885A1 (en) 2018-03-15

Family

ID=61560906

Family Applications (3)

Application Number Title Priority Date Filing Date
US15/417,518 Abandoned US20180075885A1 (en) 2016-09-12 2017-01-27 Semiconductor device and system performing calibration operation
US16/201,639 Active US10354703B2 (en) 2016-09-12 2018-11-27 Semiconductor device and system performing calibration operation
US16/201,430 Active US10522203B2 (en) 2016-09-12 2018-11-27 Semiconductor device and system performing calibration operation

Family Applications After (2)

Application Number Title Priority Date Filing Date
US16/201,639 Active US10354703B2 (en) 2016-09-12 2018-11-27 Semiconductor device and system performing calibration operation
US16/201,430 Active US10522203B2 (en) 2016-09-12 2018-11-27 Semiconductor device and system performing calibration operation

Country Status (3)

Country Link
US (3) US20180075885A1 (zh)
KR (2) KR20180029347A (zh)
CN (1) CN107818803B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180076983A1 (en) * 2016-09-13 2018-03-15 Toshiba Memory Corporation Semiconductor device and memory system
US10224928B1 (en) * 2018-03-23 2019-03-05 Western Digital Technologies, Inc. On-die impedance calibration
CN111145821A (zh) * 2018-11-05 2020-05-12 爱思开海力士有限公司 终结电路和包括该终结电路的半导体装置
US20200176036A1 (en) * 2018-11-30 2020-06-04 Micron Technology, Inc. Reduction of zq calibration time
US11264064B2 (en) * 2019-12-26 2022-03-01 SK Hynix Inc. Data driving circuit

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102675825B1 (ko) * 2018-11-05 2024-06-18 에스케이하이닉스 주식회사 반도체 장치 및 이를 이용한 반도체 시스템 및 동작 방법
KR20200086137A (ko) 2019-01-08 2020-07-16 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
KR20210027896A (ko) * 2019-09-03 2021-03-11 삼성전자주식회사 캘리브레이션 시간을 줄일 수 있는 멀티 칩 패키지 및 그것의 zq 캘리브레이션 방법
KR102385452B1 (ko) 2020-05-12 2022-04-12 (주)스케일트론 승용차용 타이어 제동력 시험장치
KR102781481B1 (ko) * 2020-05-27 2025-03-17 에스케이하이닉스 주식회사 캘리브레이션 회로 및 그 동작 방법
KR102870854B1 (ko) 2020-06-03 2025-10-13 삼성전자주식회사 가변 레퍼런스 저항을 포함하는 메모리 장치 및 그것의 교정 방법
TWI763174B (zh) * 2020-12-14 2022-05-01 瑞昱半導體股份有限公司 參數校正方法與半導體裝置
US12112827B2 (en) * 2021-11-05 2024-10-08 Samsung Electronics Co., Ltd. Memory device and method for calibrating the device and fabricating the device
TWI888786B (zh) * 2023-01-17 2025-07-01 慧榮科技股份有限公司 介面電路與記憶體控制器
TWI822563B (zh) * 2023-01-17 2023-11-11 慧榮科技股份有限公司 介面電路與記憶體控制器
TWI857460B (zh) * 2023-01-17 2024-10-01 慧榮科技股份有限公司 介面電路、記憶體控制器與校正介面電路內之訊號處理裝置之校正方法
TWI812571B (zh) 2023-01-18 2023-08-11 慧榮科技股份有限公司 介面電路與記憶體控制器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110242916A1 (en) * 2010-04-02 2011-10-06 Samsung Electronics Co., Ltd. On-die termination circuit, data output buffer and semiconductor memory device
US20120099383A1 (en) * 2010-10-20 2012-04-26 Samsung Electronics Co., Ltd. Data output buffer and memory device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100541557B1 (ko) * 2004-04-13 2006-01-10 삼성전자주식회사 메모리 모듈 및 이 모듈의 반도체 메모리 장치의 임피던스교정 방법
US7486104B2 (en) * 2006-06-02 2009-02-03 Rambus Inc. Integrated circuit with graduated on-die termination
KR100879783B1 (ko) * 2007-06-26 2009-01-22 주식회사 하이닉스반도체 온 다이 터미네이션 장치 및 이를 포함하는 반도체메모리장치
US7915912B2 (en) * 2008-09-24 2011-03-29 Rambus Inc. Signal lines with internal and external termination
KR101046242B1 (ko) * 2009-06-30 2011-07-04 주식회사 하이닉스반도체 임피던스 조정 회로 및 이를 이용한 반도체 장치
JP2012244577A (ja) * 2011-05-24 2012-12-10 Elpida Memory Inc 半導体装置
JP2013030001A (ja) * 2011-07-28 2013-02-07 Elpida Memory Inc 情報処理システム
JP2015159435A (ja) * 2014-02-24 2015-09-03 マイクロン テクノロジー， インク． 半導体装置
KR20150142426A (ko) * 2014-06-12 2015-12-22 에스케이하이닉스 주식회사 캘리브레이션 동작을 수행하는 메모리들을 포함하는 반도체 장치
KR102229942B1 (ko) * 2014-07-09 2021-03-22 삼성전자주식회사 멀티 다이들을 갖는 멀티 채널 반도체 장치의 동작 방법 및 그에 따른 반도체 장치
KR20160029392A (ko) * 2014-09-05 2016-03-15 에스케이하이닉스 주식회사 임피던스 조정 회로 및 이를 이용한 반도체 메모리와 메모리 시스템
US20160071568A1 (en) * 2014-09-08 2016-03-10 Shintaro SAKAI Semiconductor memory device
US9317052B1 (en) * 2014-11-24 2016-04-19 SK Hynix Inc. Semiconductor apparatus with calibration circuit and system including the same
KR102646905B1 (ko) 2016-07-21 2024-03-12 삼성전자주식회사 온 다이 터미네이션 회로, 이를 구비하는 메모리 장치 및 메모리 시스템

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110242916A1 (en) * 2010-04-02 2011-10-06 Samsung Electronics Co., Ltd. On-die termination circuit, data output buffer and semiconductor memory device
US20120099383A1 (en) * 2010-10-20 2012-04-26 Samsung Electronics Co., Ltd. Data output buffer and memory device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180076983A1 (en) * 2016-09-13 2018-03-15 Toshiba Memory Corporation Semiconductor device and memory system
US10454721B2 (en) * 2016-09-13 2019-10-22 Toshiba Memory Corporation Semiconductor device and memory system
US20200036561A1 (en) * 2016-09-13 2020-01-30 Kioxia Corporation Semiconductor device and memory system
US10873483B2 (en) * 2016-09-13 2020-12-22 Toshiba Memory Corporation Semiconductor device and memory system
US11381425B2 (en) 2016-09-13 2022-07-05 Kioxia Corporation Semiconductor device and memory system
US11876647B2 (en) 2016-09-13 2024-01-16 Kioxia Corporation Semiconductor device and memory system
US10224928B1 (en) * 2018-03-23 2019-03-05 Western Digital Technologies, Inc. On-die impedance calibration
CN111145821A (zh) * 2018-11-05 2020-05-12 爱思开海力士有限公司 终结电路和包括该终结电路的半导体装置
US20200176036A1 (en) * 2018-11-30 2020-06-04 Micron Technology, Inc. Reduction of zq calibration time
US10891989B2 (en) * 2018-11-30 2021-01-12 Micron Technology, Inc. Reduction of ZQ calibration time
US11264064B2 (en) * 2019-12-26 2022-03-01 SK Hynix Inc. Data driving circuit

Also Published As

Publication number Publication date
US10354703B2 (en) 2019-07-16
KR102684579B1 (ko) 2024-07-15
CN107818803A (zh) 2018-03-20
US20190139586A1 (en) 2019-05-09
CN107818803B (zh) 2021-04-27
KR20230144996A (ko) 2023-10-17
US20190096454A1 (en) 2019-03-28
KR20180029347A (ko) 2018-03-21
US10522203B2 (en) 2019-12-31

Similar Documents

Publication Publication Date Title
US10354703B2 (en) Semiconductor device and system performing calibration operation
US10491215B2 (en) Calibration circuit and calibration apparatus including the same
US9373381B2 (en) System including memories sharing calibration reference resistor and calibration method thereof
US11347670B2 (en) System and interface circuit for driving data transmission line to termination voltage
US10003335B2 (en) Data transmission device, and semiconductor device and system including the same
CN107978331B (zh) 阻抗校准电路和包括其的半导体存储器件
US9317052B1 (en) Semiconductor apparatus with calibration circuit and system including the same
US11030141B2 (en) Apparatuses for independent tuning of on-die termination impedances and output driver impedances, and related methods, semiconductor devices, and systems
US7728619B1 (en) Circuit and method for cascading programmable impedance matching in a multi-chip system
US9197209B2 (en) Semiconductor device
TWI565235B (zh) 電阻校正方法及其校正系統
TWI723210B (zh) 使用校準電路的輸出電路以及包括其的半導體裝置和系統
US9413565B1 (en) Termination circuit, and interface circuit and system including the same
CN116030852A (zh) 执行偏移校准的存储器装置及其操作方法
US10734041B2 (en) Semiconductor apparatus related to termination and semiconductor system including the semiconductor apparatus
US10884961B2 (en) Dynamic termination circuit, semiconductor apparatus and system including the same
KR102489472B1 (ko) 임피던스 교정 회로 및 이를 포함하는 반도체 메모리 장치
CN111145821B (zh) 终结电路和包括该终结电路的半导体装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: SK HYNIX INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JUNG, HAE KANG;REEL/FRAME:041537/0717

Effective date: 20161226

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION