[go: up one dir, main page]

US20180060472A1 - Efficient cell-aware fault modeling by switch-level test generation - Google Patents

Efficient cell-aware fault modeling by switch-level test generation Download PDF

Info

Publication number
US20180060472A1
US20180060472A1 US15/685,034 US201715685034A US2018060472A1 US 20180060472 A1 US20180060472 A1 US 20180060472A1 US 201715685034 A US201715685034 A US 201715685034A US 2018060472 A1 US2018060472 A1 US 2018060472A1
Authority
US
United States
Prior art keywords
circuit
switches
modeling
switch
open
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/685,034
Other languages
English (en)
Inventor
Harry Hai Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US15/685,034 priority Critical patent/US20180060472A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, HARRY HAI
Priority to TW106129444A priority patent/TW201807424A/zh
Priority to CN201710761584.8A priority patent/CN107797051A/zh
Publication of US20180060472A1 publication Critical patent/US20180060472A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G06F17/5036—
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318591—Tools
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/20—Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
    • G06F2217/02—

Definitions

  • the techniques described herein relate generally to producing a switch-level circuit model for automatic test pattern generation.
  • Test pattern generation refers to generating the various permutations of test patterns to thoroughly test a chip. Test pattern generation relies on models of the on-chip circuitry to produce the appropriate test patterns for detecting various faults.
  • Some embodiments relate to circuit modeling method for automatic test pattern generation.
  • An analog circuit representation of a circuit is received.
  • a switch-level representation of the circuit is produced by replacing analog circuit elements of the analog circuit representation with switches and modeling faults in the circuit as switches.
  • Some embodiments relate to a non-transitory computer readable storage medium, which, when executed, perform such a method.
  • Some embodiments relate to an apparatus comprising a processor and a non-transitory computer readable storage medium, which, when executed, perform such a method.
  • FIG. 1 illustrates the process flow to produce a model used for automatic test pattern generation based on analog circuit simulations.
  • FIG. 2 shows a modified method that can significantly reduce or eliminate the need for analog circuit simulations.
  • FIG. 3 shows an example of the way in which the method of FIG. 2 may be performed.
  • FIG. 4 illustrates switch models for resistors, capacitors, short circuit faults and open circuit faults.
  • FIGS. 5A and 5B illustrate a switch level model that can be used to model open-circuit faults ( FIG. 5A ) and short-circuit faults ( FIG. 5B ) for a 4-input AOI22 standard cell.
  • FIG. 5C shows the schematic diagram of an analog circuit representation of a NAND2 cell.
  • FIG. 6 shows a channel connected network of an AOI22 CMOS cell.
  • FIG. 7 shows the CCN-open circuit model.
  • FIG. 8 shows CCN-open V o (t) plots over full range of defect resistance ⁇ .
  • FIG. 9 shows the resistor network associated with this interconnect along with the p component values.
  • FIG. 10 depicts the CCN-short defect test condition.
  • FIG. 11 shows CCN-short V o (t) plots over full range of defect resistance ⁇ .
  • FIG. 12 shows the result of analog simulation for a 2-cycle transition pattern to test AOI22 bridging fault #12 between nodes C and D in FIG. 5B .
  • FIG. 13 is a block diagram of an illustrative computing device.
  • the techniques described herein relate to fault models that can be used to produce test patterns to test a digital circuit.
  • the present inventor has recognized and appreciated that prior models either failed to capture behaviors of the digital circuit that needed to be tested, or required excessive processing capabilities due to models that required extensive analog simulations.
  • “Gate level” fault models have been used to model logic gates for the purposes of test pattern generation. However, as technology progresses and transistor sizes continue to decrease, analog circuit effects become more prominent, and gate level fault models may not be sufficient to account for various types of faults. As a result, the test patterns that are generated are not designed to test for such faults, and chips may not be adequately tested.
  • analog circuit simulations have been used to provide higher modelling accuracy.
  • performing analog circuit simulations to model a complex modern integrated circuit may be prohibitive in computational complexity, and may take weeks or months to perform.
  • switch-level fault models can have improved accuracy over gate level fault models and reduced computational complexity with respect to analog circuit simulations.
  • a “cell” may be a basic digital circuit building block such as a multiplexer, logic gate, etc. Rather than designing such building blocks from scratch each time they are needed, a circuit designer may select an appropriate cell from the library having suitable characteristics such as output drive capability, power consumption, area, etc.
  • a fault model may be generated for each cell in the library.
  • a fault model is a representation of the cell that takes into account the possibility of various types of faults at a number of locations within the cell. Examples of fault types that may be taken into account include inputs or outputs stuck at logic-0 or 1, for example.
  • a gate level model of the multiplexer may take into account the possibility that one or more of the inputs or output is stuck at logic-0 or 1. Based on such a model, automatic test pattern generation may generate a sequence of test signals to test whether an instance of a multiplexer has these faults.
  • a gate-level model does not take into account all the faults that may occur within the cell, particularly as transistors become smaller in size and analog circuit effects become more prominent. Accordingly, a more accurate model is needed.
  • FIG. 1 illustrates the process flow to produce a model used for automatic test pattern generation based on analog circuit simulations.
  • Cell layout and extraction may be performed. Based on the extracted layout, the parasitics (e.g., parasitic resistance, capacitance and/or inductance) may be determined.
  • a circuit representation may be produced. As an example, a netlist (e.g., a SPICE netlist) may be generated.
  • the circuit representation is then updated to include one more defects to be tested. For each defect, an analog circuit simulation is run (e.g. in an analog circuit simulation tool, such as HSPICE, for example) for various combinations of inputs and analog input levels to determine the effect the defect has for each combination. Based on the simulation results, a model of the cell is generated that can be used for automatic test pattern generation.
  • the inventor has recognized and appreciated that performing the analog circuit simulations is a bottleneck, and can take weeks or months to run for all the cells in library.
  • the “Testbench generator” block generates all possible input conditions. For example, a 4-input cell would result in 32 2-cycle patterns being generated. A single cell library with 3 corners, 200 cells, average 32 patterns per cell, 200 defects per cell, and 3 parameters per defect would result in 11,520,000 SPICE runs. At 2 seconds per SPICE run, it would take 267.7 days to process the library. To process the library in 7 days, 38 SPICE licenses would be needed to run 38 jobs in parallel in the computing farm.
  • FIG. 2 shows a modified method that can significantly reduce or eliminate the need for analog circuit simulations.
  • a switch-level circuit representation can be produced including one or more defects.
  • the switch-level circuit representation may account for most, if not all, defects, allowing the number of analog circuit simulations to be reduced or eliminated.
  • the switch-level circuit representation may then be used for automatic test pattern generation.
  • the method of FIG. 2 requires less than 0.25% of the computation needed by the method of FIG. 1 .
  • FIG. 3 shows an example of the way in which the method of FIG. 2 may be performed.
  • a circuit representation including parasitics and faults is converted into a switch-level circuit representation.
  • the parasitics and faults that were represented by their analog circuit representations, such as capacitors and resistors, are converted into switches having suitable gate drive signals.
  • a resistor may be converted into a NMOS switch having a logic 1 applied to its gate
  • a capacitor may be converted into an NMOS switch having a logic 0 applied to its gate.
  • a PMOS switch may be used with the opposite logic value applied to its gate.
  • FIG. 4 illustrates that faults can be modeled as switches stuck open or closed.
  • a short circuit fault can be modeled as an NMOS switch having its gate tied to logic 1.
  • An open-circuit fault can be modeled as an NMOS switch having its gate tied to logic 0.
  • a PMOS switch may be used with the opposite logic value applied to its gate.
  • FIGS. 5A and 5B illustrate a switch level model that can be used to model open-circuit faults ( FIG. 5A ) and short-circuit faults ( FIG. 5B ) for a 4-input AOI22 standard cell. It should be appreciated that the techniques described herein are not limited to such a cell and can be applied to any suitable cell, portion of a cell, or combination of cells.
  • FIG. 5A illustrates the locations at which the switch-level model of an open circuit fault (e.g., switch stuck open) may be inserted to account for open circuit faults throughout the cell.
  • FIG. 5B illustrates the locations at which the switch-level model of a short circuit fault (e.g., switch stuck closed) may be inserted to account for short circuit faults throughout the cell.
  • a circuit representation is a netlist.
  • a netlist may include a textual representation of a circuit, such as the circuit components included and their interconnections.
  • a netlist may be used by analog circuit simulation tools, such as SPICE, for example, to perform simulations with various input parameters.
  • An analog circuit representation may be a netlist that describes the interconnections between analog circuit elements such as capacitors, resistors and transistors.
  • converting an analog circuit representation may include replacing the capacitors and resistors in the analog circuit representation with switches, as mentioned above. If an analog circuit representation includes a netlist, converting the netlist into a switch-level representation can be performed by replacing the netlist representation of the resistors and capacitors with switches.
  • the text in the netlist representing resistors and capacitors may be replaced with text representing switches having their inputs tied to a suitable logic level.
  • the conversion may be performed automatically by software having instructions, which, when executed, replace the text in the netlist representing resistors and capacitors with text representing switches having their inputs tied to a predetermined logic level.
  • a similar conversion may be performed for faults represented as resistors or capacitors.
  • a netlist may represent electrical devices with terminals connected together by nets.
  • the analog circuit netlist may include transistors, resistors, and capacitors.
  • Transistors have 3 functional terminals (drain, gate, and source) with the 4th non-functional terminal (bulk) tied to a power supply rail.
  • Wiring parasitics in the layout are extracted as 2-terminal resistors and capacitors. Each device has additional parameters that govern their electrical behavior which is used for accurate analog circuit simulation of the standard cell.
  • FIG. 5C shows the schematic diagram of an analog circuit representation of a NAND2 cell.
  • the SPICE netlist is reproduced in Table 1. Analog parameters are not shown in the SPICE netlist because they are ignored in creating the switch-level netlist.
  • the cell has 2 functional inputs ⁇ A1, A2 ⁇ and 1 output ⁇ ZN ⁇ , and power supply rails ⁇ VDD, VSS ⁇ .
  • the SPICE netlist can be converted to a simplified switch-level netlist as follows. Each transistor is converted to a logic switch of the same type (ignoring the bulk terminal). Each resistor is converted to an NMOS switch whose gate is tied to logic 1. Each capacitor is converted to an NMOS switch whose gate is tied to logic 0. The nets' mapping is unchanged and connects switch terminals in the switch-level netlist.
  • Table 2 shows netlist conversion of the NAND2 cell from SPICE to switch-level. Although SPICE analog parameters are ignored, switches have discrete conductance and nets have discrete capacitance strength values that govern their digital behavior in the switch-level simulation of the standard cell. Strength values are assigned according to the design style's operating principle. Eight strength values are sufficient to capture the behavior of most digital design styles. In the switch-level algebra defined by Bryant, the strongest input strength ⁇ is assigned to power supply rails while the weakest strength ⁇ is the algebra's NULL element. For digital CMOS circuits, NMOS and PMOS switches have the same conductance strength ⁇ 2. Resistor and capacitor switches have conductance strength ⁇ 3 (for defect modeling). All nets have capacitance strength ⁇ 2, except for cell outputs which are assigned ⁇ 3. Cell inputs are assigned ⁇ . The eight strength values and ordering from strongest to weakest are:
  • a “stuck-open” transistor is unable to turn on fully as in the normal case.
  • a “stuck-closed” transistor is unable to turn off fully as in the normal case.
  • An “open” wire segment in the layout means higher than normal resistance in the corresponding parasitic resistor.
  • a “short” between two distinct wire segments in the layout means a resistive bridge across the terminals of the corresponding parasitic capacitor.
  • Equivalent switch-level defects may be obtained as follows.
  • a “stuck-open” transistor maps to a switch that cannot conduct signal between drain & source. Above this is referred to as a switch stuck-open fault.
  • a “stuck-closed” transistor maps to a switch that cannot cut off drain-source signal conduction. Above this is referred to as a switch stuck-closed fault.
  • An “open” parasitic resistor maps to a stuck-open fault of the corresponding NMOS switch whose gate is tied to logic-1.
  • a “short” across a parasitic capacitor maps to a stuck-closed fault of the corresponding NMOS switch whose gate is tied to logic 0.
  • analog defects can have a range of parameter values (for example, parameter values ⁇ 1 ohm, 1 K-ohm, 1 M-ohm ⁇ for a resistive short defect).
  • the corresponding switch-level defects do not need such parameter values since their purpose is to serve as seed objectives for switch-level test generation (SL-ATPG).
  • a switch-level circuit model can be used for automated test pattern generation.
  • candidate patterns applied to the cell inputs are simulated in SPICE (slow analog simulator), once in defect-free case, and once for each defect and associated defect parameter value.
  • SPICE slow analog simulator
  • the difference in cell output responses are compared between the defect-free and defect-injected cases to determine if the candidate pattern can detect the defect and its associated parameter value as an output stuck-at or transition delay fault.
  • a defect-detecting pattern so determined becomes part of the cell-aware fault model.
  • each entry consists of the cell input pattern, the output fault type (stuck-at or transition delay), and the corresponding detected defects.
  • SL-ATPG obtains useful input patterns directly without going through the “trial-and-error” process of the conventional flow by targeting equivalent switch-level defects.
  • SL-ATPG uses well-known and efficient test generation techniques (such as from PODEM) to direct the search for useful input patterns.
  • the search process involves using switch-level simulation (orders of magnitude faster than analog simulation) to guide how cell inputs should be assigned, i.e., which inputs, what logic values. If no useful input patterns could be found, SL-ATPG identifies the defect as undetectable.
  • the output fault model can be inferred directly for many types of defects.
  • analog fault simulation of a judiciously chosen defect parameter value may be used to validate the cell-aware fault model.
  • This application describes techniques that can drastically reduce the expensive analog fault simulation currently used to create cell-aware fault models.
  • most defects in the transistor-level netlist containing parasitics can be represented by just two canonical fault classes.
  • the two canonical fault classes can be modeled by transistor switch stuck-open and stuck-closed faults. Rather than enumerating the full combination cell input patterns to search for defect detection conditions by analog fault simulation, switch-level test generation can obtain those input conditions directly, thereby reducing significantly the role of analog simulation to that of ranking conditions in terms of detection effectiveness.
  • SoC system-on-chip
  • the digital portion of today's complex system-on-chip (SoC) is predominantly constructed from a technology library of pre-defined standard cells using an automated RTL-to-GDS tools-chain flow.
  • Each cell implements a logic function offered in a variety of output drive configurations. Cell functions range from simple to complex and cover both combinational and sequential behaviors.
  • the logic synthesis tool maps the design's RTL description to a netlist of interconnected standard cells. Additional tools then perform further optimizations on the netlist to meet area, timing, power, and test goals as the design implementation is transformed into physical mask layers for fabrication.
  • DFT scan design-for-test
  • AVG automatic test pattern generation
  • Typical fault models include stuck-at (SAF), transition delay (TDF), and interconnect bridges.
  • SAF stuck-at
  • TDF transition delay
  • CAT cell-aware testing
  • each defect is injected into the cell's SPICE netlist and analog simulation is performed to find all cell input conditions that could produce a SAF or TDF effect at one or more cell outputs.
  • the set of input conditions and output fault effects then becomes the so-called user-defined fault model (UDFM) which is passed to gate-level ATPG for full-chip processing.
  • UDFM extends existing SAF and TDF models by introducing logic constraints on additional cell input pins to better reflect knowledge about how each internal defect in the transistor implementation can affect the cell's outward behavior.
  • CAT view generation for a technology library is a one-time characterization effort, it still involves massive analog fault simulation runs that could take weeks to complete; or require an inordinate number of SPICE simulator licenses for parallel runs that ties up valuable computing resources needed for other design tasks.
  • UDFM is a digital abstraction of analog fault effects, meaning much of the accurate details from analog simulation are not transferred because it would be impractical for the gate-level ATPG tool to fully consider them when design sizes are in the millions of gates.
  • some analog information may be useful to improve the effectiveness of generated patterns.
  • stand-alone cell characterization may be inaccurate because the analog simulation fails to account for design context dependency at cell instance pins. This last point will be elaborated further in Section II-B.
  • switch-level ATPG is applied to reason about the underlying switching logic and to quickly identify all defect-detecting input conditions.
  • ATPG replaced stand-alone trial-and-error fault simulation because ATPG algorithms used knowledge of logic structures to efficiently search for useful input patterns.
  • SL-ATPG working on a simplified model of the transistor circuit is orders-of-magnitude more efficient than analog fault simulation of all enumerated input conditions along with transient analysis to check for defect detection.
  • defects in a class can be represented by stuck-open/off or stuck-closed/on switches for targeting by SL-ATPG.
  • SL-ATPG may not replace analog fault simulation entirely, but it can take over those tasks that do not require analog circuit-level details. For example, SL-ATPG can quickly determine when conditions to sensitize a defect are logically impossible due to reconvergent fanout (most cell input ports fan out to NMOS and PMOS transistors that converge to the same channel-connected CMOS switch network). Analog fault simulation will need to try all enumerated conditions before reaching the same conclusion.
  • CMOS circuits The basic transistor used in CMOS circuits is a three-terminal device.
  • the gate (g) terminal controls current flow in the channel between source (s) and drain (d) terminals.
  • PMOS NMOS
  • g 0(1) cuts off signal flow.
  • the following discussion uses the switch-level schematic of the AOI22 CMOS cell in FIG. 6 for illustration.
  • a channel-connected network is comprised of switches (numbered 1 through 8) linked by their channels and nodes (labeled C, D, E, Y) joining channel terminals s and d.
  • the CCN (shaded region) is bounded by power nodes Vdd and Gnd.
  • power nodes connect many CCNs, but activities in the CCNs do not couple via the power nodes.
  • CCN switch g terminals are driven by unidirectional inputs (A0, A1, B0, B1) and they determine the states of CCN nodes.
  • Some CCN nodes are designated as outputs (Y) which generally feed g inputs of other CCNs.
  • CCNs form a natural partitioning where signal changes flow from one CCN to the next via strictly unidirectional switch g inputs.
  • signals flowing across bidirectional channels are controlled by g inputs and an iterative algorithm is used to simultaneously solve for multiple node states.
  • switch g inputs When one CCN feeds another via switch g inputs, a key aspect is that behaviors in the downstream CCN do not affect the upstream CCN unless there are explicit feedback signal paths in the design netlist.
  • the single CCN example in FIG. 6 matches a library cell exactly. But that is not always the case. Larger cells may contain multiple CCNs. e.g., a full-adder cell. More interestingly, a single CCN may also span multiple library cells. This situation arises with cells that use pass-switch logic implemented by CMOS transmission gates. Such a cell may have input ports that feed switch channel terminals directly. In the design, such cell instance pins will be driven by other cell instance outputs. Thus driving and receiving CCNs merge to form a single CCN in the design.
  • the bridge merges the CCN driving g with the CCN containing the s-d channel. Every defect instance in the design will potentially create unique merged CCN configurations. Stand-alone cell defect characterization may not capture the unique design context-dependent behaviors accurately.
  • CCN output nodes may include: Open, Bridge, Tleak. and Tdrive. The rest of this Appendix will focus on these defect types.
  • CAT has revived much interest to detect cell internal defects via more efficient test generation schemes.
  • a common strategy among these works is to leverage existing Boolean algebraic methods by transformations into the gate-level domain preserving essential aspects of defect behaviors to be tested.
  • these transformations assume fully complementary NMOS and PMOS switch network implementation of CMOS gates, which encounters practical limitations when cells employ alternative structures such as pass-switch logic. More subtle CCN behaviors affecting test quality may be lost in the translation as well.
  • SL-ATPG is a more general and viable alternative that can handle a broader range of design situations with better implementation fidelity. With the exponential advance in computing power over the past thirty years. SL-ATPG can easily cope with circuit complexity at the scope of library cells or a few merged CCNs.
  • SL-ATPG can readily treat faults associated with passive interconnects and parasitic R/C elements.
  • an open wire replace the wire by a virtual NMOS switch whose channel s/d terminals match the two wire ends and tie the g terminal to logic-1 (normally always conducting). The open wire is then equivalent to the switch stuck-open fault.
  • a virtual NMOS switch whose channel connects the two nodes and tie the g terminal to logic-0 (normally always disconnected). The bridge is then equivalent to the switch stuck-closed fault.
  • FIG. 5A open faults on 17 possible CCN wire segments (numbered 9 to 25) are shown in the AOI22 schematic. (Note new node labels due to node splits.) Targeting these along with the 8 switch stuck-open faults (numbered 1 to 8) under single fault assumption and optimistic treatment of charge-sharing. SL-ATPG generated robust 2-cycle patterns to achieve 100% coverage of all 25 faults.
  • the switch-level model assigns discrete and ranked capacitive strength levels. ⁇ 3> ⁇ 2> ⁇ 1, to each non-power node. When two nodes storing different logic values are connected by a switch, the node with the higher strength will dominate and propagate its value to the other node. In the previous SL-ATPG experiment, all non-power nodes are assigned ⁇ 2. Assigning ⁇ 3 to node Y will prevent corruption by charge-sharing at output Y. To assess worst-case charge-sharing. Y was lowered to ⁇ 2 for another SL-ATPG run with cycle count increased to 3 to allow extra “non-conflict” initializations of internal nodes.
  • FIG. 5B shows 14 possible node-pair bridging fault locations (numbered 9 to 22) involving the CCN node set ⁇ C, D, E, Y ⁇ . Adding the 8 switch stuck-closed faults (number 1 to 8) brings the total to 22. Ranked above capacitive strengths are switch conductance strength levels. ⁇ 3> ⁇ 2> ⁇ 1> ⁇ 's. The path conductance of a series-linked chain of switches rooted at a power node is the minimum conductance of the set. When two paths driven by different power node values converge at a non-power node, the higher strength path dominates, driving its value onto the node.
  • both NMOS and PMOS functional switches are assigned ⁇ 2 since CMOS designs typically do not depend on conductance ratios.
  • To generate patterns to achieve hard detection at Y (good/faulty 0/1 or 1/0), we make two SL-ATPG runs with all PMOS switches weakened in the first run and vice versa for NMOS switches in the second run. All non-functional bridging fault virtual switches are assigned ⁇ 3 to make their impacts felt.
  • cycle-1 bypasses the faulty switch to initialize a CCN output to a known value
  • cycle-2 drives the opposite value onto the output exclusively through the stuck-open switch.
  • the fault is detected as a SAF in cycle-2 because in the faulty circuit, the output capacitor could not be charged or discharged thus retaining the initialized value.
  • TDF detection at the output is allowed, then we can extend this scheme to check for a delayed output transition time. i.e., slower capacitor charge/discharge rate in the faulty circuit. Since charge/discharge rate is proportional to the path's RC time constant, all defects along the path that increases resistance potentially can also be detected.
  • These CCN-open defects comprise Tdrive and Open from which are physically associated with transistors and interconnect parasitic resistors respectively.
  • CCN-open testing can be characterized by the simple RC circuit model shown in FIG. 7 , which shows the CCN-open circuit model.
  • the circuit reflects the test condition in cycle-2 where V o (t) is the output voltage in time starting from the end of initialization.
  • R is the charge/discharge path resistance.
  • C is the output capacitance.
  • V i is the initialized voltage at the end of cycle-1.
  • V i is the driving voltage for cycle-2.
  • ⁇ governs the rate of output change.
  • CMOS design property P1 CMOS design property
  • V o (t) Plots of V o (t) are shown for both cases in FIG. 8 as R varies from minimum to infinity illustrating various degrees of defect impact spanning minimal small-delay TDF to worst-case floating SAF. Based on our CCN-open analysis, the following key points can be made:
  • K1—TDF is the UDFM for all CCN-open defects since a transition is required and the floating SAF is just a special case of TDF where the delay is “forever”.
  • K2—CCN-open defects can be detected by transition patterns targeting proxy switch stuck-open faults.
  • analog simulation could have a role to preferentially rank patterns obtained by SL-ATPG. Since the actual value of defect resistance is unknown, one could choose a single moderately large p value to simulate each pattern with. By comparing delay size impact, patterns can be ranked for gate-level ATPG to choose, favoring those with the largest impact to enhance test effectiveness.
  • interconnect-related capacitors and resistors number 478 and 29 respectively. All are defect candidates taking up a large proportion of analog fault simulation time for that cell.
  • FIG. 9 shows the resistor network associated with this interconnect along with the ⁇ component values.
  • Vdd charges Y via B1:p ⁇ channel, the ⁇ network, and A0:p ⁇ channel as indicated by the dotted line.
  • the ⁇ network resistance is 210 ⁇ derived from ⁇ 2 in parallel with ⁇ 1+ ⁇ 3.
  • Open fault #13 is an example of a “cross-wire open” which is important to detect.
  • the real issue highlighted by this example is the risk of using parasitic elements as defect candidates. Given the frequent occurrence of parallel resistor structures, much wasteful analog simulation could result.
  • CCN-short defects comprise Tleak and Bridge which are physically associated with transistors and interconnect parasitic capacitors, respectively.
  • a necessary test condition is for the two nodes to be at opposite states; otherwise the defect's presence will not be apparent. Given opposite node states, the presence of the defect will create a conduction path between Vdd and Gnd. Along the path composed of resistors, nodes will have divided voltage values. For voltage detection of the defect at a CCN output, there needs to be an observable signal path from a node on the Vdd-Gnd path to that output.
  • the RC circuit model in FIG. 10 depicts the CCN-short defect test condition.
  • R u (R d ) is the pull-up (down) resistor network with respect to node V r , and the observation path is from V r through R o to output V o .
  • the test condition applies a 2-cycle pattern to allow TDF detection.
  • V o (t) is the output transient starting from the end of cycle-1.
  • V i is the initial voltage at output capacitor C.
  • V f is the steady-state voltage reached at the end of cycle-2. Its value is derived from the resistive divider relationship of R u and R d .
  • ⁇ determines the rate of output change.
  • CMOS design property P2 the defect cannot exist in R o ; otherwise R o and R d constitutes a non-faulty Vdd to Gnd path.
  • CMOS design property P1 the defect exists either in R u or in R d to enable a path to Vdd or Grind that should be normally non-conducting. There are two cases to consider:
  • K4—2-cycle TDF is the UDFM for all CCN-short defects that covers the full range of p starting from zero.
  • 1-cycle SAF UDFM holds for a much limited p range.
  • K5—CCN-short defects can be detected by transition patterns targeting proxy switch stuck-closed faults. Since SL-ATPG generates a 1-cycle pattern for such faults, a prior initialization cycle needs to be added to create a transition pattern. Robust transition is unnecessary as the output is driven in both cycles.
  • V f must fall below (rise above) 0-threshold (1-threshold) for SA0 (SA1).
  • the gap between V f and the threshold can be a metric for pattern ranking—larger is better.
  • FIG. 12 shows the result of analog simulation for a 2-cycle transition pattern to test AOI22 bridging fault #12 between nodes C and D in FIG. 5B .
  • Three ⁇ ohmic values were tried: 12T for no defect, 4K, and zero (worst case).
  • V f reached above the 1-threshold of 0.6V which maps to a TDF with extra delay of 13 ps.
  • V f eventually reaches 0.39V. Therefore, SA0 is disqualified for any value of ⁇ , but the defect can still be detected as a TDF.
  • techniques described herein may be carried out using one or more computing devices. Embodiments are not limited to operating with any particular type of computing device.
  • FIG. 13 is a block diagram of an illustrative computing device 1000 .
  • Computing device 1000 may include one or more processors 1001 and one or more tangible, non-transitory computer-readable storage media (e.g., memory 1003 ).
  • Memory 1003 may store, in a tangible non-transitory computer-recordable medium, computer program instructions that, when executed, implement any of the above-described functionality.
  • Processor(s) 1001 may be coupled to memory 1003 and may execute such computer program instructions to cause the functionality to be realized and performed.
  • Computing device 1000 may also include a network input/output (I/O) interface 1005 via which the computing device may communicate with other computing devices (e.g., over a network), and may also include one or more user I/O interfaces 1007 , via which the computing device may provide output to and receive input from a user.
  • the user I/O interfaces may include devices such as a keyboard, a mouse, a microphone, a display device (e.g., a monitor or touch screen), speakers, a camera, and/or various other types of I/O devices.
  • the embodiments can be implemented in any of numerous ways.
  • the embodiments may be implemented using hardware, software or a combination thereof.
  • the software code can be executed on any suitable processor (e.g., a microprocessor) or collection of processors, whether provided in a single computing device or distributed among multiple computing devices.
  • any component or collection of components that perform the functions described above can be generically considered as one or more controllers that control the above-discussed functions.
  • the one or more controllers can be implemented in numerous ways, such as with dedicated hardware, or with general purpose hardware (e.g., one or more processors) that is programmed using microcode or software to perform the functions recited above.
  • one implementation of the embodiments described herein comprises at least one computer-readable storage medium (e.g., RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or other tangible, non-transitory computer-readable storage medium) encoded with a computer program (i.e., a plurality of executable instructions) that, when executed on one or more processors, performs the above-discussed functions of one or more embodiments.
  • the computer-readable medium may be transportable such that the program stored thereon can be loaded onto any computing device to implement aspects of the techniques discussed herein.
  • the invention may be embodied as a method, of which an example has been provided.
  • the acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
US15/685,034 2016-08-30 2017-08-24 Efficient cell-aware fault modeling by switch-level test generation Abandoned US20180060472A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US15/685,034 US20180060472A1 (en) 2016-08-30 2017-08-24 Efficient cell-aware fault modeling by switch-level test generation
TW106129444A TW201807424A (zh) 2016-08-30 2017-08-30 自動測試樣式生成的電路建模方法、非暫態電腦可讀存儲介質以及自動測試樣式生成電路
CN201710761584.8A CN107797051A (zh) 2016-08-30 2017-08-30 自动测试样式生成的电路建模方法以及自动测试样式生成电路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662381040P 2016-08-30 2016-08-30
US15/685,034 US20180060472A1 (en) 2016-08-30 2017-08-24 Efficient cell-aware fault modeling by switch-level test generation

Publications (1)

Publication Number Publication Date
US20180060472A1 true US20180060472A1 (en) 2018-03-01

Family

ID=61242813

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/685,034 Abandoned US20180060472A1 (en) 2016-08-30 2017-08-24 Efficient cell-aware fault modeling by switch-level test generation

Country Status (3)

Country Link
US (1) US20180060472A1 (zh)
CN (1) CN107797051A (zh)
TW (1) TW201807424A (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113514751A (zh) * 2020-06-25 2021-10-19 台湾积体电路制造股份有限公司 识别集成电路缺陷的系统和方法以及计算机可读存储介质
US20210326506A1 (en) * 2020-04-20 2021-10-21 Synopsys, Inc. Method and system for custom model definition of analog defects in an integrated circuit
US11182525B1 (en) * 2020-07-07 2021-11-23 Infineon Technologies Ag Fault aware analog model (FAAM)
CN114510890A (zh) * 2021-01-27 2022-05-17 台湾积体电路制造股份有限公司 测试电路模型的方法和器件以及非暂时性计算机可读介质
US20220351795A1 (en) * 2019-09-03 2022-11-03 Technische Universiteit Delft Device Aware Test for Memory Units
US11579994B2 (en) * 2020-04-16 2023-02-14 Synopsys, Inc. Fast and scalable methodology for analog defect detectability analysis
US11635462B2 (en) * 2020-08-27 2023-04-25 Siemens Industry Software Inc. Library cell modeling for transistor-level test pattern generation
US11663387B2 (en) 2018-08-31 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Fault diagnostics
US20240193336A1 (en) * 2022-12-12 2024-06-13 Synopsys, Inc. Automatic test pattern generation to increase coverage in detecting defects in analog circuits

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI689835B (zh) * 2018-06-13 2020-04-01 瑞昱半導體股份有限公司 用於適應性電壓縮放以消除整體設計之延遲變異的方法與裝置
CN110268404B (zh) 2019-05-09 2020-09-25 长江存储科技有限责任公司 用于功能对等检测中的仿真方法
TWI719917B (zh) * 2020-07-14 2021-02-21 金麗科技股份有限公司 將類比動態電路運用於數位測試工具的處理方法
TWI768536B (zh) * 2020-11-06 2022-06-21 瑞昱半導體股份有限公司 積體電路模擬及設計方法與系統
CN113919281A (zh) * 2021-05-25 2022-01-11 杨家奇 一种测试芯片版图的生成方法
CN116127657A (zh) * 2021-11-15 2023-05-16 长鑫存储技术有限公司 芯片版图结构以及仿真测试方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278769A (en) * 1991-04-12 1994-01-11 Lsi Logic Corporation Automatic logic model generation from schematic data base
US5629858A (en) * 1994-10-31 1997-05-13 International Business Machines Corporation CMOS transistor network to gate level model extractor for simulation, verification and test generation
US20050262454A1 (en) * 1999-09-27 2005-11-24 International Business Machines Corporation Method for VLSI system debug and timing analysis

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002101601A2 (en) * 2001-06-08 2002-12-19 Magma Design Automation, Inc. Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
US8359558B2 (en) * 2010-03-16 2013-01-22 Synopsys, Inc. Modeling of cell delay change for electronic design automation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278769A (en) * 1991-04-12 1994-01-11 Lsi Logic Corporation Automatic logic model generation from schematic data base
US5629858A (en) * 1994-10-31 1997-05-13 International Business Machines Corporation CMOS transistor network to gate level model extractor for simulation, verification and test generation
US20050262454A1 (en) * 1999-09-27 2005-11-24 International Business Machines Corporation Method for VLSI system debug and timing analysis

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11663387B2 (en) 2018-08-31 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Fault diagnostics
US11869612B2 (en) * 2019-09-03 2024-01-09 Technische Universiteit Delft Device aware test for memory units
US20220351795A1 (en) * 2019-09-03 2022-11-03 Technische Universiteit Delft Device Aware Test for Memory Units
US11579994B2 (en) * 2020-04-16 2023-02-14 Synopsys, Inc. Fast and scalable methodology for analog defect detectability analysis
US11763056B2 (en) * 2020-04-20 2023-09-19 Synopsys, Inc. Method and system for custom model definition of analog defects in an integrated circuit
US20210326506A1 (en) * 2020-04-20 2021-10-21 Synopsys, Inc. Method and system for custom model definition of analog defects in an integrated circuit
US20210407614A1 (en) * 2020-06-25 2021-12-30 Taiwan Semiconductor Manufacturing Company Limited Systems and methods to detect cell-internal defects
US11295831B2 (en) * 2020-06-25 2022-04-05 Taiwan Semiconductor Manufacturing Company Limited Systems and methods to detect cell-internal defects
US11837308B2 (en) 2020-06-25 2023-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods to detect cell-internal defects
CN113514751A (zh) * 2020-06-25 2021-10-19 台湾积体电路制造股份有限公司 识别集成电路缺陷的系统和方法以及计算机可读存储介质
US11182525B1 (en) * 2020-07-07 2021-11-23 Infineon Technologies Ag Fault aware analog model (FAAM)
US11635462B2 (en) * 2020-08-27 2023-04-25 Siemens Industry Software Inc. Library cell modeling for transistor-level test pattern generation
US20220237353A1 (en) * 2021-01-27 2022-07-28 Taiwan Semiconductor Manufacturing Company Limited Fault detection of circuit based on virtual defects
CN114510890A (zh) * 2021-01-27 2022-05-17 台湾积体电路制造股份有限公司 测试电路模型的方法和器件以及非暂时性计算机可读介质
US20240193336A1 (en) * 2022-12-12 2024-06-13 Synopsys, Inc. Automatic test pattern generation to increase coverage in detecting defects in analog circuits

Also Published As

Publication number Publication date
TW201807424A (zh) 2018-03-01
CN107797051A (zh) 2018-03-13

Similar Documents

Publication Publication Date Title
US20180060472A1 (en) Efficient cell-aware fault modeling by switch-level test generation
US6499129B1 (en) Method of estimating performance of integrated circuit designs
US7590953B2 (en) Static timing analysis and dynamic simulation for custom and ASIC designs
Bryant A survey of switch-level algorithms
US7000202B1 (en) Method of vector generation for estimating performance of integrated circuit designs
US8484590B2 (en) Method of predicting electronic circuit floating gates
Huang et al. Methodology of generating dual-cell-aware tests
Mongelli et al. A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation
Chen et al. Efficient cell-aware fault modeling by switch-level test generation
Pant et al. Static timing analysis considering power supply variations
Chuang et al. Cell-aware test generation time reduction by using switch-level ATPG
Loiacono et al. Fast cone-of-influence computation and estimation in problems with multiple properties
Ladhar et al. Efficient and accurate method for intra-gate defect diagnoses in nanometer technology and volume data
De Jonghe et al. Advances in variation-aware modeling, verification, and testing of analog ICs
Chen et al. Improving Efficiency of Cell-Aware Fault Modeling By Utilizing Defect-Free Analog Simulation
Lin et al. On modeling CMOS library cells for cell internal fault test pattern generation
Kashyap et al. Silicon feedback to improve frequency of high-performance microprocessors-an overview
Xu et al. Mutant generation for analog circuit designs
Gao et al. Reducing library characterization time for cell-aware test while maintaining test quality
Mongelli et al. Accelerating Cell-Aware Model Generation for Sequential Cells using Graph Theory
Taatizadeh et al. An automated SAT-based method for the design of on-chip bit-flip detectors
Mongelli et al. A Defect-Detection Graph-Based Methodology for Cell-Aware Model Generation
Alagappan Dictionary-Less Defect Diagnosis as Real or Surrogate Single Stuck-At Faults
Barceló et al. An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation
Hopsch et al. Characterization of digital cells for statistical test

Legal Events

Date Code Title Description
AS Assignment

Owner name: MEDIATEK INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, HARRY HAI;REEL/FRAME:043384/0125

Effective date: 20170824

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION