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US20180006189A1 - Epitaxial structure with tunnel junction, p-side up processing intermediate structure and method of manufacturing the same - Google Patents

Epitaxial structure with tunnel junction, p-side up processing intermediate structure and method of manufacturing the same Download PDF

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Publication number
US20180006189A1
US20180006189A1 US15/432,069 US201715432069A US2018006189A1 US 20180006189 A1 US20180006189 A1 US 20180006189A1 US 201715432069 A US201715432069 A US 201715432069A US 2018006189 A1 US2018006189 A1 US 2018006189A1
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type semiconductor
semiconductor layer
layer
tunnel junction
substrate
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US15/432,069
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Tzu-Wen Wang
Wei-Yu Tseng
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Epileds Technologies Inc
Epileds Tech Inc
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Epileds Tech Inc
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Assigned to Epileds Technologies Inc. reassignment Epileds Technologies Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TSENG, WEI-YU, WANG, TZU-WEN
Publication of US20180006189A1 publication Critical patent/US20180006189A1/en
Abandoned legal-status Critical Current

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    • H01L33/14—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/816—Bodies having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures
    • H01L33/0062—
    • H01L33/0079—
    • H01L33/06—
    • H01L33/30—
    • H01L33/40—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material
    • H01L2933/0016—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/032—Manufacture or treatment of electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP

Definitions

  • the present invention relates to a semiconductor epitaxial structure, a processing intermediate structure, and the method of manufacturing the is same. Specifically, it relates to an epitaxial structure having a tunnel junction layer, an intermediate structure having its p-type semiconductor layer facing upward, and the method of manufacturing the same.
  • a die of a light-emitting diode includes an n-type semiconductor layer and a p-type semiconductor layer.
  • multiple flipping steps are applied in the conventional epitaxial process.
  • FIG. 1 shows a conventional manufacturing process flow for a die with the p-type semiconductor layer facing upward.
  • an n-type semiconductor layer 101 , a multiple quantum well (MQW) layer 102 , and a p-type semiconductor layer 103 are sequentially deposited on a gallium arsenide substrate 100 .
  • a temporary substrate 104 is bonded onto the p-type semiconductor layer 103 to form the first stack structure 10 .
  • the first stack structure 10 is then flipped to remove the uppermost substrate 100 so as to expose the n-type semiconductor layer 101 .
  • a permanent substrate 105 is bonded onto the exposed uppermost n-type semiconductor layer 101 to form the second stack structure 15 .
  • the second stack structure 15 is flipped again to remove the temporary substrate 104 so as to expose the p-type semiconductor layer 103 and finally form the final structure of the die with its uppermost p-type semiconductor layer facing upward.
  • the intermediate structure of the upward-facing p-type semiconductor layer as produced by the aforementioned manufacturing process flow requires a bonding temperature higher than 500° C., which is a higher bonding temperature than the bonding temperature required for the n-type semiconductor layer, which is not favorable for a subsequent process.
  • the purpose of the present invention is to offer a processing intermediate structure, which provides for a better condition for the subsequent process of forming an interface between the semiconductor and metal, and also to provide for a simplified semiconductor manufacturing process flow.
  • the present invention provides an epitaxial structure having a tunnel junction layer and includes a first substrate, a first n-type semiconductor layer disposed on the first substrate, the tunnel junction layer disposed on the first n-type semiconductor layer, a p-type semiconductor layer disposed on the tunnel junction layer, and a second n-type semiconductor layer disposed on the p-type semiconductor layer, wherein the first n-type semiconductor layer, the tunnel junction layer, and the p-type semiconductor layer jointly form a p-type semiconductor structure.
  • the epitaxial structure further includes a multiple quantum well layer, which may be disposed between the p-type semiconductor structure and the second n-type semiconductor layer.
  • the first n-type semiconductor layer, the p-type semiconductor layer, and the second n-type semiconductor layer may include gallium arsenide, aluminum gallium arsenide, gallium nitride, or gallium phosphide.
  • the tunnel junction layer may include both a heavily doped n-type layer and a heavily doped p-type layer, and the heavily doped n-type and p-type layers may include AlGaInAs:Te/C or AlGaAs:Te/C.
  • the present invention provides a method of manufacturing a p-side up processing intermediate structure, which includes the following steps: providing a first substrate; forming a first n-type semiconductor layer on the first substrate; forming a p-type semiconductor layer on the first n-type semiconductor layer; forming a tunnel junction layer between the first n-type semiconductor layer and the p-type semiconductor layer so that the first n-type semiconductor layer, the p-type semiconductor layer, and the tunnel junction layer jointly form a p-type semiconductor structure; forming a second n-type semiconductor layer on the p-type semiconductor structure; bonding a second substrate onto the second n-type semiconductor layer to form a stack structure; then turning the stack structure upside down and removing the first substrate.
  • the method may further include a step of forming a multiple quantum well layer between the p-type semiconductor structure and the second n-type semiconductor layer.
  • the method may further include a step of forming a metal layer between the first substrate and the first n-type semiconductor layer so as to form an ohmic contact.
  • the method may further include forming another metal layer between the second n-type semiconductor layer and the second substrate so as to form an ohmic contact.
  • the first n-type semiconductor layer, the p-type semiconductor layer, and the second n-type semiconductor layer may include gallium arsenide, aluminum gallium arsenide, gallium nitride, or gallium phosphide.
  • the tunnel junction layer may include both a heavily doped n-type layer and a heavily doped p-type layer, and the heavily doped n-type and p-type layers may include AlGaInAs:Te/C or AlGaAs:Te/C.
  • a p-side up processing intermediate structure from bottom to top sequentially includes a second substrate, a second n-type semiconductor layer disposed on the second substrate, and a p-type semiconductor structure disposed on the second n-type semiconductor layer.
  • the p-type semiconductor structure includes a p-type semiconductor layer disposed on the second n-type semiconductor layer, a first n-type semiconductor layer disposed on the p-type semiconductor layer, and a tunnel junction layer disposed between the p-type semiconductor layer and the first n-type semiconductor layer.
  • a multiple quantum well layer may be disposed between the second n-type semiconductor layer and the p-type semiconductor structure.
  • the first n-type semiconductor layer, the p-type semiconductor layer, and the second n-type semiconductor layer may include gallium arsenide, aluminum gallium arsenide, gallium nitride, or gallium phosphide.
  • a metal layer may be disposed between the second substrate and the second n-type semiconductor layer.
  • another metal layer may be disposed on the first n-type semiconductor layer.
  • the tunnel junction layer may include both a heavily doped n-type layer and a heavily doped p-type layer, and the heavily doped n-type and p-type layers may include AlGaInAs:Te/C or AlGaAs:Te/C.
  • the present invention provides the epitaxial structure having the tunnel junction layer, the p-side up processing intermediate structure, and the method of manufacturing the same, wherein the tunnel junction layer disposed between the p-type semiconductor layer and the n-type semiconductor layer provides one or more of following advantages:
  • the combination of the p-type semiconductor layer, the tunnel junction layer and the n-type semiconductor layer shows the properties of a p-type semiconductor, that is overall the trilayer combination is p-type relative to the other n-type semiconductor layer, and therefore the three layers together form the p-type semiconductor structure.
  • the processing intermediate structure of the present invention includes two n-type semiconductor layers, onto which ohmic contacts can be subsequently formed, thereby avoiding the processing difficulty of forming an ohmic contact on a p-type semiconductor layer.
  • FIG. 1 is a process diagram showing a conventional manufacturing process flow for a die with the p-type semiconductor layer facing upward.
  • FIG. 2 is a flowchart showing a manufacturing process of the processing intermediate structure with the p-type semiconductor structure facing upward, that is the p-side up processing intermediate structure, according to an embodiment of the present invention.
  • FIGS. 3 and 4 are schematic diagrams showing the processing intermediate structure in stages before and after flipping respectively of the manufacturing process of the p-side up processing intermediate structure according to the first embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing a p-side up processing intermediate structure according to the second embodiment of the present invention.
  • the following one or more embodiments of the present invention disclose an epitaxial structure having a tunnel junction layer, a p-side up processing intermediate structure, and a method of manufacturing the processing intermediate structure.
  • an epitaxial structure having a p-type semiconductor structure As disclosed in the following embodiments of an epitaxial structure having a p-type semiconductor structure, the p-side up processing intermediate structure, and the method of manufacturing the same, only a low processing temperature is required to form an ohmic contact for the processing intermediate structure, which is advantageous for the subsequent process.
  • the following embodiments disclose the epitaxial structure having the tunnel junction layer, and that the use thereof can simplify the manufacturing process flow of the p-side up processing intermediate structure, and therefore also reduce the processing time and cost.
  • the manufacturing method includes: a step S 1 of providing the first substrate; a step S 2 of forming the first n-type semiconductor layer on the first substrate; a step S 3 of forming the tunnel junction layer on the first n-type semiconductor layer; a step S 4 of forming the p-type semiconductor layer on the tunnel junction layer and, as a result, the first n-type semiconductor layer, the p-type semiconductor layer, and the tunnel junction layer jointly form the p-type semiconductor structure; a step S 5 of forming the second n-type semiconductor layer on the p-type semiconductor structure; a step S 6 of bonding the second substrate on the second n-type semiconductor layer to form the stack structure; and a step S 7 of flipping the stack structure upside down and removing the first substrate.
  • the present invention provides a first embodiment of the manufacturing method of the processing intermediate structure, which is further illustrated with FIGS. 3 and 4 , which show the processing intermediate structure in stages before and after flipping respectively of the manufacturing process of the p-side up processing intermediate structure according to the first embodiment of the present invention.
  • the first substrate 3 may be gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium nitride (GaN), or gallium phosphide (GaP), but the present invention is not limited to these.
  • the first substrate is formed of gallium arsenide (GaAs).
  • the first n-type semiconductor layer 301 is formed on the first substrate 3 .
  • the first n-type semiconductor layer 301 is n-type gallium arsenide, and preferably doped with silicon (Si) or Tellurium (Te).
  • the tunnel junction layer 302 is disposed on the first n-type semiconductor layer 301 and the p-type semiconductor layer 303 is sequentially formed on the tunnel junction layer 302 .
  • the tunnel junction layer 302 which is an AlGaInAs or AlGaAs layer doped with Te or carbon (C), includes a heavily doped n-type layer and a heavily doped p-type layer.
  • the p-type semiconductor layer 303 is p-type doped gallium arsenide, and preferably the dopant is zinc (Zn).
  • the multiple quantum well layer 304 is disposed on the p-type semiconductor layer 303 .
  • the final step to form the epitaxial structure 320 is to dispose the second n-type semiconductor layer 305 on the multiple quantum well layer 304 .
  • the material of the second n-type semiconductor layer may be the same as or different from the material of the first n-type semiconductor layer.
  • the second n-type semiconductor layer 305 and the first n-type semiconductor layer 301 are the same and are gallium arsenide doped with silicon.
  • the second substrate 306 is then bonded onto the second n-type semiconductor layer 305 to complete the formation of the stack structure 35 , wherein the second substrate 306 may be a silicon substrate, a sapphire substrate, an aluminum nitride substrate, or a glass substrate. In this embodiment, the second substrate is a silicon substrate.
  • the stack structure 35 is then flipped upside down. As a result, the top second substrate 306 of the stack structure 35 becomes the bottom layer, and the bottom first substrate 3 of the stack structure 35 becomes the top layer. The first substrate 3 is then removed from the flipped stack structure 35 to complete the process of forming the processing intermediate structure 40 .
  • the energy band difference between a p-type and an n-type semiconductor causes an energy barrier that blocks electrons from flowing from the p-type semiconductor to n-type semiconductor.
  • the addition of the tunnel junction layer between the p-type semiconductor layer and first n-type semiconductor layer lowers the energy barrier at the interface therebetween, so that in forward bias across the processing intermediate structure (which corresponds to a reverse bias locally across the tunnel junction) the different electron and hole energy states on each side of the junction increasingly align, allowing the electrons in the valence band of the p-type semiconductor layer to tunnel to unoccupied sites in the conduction band of the first n-type semiconductor layer.
  • the processing intermediate structure 40 in the embodiment of the present invention includes the first n-type semiconductor layer 301 , the tunnel junction layer 302 , and the p-type semiconductor layer 303 .
  • the component layers of the trilayer structure have the same or extremely similar valence bands; and so the trilayer structure as a whole shows the properties of a p-type semiconductor relative to the second n-type semiconductor layer. Therefore, the trilayer of the first n-type semiconductor layer 301 , the tunnel junction layer 302 , and the p-type semiconductor layer 303 forms a p-type semiconductor structure 310 .
  • the disposition of the tunnel junction layer not only solves the problem of increasing voltage but also forms a p-type semiconductor structure 310 by combining the first n-type semiconductor layer 301 and the p-type semiconductor layer 303 , and results in the p-type semiconductor structure 310 of the processing intermediate structure 40 being disposed facing upward.
  • the inclusion of the tunnel junction layer therefore implies that the method of the manufacturing process of the p-side up processing intermediate structure of the present invention is able to provide the processing intermediate structure 40 with its p-type semiconductor structure 210 facing upward with the use of only one flipping step, and thereby simplifies the conventional multi-flip procedure of manufacturing a p-side up semiconductor structure, that in the present invention corresponds to the processing intermediate structure
  • the growth method of the epitaxial structure of the embodiments in the present invention may be by liquid phase epitaxy (LPE), vapor phase epitaxy (VPE) or metal organic chemical vapor deposition (MOCVD).
  • LPE liquid phase epitaxy
  • VPE vapor phase epitaxy
  • MOCVD metal organic chemical vapor deposition
  • the present invention provides a second embodiment of the p-side up processing intermediate structure, as shown in FIG. 5 .
  • the processing intermediate structure 50 includes the silicon substrate 506 formed in a way such as that of the second substrate in the first embodiment, the second n-type semiconductor layer 505 , the multiple quantum well layer 504 , the p-type semiconductor layer 503 , the tunnel junction layer 502 , and the first n-type semiconductor layer 501 .
  • the material of each component of the processing intermediate structure 50 is the same as the material of each component of the processing intermediate structure 40 .
  • the p-type semiconductor structure 510 is formed by combining the first n-type semiconductor layer 501 , the tunnel junction layer 502 and the p-type semiconductor layer 503 , wherein the characteristics of the tunneling effect are the same as those aforementioned in the first embodiment. It is thus not necessary to repeat what is written therein.
  • An ohmic contact may be formed between the semiconductor and the metal to introduce electric current into the semiconductor when operating the device in forward bias. As shown in FIG. 5 , for the second embodiment this is done by forming multiple metal layers 521 and 522 on the first n-type semiconductor layer 501 and the second n-type semiconductor layer 505 with ohmic contacts between the n-type semiconductor layers and the metals. This facilitates subsequent connection to first and the second electrodes.
  • metal layers are disposed between the second substrate and the second n-type semiconductor layer and on the first n-type semiconductor layer.
  • the material of the metal layers may be silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), Nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), ytterbium (Yb), germanium gold (GeAu), gold beryllium (BeAu), titanium (Ti), indium tin oxide (ITO), or calcium (Ca).
  • the metal layers are formed of germanium gold (GeAu), but the present invention is not limited thereof.
  • forming an ohmic contact on a p-type semiconductor layer requires an annealing process after forming the metal layer on the p-type semiconductor layer.
  • metal materials such as beryllium, gold, or indium tin oxide (ITO)
  • ITO indium tin oxide
  • an annealing temperature of 500° C. or higher is required to form an ohmic contact on a p-type semiconductor.
  • the metal Indium which is used in this embodiment, is not able to withstand such high temperatures, thus making it difficult to form an ohmic contact on the p-type semiconductor layer.
  • forming an ohmic contact on the p-type semiconductor layer is usually desirable for subsequent use of the processing intermediate structure in specific applications.
  • the processing intermediate structure has the p-type semiconductor structure that includes the second n-type semiconductor layer as the exposed top layer; and so an ohmic contact may be formed on the n-type semiconductor layer with an annealing temperature in the range of 300° C. to 330° C. Therefore, the present invention avoids the difficulty of forming an ohmic contact on a p-type semiconductor layer while still providing the p-type semiconductor structure facing upward.
  • the trilayer combination forms a structure with the properties of a p-type semiconductor.
  • the upward-facing disposition of the p-type semiconductor structure may be produced with only one flipping step in the manufacturing process, and thereby simplifying the process of manufacturing the processing intermediate structure.
  • Ohmic contacts may be formed in the processing intermediate structure of the present invention by forming metal layers on two n-type semiconductor layers, thereby avoiding the difficulty of forming an ohmic contact on a p-type semiconductor layer.
  • the manufacturing method of the present invention provides the processing intermediate structure with p-side up and includes easily forming the ohmic contacts with metal layers, and thereby simplifies the manufacturing process and reduces the manufacturing costs.

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US15/432,069 2016-06-29 2017-02-14 Epitaxial structure with tunnel junction, p-side up processing intermediate structure and method of manufacturing the same Abandoned US20180006189A1 (en)

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TW105120545A TWI617048B (zh) 2016-06-29 2016-06-29 具有穿隧接合層的磊晶結構、p型半導體結構朝上的製程中間結構及其製造方法

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220029049A1 (en) * 2018-02-07 2022-01-27 The Regents Of The University Of California Metal organic chemical vapor depostion (mocvd) tunnel junction growth in iii-nitride devices
WO2024237161A1 (ja) * 2023-05-12 2024-11-21 住友電気工業株式会社 半導体積層体および光半導体素子

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111540817A (zh) * 2020-05-19 2020-08-14 錼创显示科技股份有限公司 微型发光二极管芯片
TWI750664B (zh) 2020-05-19 2021-12-21 錼創顯示科技股份有限公司 微型發光二極體晶片

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070034853A1 (en) * 2005-08-15 2007-02-15 Robbins Virginia M Structures for reducing operating voltage in a semiconductor device
US20070290203A1 (en) * 2005-12-27 2007-12-20 Kabushiki Kaisha Toshiba Semiconductor element and method of manufacturing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847057B1 (en) * 2003-08-01 2005-01-25 Lumileds Lighting U.S., Llc Semiconductor light emitting devices
WO2007074969A1 (en) * 2005-12-27 2007-07-05 Samsung Electronics Co., Ltd. Group-iii nitride-based light emitting device
JP4172505B2 (ja) * 2006-06-29 2008-10-29 住友電気工業株式会社 面発光型半導体素子及び面発光型半導体素子の製造方法
EP2253988A1 (en) * 2008-09-19 2010-11-24 Christie Digital Systems USA, Inc. A light integrator for more than one lamp

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070034853A1 (en) * 2005-08-15 2007-02-15 Robbins Virginia M Structures for reducing operating voltage in a semiconductor device
US20070290203A1 (en) * 2005-12-27 2007-12-20 Kabushiki Kaisha Toshiba Semiconductor element and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220029049A1 (en) * 2018-02-07 2022-01-27 The Regents Of The University Of California Metal organic chemical vapor depostion (mocvd) tunnel junction growth in iii-nitride devices
US12471410B2 (en) * 2018-02-07 2025-11-11 The Regents Of The University Of California Metal organic chemical vapor depostion (MOCVD) tunnel junction growth in III-nitride devices
WO2024237161A1 (ja) * 2023-05-12 2024-11-21 住友電気工業株式会社 半導体積層体および光半導体素子
JPWO2024237161A1 (zh) * 2023-05-12 2024-11-21

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