US20170309813A1

US20170309813A1 - Integrated circuits with magnetic tunnel junctions and methods for producing the same

Info

Publication number: US20170309813A1
Application number: US15/443,741
Authority: US
Inventors: Vinayak Bharat Naik; Kazutaka Yamane; Kangho Lee
Original assignee: GlobalFoundries Singapore Pte Ltd
Current assignee: GlobalFoundries Singapore Pte Ltd
Priority date: 2016-04-26
Filing date: 2017-02-27
Publication date: 2017-10-26
Also published as: US20170345999A1; US10032980B2

Abstract

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a fixed layer that is magnetic and a tunnel barrier layer overlying the fixed layer, where the tunnel barrier layer is non-magnetic. A total free layer overlies the tunnel barrier layer, where the total free layer includes a plurality of individual free layers, wherein each of the plurality of individual free layers includes one or more of cobalt, iron, or boron, and where each of the plurality of individual free layers is magnetic. At least one of the plurality of individual free layers includes an atomic ratio of cobalt to iron that is from about 0.9/1 to about 1.1/1.

Description

TECHNICAL FIELD

The technical field generally relates to integrated circuits with magnetic tunnel junctions (MTJs) and methods of producing the same, and more particularly relates to integrated circuits with MTJs that are stable at elevated temperatures and methods of producing the same.

BACKGROUND

Magnetoresistive Random Access Memory (MRAM) is an emerging technology that may be competitive with prior integrated circuit memory technologies, such as floating gate technology. The MRAM technology may integrate silicon-based electronic components with magnetic tunnel junction technology. A significant element in MRAM is the magnetic tunnel junction where information may be stored. The magnetic tunnel junction stack (MTJ stack) has at least two magnetic layers separated by a non-magnetic barrier, where a fixed layer has a set magnetic property and a free layer has a programmable magnetic property for storing information. If the fixed layer and the free layer have parallel magnetic poles, the resistance through the MTJ stack is measurably less than if the fixed layer and the free layer have anti-parallel poles, so parallel magnetic poles may be read as a “0” and anti-parallel poles may be read as a “1.”
In some embodiments, the free layer may be pre-programmed before an integrated circuit is incorporated into a device. Incorporation of the integrated circuit into a device often involves a packaging reflow process that solders components at about 260 degrees Celsius (° C.). The stability of the permanent magnetic pole in the free magnetic layer degrades as the temperature increases, and the free layer may become demagnetized if the temperature exceeds the Curie temperature for the magnetic material in the free magnetic layer. A demagnetized free layer no longer retains the stored information. An energy barrier (Eb) of the free layer should be sufficiently high at the packaging reflow process temperature to maintain magnetism so the stored information is not lost. For example, an energy barrier of about 40 k_bT (k_bis the boltzman constant times temperature, where k_bis in joules per degree Kelvin, and T is temperature in degrees Kelvin, so k_bT is expressed in joules) or greater at the packaging reflow process temperature is generally sufficient to retain magnetism in the free layer so stored information is not lost. However, MTJ stack designs that increase the overall energy barrier also increases the footprint of the MTJ stack, the power consumption, and decreases the endurance.
Accordingly, it is desirable to provide integrated circuits with magnetic tunnel junctions having an energy barrier that is less sensitive to temperature increases than traditional magnetic tunnel junctions. In addition, it is desirable to provide integrated circuits with magnetic tunnel junctions that are temperature stable but do not have a high energy barrier at low temperatures such that desirable footprints and operations are possible, and methods of producing the same. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.

BRIEF SUMMARY

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a fixed layer that is magnetic and a tunnel barrier layer overlying the fixed layer, where the tunnel barrier layer is non-magnetic. A total free layer overlies the tunnel barrier layer, where the total free layer includes a plurality of individual free layers, wherein each of the plurality of individual free layers includes one or more of cobalt, iron, or boron, and where each of the plurality of individual free layers is magnetic. At least one of the plurality of individual free layers includes an atomic ratio of cobalt to iron that is from about 0.9 to 1 to about 1.1 to 1.
An integrated circuit is provided in another embodiment. The integrated circuit includes a fixed layer that is magnetic and a tunnel barrier layer overlying the fixed layer, where the tunnel barrier layer is non-magnetic. A total free layer overlies the tunnel barrier layer, where the total free layer includes a plurality of individual free layers that are magnetic. At least one of the plurality of individual free layers includes a tempco element, where the tempco element is at least one of samarium, dysprosium, copper, molybdenum, tungsten, and zirconium.
A method of producing an integrated circuit is provided in yet another embodiment. The method includes forming a fixed layer that is magnetic and forming a tunnel barrier layer overlying the fixed layer, where the tunnel barrier layer is non-magnetic. A total free layer is formed overlying the tunnel barrier layer, where the total free layer includes a first free layer and a second free layer that are magnetic. A first spacer layer is between the first and second free layers, and the first spacer layer is non-magnetic. The first free layer has a first free layer temperature coefficient, the second free layer has a second free layer temperature coefficient that is different than the first free layer temperature coefficient, and the total free layer has a total free layer temperature coefficient that is between the first and second free layer temperature coefficients.

BRIEF DESCRIPTION OF THE DRAWINGS

The present embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:

FIGS. 1-3 illustrate, in cross sectional views, an integrated circuit and methods for fabricating the same in accordance with exemplary embodiments; and

FIGS. 4 and 5 illustrate hypothetical graphs depicting temperature vs. energy barriers for different embodiments of a total free layer.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and is not intended to limit the various embodiments or the application and uses thereof. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description. Embodiments of the present disclosure are generally directed to integrated circuits and methods for fabricating the same. The various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of integrated circuits are well-known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
An integrated circuit includes a magnetic junction stack with a total free layer, where the total free layer includes a magnetic first free layer and a magnetic second free layer separated by a non-magnetic first spacer layer. The total free layer has a total free layer energy barrier that changes with temperature, where the total free layer energy barrier typically decreases with increasing temperatures. The total free layer also has a total free layer temperature coefficient that is the slope of the total free layer energy barrier plotted against the temperature. Therefore, the temperature coefficient typically has a negative value. An increase in the total free layer temperature coefficient (i.e., a less negative temperature coefficient) allows for a relatively low energy barrier at ambient temperatures with a higher energy barrier at elevated temperatures, relative to standard designs. In other words, the energy barrier changes more slowly with temperature as the temperature coefficient increases from a negative value towards zero. Various techniques are described for increasing the total free layer temperature coefficient towards a more positive value from a negative value.
Referring to an exemplary embodiment illustrated in FIG. 1, an integrated circuit 10 includes a substrate 12 formed of a semiconductor material. As used herein, the term “semiconductor material” will be used to encompass semiconductor materials conventionally used in the semiconductor industry from which to make electrical devices. Semiconductor materials include monocrystalline silicon materials, such as the relatively pure or lightly impurity-doped monocrystalline silicon materials typically used in the semiconductor industry, as well as polycrystalline silicon materials, and silicon admixed with other elements such as germanium, carbon, and the like. In addition, “semiconductor material” encompasses other materials such as relatively pure and impurity-doped germanium, gallium arsenide, zinc oxide, glass, and the like. As referred to herein, a material that includes a recited element/compound includes the recited element/compound in an amount of at least 10 weight percent or more based on the total weight of the material unless otherwise indicated. In many embodiments, the substrate 12 primarily includes a monocrystalline semiconductor material. The substrate 12 may be a bulk silicon wafer (as illustrated) or may be a thin layer of silicon on an insulating layer (commonly known as silicon-on-insulator or SOI, not illustrated) that, in turn, is supported by a carrier wafer. The substrate 12 has a substrate surface, and the substrate surface may be used as a reference for various components described herein.
A gate insulator 14 overlies the substrate 12, and a gate 16 overlies the gate insulator 14. As used herein, the term “overlying” means “over” such that an intervening layer may lie between the gate insulator 14 and the substrate 12, or “on” such that the gate insulator 14 physically contacts the substrate 12. In an exemplary embodiment, the gate insulator 14 includes an electrically insulating material and the gate 16 includes an electrically conductive material. As used herein, an “electrically insulating material” is a material with a resistivity of about 1×10⁴ohm meters or more, an “electrically conductive material” is a material with a resistivity of about 1×10⁻⁴ohm meters or less, and an “electrically semiconductive material” is a material with a resistivity of from about more than 1×10⁻⁴ohm meters to less than about 1×10⁴ohm meters. For example, the gate insulator 14 may include silicon dioxide and the gate 16 may include polysilicon doped with conductivity determining impurities, but other materials may be used in alternate embodiments. Electrically insulating spacers 18 may overlie the substrate 12 adjacent to the gate insulator 14 and the gate 16, where spacers 18 are positioned on opposite sides of the gate insulator 14 and the gate 16. The spacers 18 may include silicon dioxide, silicon nitride, or other electrically insulating materials in various embodiments. A source 20 may be formed within the substrate 12 on one side of the gate 16, and a drain 22 may be formed within the substrate 12 on the opposite side of the gate 16. The source 20 and drain 22 include conductivity determining impurities (sometimes referred to as “dopants”) at a higher concentration than in the substrate 12. FIG. 1 illustrates a planar transistor 28, where the transistor 28 includes the gate insulator 14, the gate 16, the spacers 18, the source 20, the drain 22, and a channel 24 disposed within the substrate 12 between the source 20 and drain 22 and underlying the gate 16. However, finned field effect transistors or other types of transistors 28 may be used in alternate embodiments.
In the illustrated embodiment, a bottom electrode 30 is in electrical communication with the drain 22, and a top electrode 32 is in electrical communication with the source 20. A contact 26 may be used to electrically connect the source 20 and drain 22 with top and bottom electrodes 32, 30, respectively. The term “electrical communication,” as used herein, means electrical current is capable of flowing from one component to another, where the electrical current may or may not flow through an electrically conductive or semiconductive intervening component. The term “direct electrical contact,” as used herein, means direct physical contact between components that are electrically conductive or semiconductors, but not electrical insulators. A magnetic tunnel junction stack 34 (MTJ stack) is positioned between the bottom and top electrodes 30, 32, where the MTJ stack 34 is in electrical communication with the bottom and top electrodes 30, 32. In an exemplary embodiment, the bottom electrode 30 may serve as a word line, and the top electrode 32 may serve as a bit line, but other embodiments are also possible. The bottom and top electrodes 30, 32 may include several layers (not illustrated,) such as a seed layer, a core, and a cover, and may include tantalum, tantalum nitride, nickel, copper, aluminum, or other electrically conductive materials. The MTJ stack 34 and the bottom and top electrodes 30, 32 may also be connected to other electronic components instead of the transistor 28 as illustrated, or in addition to the transistor 28 in various embodiments.
The MTJ stack 34 is illustrated in greater detail in FIG. 2. The MTJ stack 34 includes several layers overlying each other, where the illustrated layers may include sub-layers in some embodiments and where additional layers may also be present. In an exemplary embodiment, a seed layer 36 overlies the bottom electrode 30, a second hard metal layer 38 overlies the seed layer 36, a fixed divider layer 40 overlies the second hard metal layer 38, a first hard metal layer 42 overlies the fixed divider layer 40, a transition layer 44 overlies the first hard metal layer 42, and a reference layer 46 overlies the transition layer 44. In the illustrated embodiment, a fixed layer 50 includes the second hard metal layer 38, the fixed divider layer 40, the first hard metal layer 42, the transition layer 44, and the reference layer 46. The first and second hard metal layers 42, 38 are magnetic, and the fixed divider layer 40 is non-magnetic. As used herein, a layer or material is “magnetic” if it is a ferromagnetic material, where the term “ferromagnetic” does not require the presence of iron. More particularly, a material if “magnetic” if it is a permanent magnet that retains its magnetic field after an induction magnetic field is removed, where the permanent magnet has a residual flux density of about 0.1 tesla or more. A layer or material is “non-magnetic” if it is a diamagnetic or a paramagnetic material, and more particularly does not form a permanent magnet or is only capable of forming a permanent magnet that has a residual flux density of less than about 0.1 tesla or less. A “permanent” magnet is a magnet that has residual flux density of about 0.1 tesla or more for at least about 1 week or more after being removed from an induction magnetic field. The transition layer 44 is nonmagnetic and the reference layer 46 is magnetic in an exemplary embodiment.
In an exemplary embodiment, the seed layer 36 includes two or more of nickel, chromium, ruthenium, and platinum, and may also include other materials; the first and second hard metal layers 42, 38 include cobalt platinum compounds, cobalt nickel compounds, cobalt iron compounds, manganese platinum compounds, or other materials; the fixed divider layer 40 primarily includes one or more of ruthenium, iridium, rhodium, chromium, or nickel; the transition layer 44 primarily includes one or more of tantalum, tungsten, or molybdenum; and the reference layer 46 primarily includes cobalt, iron, and boron. However, other materials may be used in alternate embodiments. In an exemplary embodiment, the seed layer 36, the first and second hard metal layers 42, 38, the fixed divider layer 40, the transition layer 44 and the reference layer 46 are formed by sputtering or by ion beam deposition using the materials of the various layers, but other deposition techniques may also be used. The first and second hard metal layers 42, 38 may have the same composition as each other or may have compositions that vary from each other in various embodiments.
A tunnel barrier layer 52 is formed overlying the fixed layer 50, where the tunnel barrier layer 52 includes magnesium oxide in an exemplary embodiment. The tunnel barrier layer 52 and the remaining layers in the MTJ stack 34 may be formed by sputtering, by ion beam deposition, or by other techniques in various embodiments. A total free layer 60 overlies the tunnel barrier layer 52, a capping layer 54 overlies the total free layer 60, and the top electrode 32 overlies the capping layer 54. An additional tunnel barrier layer (not illustrated) or other layers may also be included in the MTJ stack 34 in various embodiments. The capping layer 56 is a nonmagnetic layer that may include ruthenium, hafnium, molybdenum, tungsten, platinum, nickel, or other compounds. The capping layer 56 may be formed with a crystalline structure, as opposed to an amorphous structure, and this crystalline structure may help induce a crystalline structure in adjoining individual layers within the total free layer 60.
The total free layer 60 includes a plurality of individual free layers separated by spacer layers, as illustrated in an exemplary embodiment in FIG. 3 with continuing reference to FIG. 2. In the illustrated embodiment, the total free layer 60 includes a first free layer 62 that is a magnetic layer, and a first spacer layer 64 overlying the first free layer 62, where the first spacer layer 64 is nonmagnetic. A second free layer 66 overlies the first spacer layer 64, where the second free layer 66 is a magnetic layer. The total free layer 60 may include a total of two individual free layers in some embodiments, such as a first and second free layer 62, 66, but the total free layer 60 may include additional free layers in alternate embodiments. The embodiment illustrated in FIG. 3 includes a non-magnetic second spacer layer 68 overlying the second free layer 66, a magnetic third free layer 70 overlying the second spacer layer 68, a non-magnetic third spacer layer 72 overlying the third free layer 70, and a magnetic fourth free layer 74 overlying the third spacer layer 72. However, there may be a total of two, three, four, or more individual free layers in alternate embodiments, where an individual non-magnetic spacer layer is positioned between each of the plurality of individual free layers. All the individual free layers are magnetic, and all the individual spacer layers are nonmagnetic.
Typically, the individual free layers are formed by depositing a cobalt iron boron compound, and then annealing that compound. However, in some embodiments each of the individual free layers include one or more of cobalt, iron, or boron, as alloys or as multilayers (not illustrated) so an individual free layer may include 1, 2, or 3 elements selected from cobalt, iron, or boron. The temperature coefficient (described more fully below) of cobalt iron boron compounds tends to increase (move towards positive, or become less negative) as the atomic ratio of cobalt to iron approaches 1/1. However, other atomic ratios with more iron than cobalt may provide performance benefits, such as better retention of a permanent magnetic property. Therefore, one or more of the individual free layers may have an atomic ratio of cobalt to iron of from about 0.01/1 to about 0.5/1, or from about 0.01/1 to about 0.7/1, or from about 0.01/1 to about 0.8/1 in various embodiments, for performance reasons. However, one or more of the other individual free layers (i.e., one or more of the first, second, third, or fourth free layer 62, 66, 70, 74 or other individual free layers that may be present) may have an atomic ratio of cobalt to iron of from about 0.8/1 to about 1.2/1, or from about 0.9/1 to about 1.1/1, or from about 0.95/1 to about 1.05/1 in various embodiments, where the cobalt to iron ratio that is closer to 1/1 provides a higher temperature coefficient. At the same time, another of the first, second, third, and fourth free layers 62, 66, 70, 74 may have a cobalt to iron ratio of from about 0.01/1 to about 0.5/1, or from about 0.01/1 to about 0.7/1, or from about 0.01/1 to about 0.8/1. The formation energy and temperature coefficient of the total free layer 60 is a combination of the formation energies and temperature coefficients of the individual free layers. Therefore, the combination of one or more individual free layers with a low cobalt to iron ratio with another one or more individual free layers with a cobalt to iron ratio that is about 1/1 produces a total free layer 60 with beneficial properties from both cobalt to iron ratios.
An alternate technique for increasing the temperature coefficient (making the temperature coefficient less negative) includes the addition of a “tempco” element to one or more of the individual free layers, where “tempco” refers to an element that impacts the temperature coefficient. Any one or more of the individual free layers (first, second, third, fourth or other free layers 62, 66, 70, 74) may include one or more tempco elements, where the tempco elements are samarium, dysprosium, copper, molybdenum, tungsten, and zirconium. The inclusion of the tempco element may increase the temperature coefficient towards positive, and in some cases may achieve a positive temperature coefficient within a temperature range of from about ambient (20 to 30° C.) to about 260° C. Cobalt and iron may be present at low concentrations in an individual free layer with a positive temperature coefficient, such as at from about 0 to about 1 atomic percent for cobalt and iron combined, but cobalt and iron may be present at higher concentrations in other embodiments, such as from about 1 to about 90 atomic percent for cobalt and iron combined. The tempco element or elements may be present at from about 80 to about 100 atomic percent, or from about 60 to about 100 atomic percent, or from about 10 to about 100 atomic percent in various embodiments. In an exemplary embodiment, the tempco element is samarium (Sm), where the samarium is combined with a transition metal (TM) in the form of Sm₂TM₁₇. In this embodiment, the tempco element samarium may be present in the individual free layer at a concentration of from about 0.5 to about 10 atomic percent, or from about 1 to about 10 percent, or from about 1 to about 100 percent in various embodiments, where cobalt and iron may also be present in the same individual free layer.
One or more of the other individual free layers may not include the tempco element at an appreciable concentration, such as no more than about 0.1 atomic percent, and this other individual free layer (first, second, third, fourth, or other free layer 62, 66, 70, 74) may primarily include cobalt and iron, and possibly boron. Cobalt and iron may be present in these other individual free layers at a total of from about 80 to about 100 atomic percent (for cobalt and iron combined), or from about 60 to about 100 atomic percent, or from about 10 to about 100 atomic percent in various embodiments. Boron may also be present.
Another technique that may help increase the temperature coefficient (make the temperature coefficient less negative) is the use of a plurality of individual free layers in the total free layer 60. FIG. 3 illustrates four individual free layers (62, 66, 70, 74), but there may be more of fewer individual free layers in alternate embodiments. The combination of a plurality of individual free layers may also increase the temperature coefficient of the total free layer 60, even in embodiments where the compositions of the individual free layers are the same. The capping layer 54 may be formed with a crystalline structure that helps induce a crystalline structure in the adjoining individual free layer, such as the fourth free layer 74 as illustrated or other individual free layers in alternate embodiments. The temperature coefficient of an individual free layer tends to increase as the crystallinity of that individual free layer increases, so a higher crystallinity in the capping layer 54 that induces higher crystallinity in the adjoining individual free layer may further increases the combined, overall temperature coefficient of the total free layer 60.
The total free layer 60 is annealed after formation, such as at a temperature of from about 300 to about 400° C. Boron may migrate during the anneal process such that boron may or may not be present after the anneal. Once all the layers in the MTJ stack 34 are formed, the MTJ stack 34 may be annealed to fix the free layer magnetization direction, also referred to as the easy axis direction for anisotropic magnetic layers. In general, heating a magnetic material to its Curie temperature or greater eliminates the permanent magnetic field, so the magnetic material has to be re-magnetized when cooled below its Curie temperature to re-establish a permanent magnetic field. The first and second hard metal layers 42, 38 are generally formed from magnetic materials with a Curie temperature above the temperatures reached in a packaging reflow process, so the fixed layer 50 retains its induced magnetism. However, the individual free layers typically include cobalt iron boron materials, and the Curie temperature for many of these materials may be below a packaging reflow process temperature, so information stored in the total free layer 60 can be lost during the packaging reflow process.
Reference is made to FIG. 4, with continuing reference to FIGS. 2 and 3, where FIG. 4 is a representation of the energy barrier for an embodiment with two free layers; a first free layer 62 and a second free layer 66. A first free layer line 80 illustrates the relationship of the energy barrier of the first free layer 62 plotted against temperature, and the second free layer line 82 illustrates the relationship of the energy barrier of the second free layer 66 plotted against temperature. The relationship of the energy barrier for the total free layer 60 results from a combination of the first and second free layers 62, 66, and is illustrated as a dashed line referred to herein as the total free layer line 84. The temperature coefficient may change at different temperatures, so the first free layer line 80 or any other free layer line may not be constant, or may not be constant at all temperatures. In the embodiment illustrated in FIG. 4, the maximum packaging reflow process temperature is illustrated as 260° C., and the energy barrier at the Curie temperature is illustrated as 40 k_bT. The slope of the first free layer line 80 is the temperature coefficient of the first free layer 62, and is illustrated as a negative value because the first free layer line 80 has decreasing energy barrier values as the temperature increases. The slope of the second free layer line 82 is the temperature coefficient of the second free layer 66, and is illustrated as a negative value, but a higher value (less negative) than that for the first free layer 62 because the energy barrier values decrease more slowly than the first free layer line 80 as the temperature increases. The slope of the total free layer line 84 is between that of the first and second free layer lines 80, 82. As can be seen, the energy barrier for the total free layer 60 is greater than 40 k_bT at 260° C.
The temperature coefficient of the first and second free layers 62, 66 depends on the composition of those layers, as described above. The combination of the individual free layers with different compositions (i.e., cobalt to iron ratios, and/or inclusion of a tempco element) may produce a total free layer line 84 with a temperature coefficient that keeps the energy barrier equal to or greater than about 40 k_bT at the packaging reflow temperature, such as about 260° C. More than one individual free layer may be included to provide desired performance with an acceptable temperature coefficient for the total free layer 60. The higher temperature coefficient allows for a total free layer line 84 that has a relatively low energy barrier at ambient temperatures (about 20 to about 30° C.) combined with an energy barrier above the Curie temperature at the packaging reflow temperature. As such, the MTJ stack 34 for an individual memory cell may be formed with a relatively small footprint, low power consumption, and high endurance compared to a typical MTJ stack 34 with an energy barrier above the Curie temperature at the packaging reflow temperature.
Reference is made to FIG. 5, which is a different representation of the energy barrier for an embodiment with two free layers; a third free layer 70 and a fourth free layer 74, where different labels are used to clarify the distinction between FIGS. 4 and 5. A third free layer line 86 illustrates the relationship of the energy barrier of the third free layer 70 plotted against temperature, and a fourth free layer line 88 illustrates the relationship of the energy barrier of the fourth free layer 74 plotted against temperature. The resulting alternate total free layer line 90 is also illustrated. As can be seen in this hypothetical example, the fourth free layer line 88 has a positive slope, so the temperature coefficient of the fourth free layer 74 is positive. A positive temperature coefficient for an individual free layer may be possible by including the tempco element at sufficient concentrations in that individual free layer. As described above, the properties of the third and fourth free layers 70, 74 are combined in the alternate total free layer line 90 to provide performance with acceptable temperature coefficients.
The MTJ stack 34 may be patterned into a desired shape for use as a memory cell (not illustrated) using photolithography and a reactive ion etch techniques. The patterned MTJ stack 34 may then be further incorporated into an integrated circuit 10 in a wide variety of manners. The temperature coefficient of the total free layer 60 may be increased using one or more of the techniques described above. An increased temperature coefficient for the total free layer 60 can facilitate a lower energy barrier at ambient conditions, such as from about 20 to about 30° C., and a higher energy barrier at elevated temperatures, such as a packaging reflow temperature of about 260° C., as compared to a total free layer 60 with a lower (more negative) temperature coefficient.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the application in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing one or more embodiments, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope, as set forth in the appended claims.

Claims

1. An integrated circuit comprising:

a fixed layer that is magnetic;

a tunnel barrier layer overlying the fixed layer, wherein the tunnel barrier layer is non-magnetic;

a total free layer overlying the tunnel barrier layer, wherein the total free layer comprises a plurality of individual free layers, wherein each of the plurality of individual free layers includes one or more of cobalt, iron, or boron, wherein each of the plurality of individual free layers is magnetic, and wherein at least one of the plurality of individual free layers comprises an atomic ratio of cobalt to iron that is from about 0.9/1 to about 1.1/1.

2. The integrated circuit of claim 1 wherein the at least one of the plurality of individual free layers comprise the atomic ratio of cobalt to iron that is from about 0.01/1 to about 0.7/1

3. The integrated circuit of claim 1 wherein the plurality of individual free layers comprise a first free layer and a second free layer; and

wherein the total free layer comprises a first spacer layer that is non-magnetic, wherein the first spacer layer is between the first free layer and the second free layer.

4. The integrated circuit of claim 3 wherein the plurality of individual free layers comprise:

a third free layer overlying the second free; and

wherein the total free layer comprises a second spacer layer between the third free layer and the second free layer, wherein the second spacer layer is non-magnetic.

5. The integrated circuit of claim 4 wherein the plurality of individual free layers comprise:

a fourth free layer overlying the third free; and

wherein the total free layer comprises a third spacer layer between the fourth free layer and the third free layer, wherein the third spacer layer is non-magnetic.

6. The integrated circuit of claim 1 wherein the fixed layer comprises:

a first hard metal layer that is magnetic;

a second hard metal layer that is magnetic; and

a fixed divider layer between the first hard metal layer and the second hard metal layer wherein the fixed divider layer is non-magnetic.

7. The integrated circuit of claim 6 wherein the fixed divider layer comprises one or more of ruthenium, iridium, rhodium, chromium, or nickel.

8. The integrated circuit of claim 1 wherein at least one of the plurality of individual free layers comprises a tempco element, wherein the tempco element is at least one of samarium, dysprosium, copper, molybdenum, tungsten, and zirconium.

9. The integrated circuit of claim 8 wherein the tempco element is present in the at least one of the plurality of individual free layers at from about 10 to about 100 atomic percent.

10. The integrated circuit of claim 8 wherein at least one of the plurality of individual free layers has a temperature coefficient that is positive within a temperature range of from about 40 degrees Celsius to about 260 degrees Celsius.

11. The integrated circuit of claim 1 wherein the total free layer has a formation energy of about 40 k_bT or greater at a temperature of about 260 degrees Celsius.

12. An integrated circuit comprising:

a fixed layer that is magnetic;

a total free layer overlying the tunnel barrier layer, wherein the total free layer comprises a plurality of individual free layers wherein each of the plurality of individual free layers are magnetic, wherein at least one of the plurality of individual free layers comprise a tempco element, wherein the tempco element is at least one of samarium, dysprosium, copper, molybdenum, tungsten, and zirconium.

13. The integrated circuit of claim 12 wherein the tempco element is present in the at least one of the plurality of individual free layers at a concentration of from about 10 to about 100 atomic percent.

14. The integrated circuit of claim 12 wherein the at least one of the plurality of individual free layers that comprises the tempco element has a positive temperature coefficient within a temperature range of from about 40 degrees Celsius and about 260 degrees Celsius.

15. The integrated circuit of claim 12 wherein the plurality of individual free layers comprise:

a first free layer and a second free layer; and

wherein the total free layer comprises a first spacer layer between the first free layer and the second free layer, wherein the first spacer layer is non-magnetic.

16. The integrated circuit of claim 15 wherein the plurality of individual free layers comprises:

a third free layer overlying the second free layer; and

17. The integrated circuit of claim 12 wherein the total free layer has an energy barrier of about 40 k_bT or greater at a temperature of about 260 degrees Celsius.

18. The integrated circuit of claim 12 wherein at least one of the plurality of individual free layers has a cobalt to iron ratio of from about 0.9/1 to about 1.1/1.

19. The integrated circuit of claim 12 wherein the at least one of the plurality of individual free layers that comprises the tempco element comprise a combination of samarium and a transition metal (TM) in the form of Sm₂TM₁₇.

20. A method of forming an integrated circuit comprising:

forming a fixed layer that is magnetic;

forming a tunnel barrier layer overlying the fixed layer, wherein the tunnel barrier layer is non-magnetic; and

forming a total free layer overlying the tunnel barrier layer, wherein the total free layer comprises a first free layer that is magnetic, a second free layer that is magnetic, and a first spacer layer between the first free layer and the second free layer wherein the first spacer layer in non-magnetic, wherein the first free layer has a first free layer temperature coefficient, the second free layer has a second free layer temperature coefficient that is different than the first free layer temperature coefficient, and the total free layer has a total free layer temperature coefficient that is between the first free layer temperature coefficient and the second free layer temperature coefficient.