WO2019005156A1

WO2019005156A1 - Spin orbit torque (sot) memory devices with enhanced switching capability and their methods of fabrication

Info

Publication number: WO2019005156A1
Application number: PCT/US2017/040493
Authority: WO
Inventors: Kevin P. O'brien; Kaan OGUZ; Brian S. Doyle; Charles C. Kuo; Mark L. Doczy; Satyarth Suri; Sarah ATANASOV
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03
Anticipated expiration: 2019-12-30

Abstract

A spin orbit torque (SOT) memory device includes a spin orbit torque electrode disposed in a dielectric layer above a substrate and a magnetic tunnel junction (MTJ) device disposed on a portion of the spin orbit torque electrode. The spin orbit torque electrode has an uppermost is 10-20 times larger than the MTJ device. The MTJ device includes a free layer disposed on the spin orbit torque electrode, a tunnel barrier such as an MgO disposed on the free layer and a fixed layer disposed on the tunnel barrier.

Description

SPIN ORBIT TORQUE (SOT) MEMORY DEVICES WITH ENHANCED SWITCHING CAPABILITY AND

THEIR METHODS OF FABRICATION

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit fabrication and, in particular, related to spin orbit torque (SOT) memory devices with enhanced switching capability and methods to form the same.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely on innovative devices such as spin orbit torque (SOT) memory devices including a spin orbit torque electrode coupled with a compatible MTJ device to overcome the requirements imposed by scaling.

Non-volatile embedded memory with SOT memory devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of assembling a material layer stack to form functional SOT memory devices present formidable roadblocks to commercialization of this technology today.

Specifically, increasing thermal stability of and reducing retention loss in SOT memory devices are some important areas of process development.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 A illustrates a cross-sectional view of a spin orbit torque (SOT) memory device, in accordance with an embodiment of the present disclosure.

Figure IB illustrates a plan view of a magnetic tunnel junction (MTJ) device disposed on a spin orbit torque electrode, in accordance with an embodiment of the present disclosure.

Figure 1C illustrates a cross-sectional view depicting the direction of magnetization in a free magnetic layer relative to the direction of magnetization in a fixed magnetic layer, in accordance with an embodiment of the present disclosure.

Figure ID illustrates a cross-sectional view depicting the direction of magnetization in a free magnetic layer relative to the direction of magnetization in a fixed magnetic layer, in accordance with an embodiment of the present disclosure.

Figures IE illustrates a cross-sectional view of individual layers of a synthetic antiferromagnetic structure, in accordance with an embodiment of the present disclosure. Figure 2 illustrates a cross-sectional view of a SOT memory device, in accordance with an embodiment of the present disclosure.

Figure 3A illustrates a SOT memory device in a low resistance state.

Figure 3B illustrates a SOT memory device switched to a high resistance state after the application of a spin hall current, a spin torque transfer current and/or an external magnetic field.

Figure 3C illustrates a SOT memory device switched to a low resistance state after the application of a spin hall current, a spin torque transfer current and/or an external magnetic field.

Figures 4A- 4H illustrate cross-sectional views representing various operations in a method of fabricating an SOT memory device in accordance with embodiments of the present disclosure.

Figure 4A illustrates a cross-sectional view of the formation of a spin orbit torque layer on an insulator formed above a substrate, in an accordance with embodiments of the present disclosure.

Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of a lithographically patterned resist layer to subsequently pattern the spin orbit torque layer.

Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following patterning of the spin orbit torque layer to form a spin orbit torque electrode.

Figure 4D illustrate cross-sectional and plan views of the structure in Figure 4C following the deposition of a dielectric layer on the spin orbit torque electrode and planarization of the dielectric layer and an uppermost portion of the spin orbit torque electrode.

Figure 4E illustrates a cross-sectional view of the structure in Figure 4D following the formation of a storage layer including anti-ferromagnetically coupled free layers on the spin orbit torque electrode and on the dielectric layer.

Figure 4F illustrates a cross-sectional view of the structure in Figure 4E following the formation of a tunnel barrier layer, a fixed magnetic layer, a top electrode to form a material layer stack for magnetic tunnel junction device.

Figure 4G illustrates a cross-sectional view of the structure in Figure 4F following the process of etching the material layer stack to form a magnetic tunnel junction device on the spin orbit torque electrode.

Figure 4H illustrates a cross-sectional view of the structure in Figure 4G following the formation of a dielectric spacer adjacent to the magnetic tunnel junction device.

Figure 5 illustrates a cross-sectional view of a SOT memory device coupled to a first transistor, a second transistor and a bit line.

Figure 6 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 7 illustrates an integrated circuit (IC) structure that includes one or more embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

Spin orbit torque (SOT) memory devices with enhanced switching capability and methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

A SOT memory device includes a magnetic tunnel junction (MTI) device formed on a spin orbit torque electrode. The MTJ device functions as a memory device where the resistance of the MTJ device switches between a high resistance state and a low resistance state. The resistance state of an MTJ device is defined by the relative orientation of magnetization between a free magnetic layer and a fixed magnetic layer that are separated by a tunnel barrier. When the magnetization of the free magnetic layer and a fixed magnetic layer have orientations that are in the same direction, the MTJ device is said to be in a low resistance state. Conversely, when the magnetization of the free magnetic layer and a fixed magnetic layer have orientations that are in opposite directions, the MTJ device is said to be in a high resistance state.

In an embodiment, in an absence of a spin orbit torque electrode, resistance switching in an MTJ device is brought about by passing a critical amount of spin polarized current through the MTJ device so as to influence the orientation of the magnetization of the free magnetic layer to align with the magnetization of the fixed magnetic layer. The act of influencing the magnetization is brought about by a phenomenon known as spin torque transfer, where the torque from the spin polarized current is imparted to the magnetization of the free magnetic layer. By changing the direction of the current, the direction of magnetization in the free magnetic layer may be reversed relative to the direction of magnetization in the fixed magnetic layer. Since the free magnetic layer does not need a constant source of spin polarized current to maintain a magnetization direction, the resistance state of the MTJ device is retained even when there is no current flowing through the MTJ device. For this reason, the MTJ device belongs to a class of memory known as non-volatile memory.

As an MTJ device is scaled down in size, the amount of critical spin polarized current density required to switch the device increases. It then becomes advantageous to have an additional source of switching torque to avoid simply increasing the spin polarized current density. By implementing an MTJ device on a spin orbit torque electrode, the magnetization in the free magnetic layer gets an additional switching torque from a different source. The additional torque comes from a spin hall current, induced by passing an electrical current in a transverse direction, through the spin orbit torque electrode. The spin hall current arises from spin dependent scattering of electrons due to a phenomenon of spin orbit interaction. Electrons of one spin polarity are directed towards an upper portion of the spin orbit torque electrode and electrons with an opposite spin polarity are directed toward a bottom portion of the spin orbit torque electrode. Electrons of a particular spin polarity are directed toward the MTJ device and impart a spin orbit torque on the magnetization of the free magnetic layer. In addition to providing switching assistance in the form of a spin orbit torque, the spin hall current can also help the MTJ device to switch faster. It is to be appreciated that, in an embodiment, the spin hall current can fully switch a free magnetic layer having a magnetization that is oriented in an in- plane direction, even in the absence of a spin polarized current passing through the MTJ device. An in-plane direction is defined as a direction that is parallel to an uppermost surface of the spin orbit torque electrode.

Integrating a non-volatile memory device such as a SOT memory device onto access transistors enables the formation of embedded memory for system on chip applications.

However, approaches to integrate a SOT memory device onto access transistors presents challenges that have become far more formidable with scaling. One such challenge is the need to improve switching speed of the SOT memory device. Ferromagnets such as those used as free magnetic and fixed magnetic layers in the SOT memory device can have multiple magnetic domains depending on the size of the ferromagnets. A ferromagnet having a dimension lager than approximately 30nm a has multiple magnetic domains. A ferromagnet having a dimension smaller than approximately 30nm is typically a single domain magnet. When there are multiple domains, each magnetic domain has a magnetization that points in a different direction from a magnetization of a neighboring domain. However, during the fabrication process, application of a sufficiently strong external magnetic field helps to align the magnetization of the individual magnetic domains along a particular direction.

It is to be appreciated that even if the magnetization of each of the different magnetic domains are all aligned in a single direction, the magnetization of the entire free magnetic layer does not simultaneously undergo a change in direction during an MTJ device switching process. More specifically, the switching process involves switching of individual magnetic domains of the free magnetic layer. Moreover, even when an MTJ device has a single domain, the magnetization of the entire free magnetic layer does not simultaneously undergo a change in direction. Rather, the magnetization over a certain portion of the free magnetic layer changes direction first and the switching propagates throughout the remaining portion of the free magnetic layer over a short time period ultimately resulting in reversal of direction of magnetization of the entire free magnet.

The switching speed of the SOT memory device, thus, depends on the switching speed of magnetic domains in the free magnetic layer for a multinomial magnet and on the switching speed of the individual magnetic moments for a single domain magnet. The switching speed of the magnetic domains depends on a parameter known as domain wall speed. Typical domain wall speeds range from 50-100m/s in ferromagnetically coupled free layers but can be as high as 700m/s in anti-ferromagnetically coupled free layers. Magnetic domains can range from 30nm to lOOnm along a broadest dimension of a free magnetic layer and can be irregularly shaped. While reducing the MTJ device size can lessen undesirable effects of multi-domain switching in a free magnetic layer, a further increase in the switching speed can be brought about by replacing a single free magnetic layer with an anti-ferromagnetically coupled free layer having two ferromagnet separated by a non-magnetic material.

As MTJ devices (formed on spin orbit torque electrode) are scaled, the need for smaller memory elements to fit into a scaled cell size has driven the industry in the direction of perpendicular MTJs. Perpendicular MTJs are memory devices where the fixed magnetic layer and the free magnetic layer have magnetic anisotropy that is perpendicular with respect to a plane defining an uppermost surface of the spin orbit torque electrode. Furthermore, perpendicular MTJs can be scaled to dimensions of less than 30nm where the number of individual magnetic domains can be reduced to a single domain. By implementing a perpendicular MTJ with an anti-ferromagnetically coupled free magnetic layer on a spin orbit torque electrode several advantages can be gained such as single domain switching, higher switching speeds and additional switching torque assistance from a spin hall current. In accordance with embodiments of the present disclosure, a spin orbit torque (SOT) memory device includes a spin orbit torque electrode disposed in a dielectric layer above a substrate and a magnetic tunnel junction (MTJ) device disposed on a portion of the spin orbit torque electrode. In an embodiment, the spin orbit torque electrode has uppermost surface area that is 10-20 times larger than a lowermost surface area of the MTJ device. In an embodiment, the MTJ device includes a storage layer (a composite free layer that collectively undergoes magnetization switching) disposed on the spin orbit torque electrode, a tunnel barrier such as an MgO disposed on the storage layer and a fixed magnetic layer disposed on the tunnel barrier. In an embodiment, the storage layer includes a first ferromagnet disposed on the spin orbit torque electrode, an antiferromagnetic coupling layer disposed on the first ferromagnet, and a second ferromagnet disposed on the antiferromagnetic coupling layer. The first ferromagnet and the second ferromagnet are anti-ferromagnetically coupled and undergo magnetization switching together.

Antiferromagnetic coupling between the first ferromagnet and the second ferromagnet takes place through a phenomenon known as interlayer exchange coupling through the antiferromagnetic coupling layer. Antiferromagnetic coupling is dependent on the choice of material and on the thickness of the antiferromagnetic coupling layer. Materials for use as an antiferromagnetic coupling layer include metals such as ruthenium and molybdenum. While such an anti-ferromagnetically coupled storage layer can enable higher switching speeds, it is to be appreciated that the material composition of each of the first ferromagnet and second ferromagnet is also important for spin orbit torque memory devices.

Firstly, when the first ferromagnet is directly disposed on the spin orbit torque electrode, it is desirable for the first ferromagnet to be a strong spin orbit torque coupling material in order to receive the benefit of the torque from the flux of electrons generated from the spin hall current in the spin orbit torque electrode. Secondly, the second ferromagnet adj acent to the tunnel barrier should be as closely lattice matched with the tunnel barrier above to optimize spin polarization current. Closely matching the lattice structure of the free magnet with a lattice structure of tunnel barrier enables a higher tunneling magnetoresistance (TMR) ratio in the MTJ device. The TMR ratio of an MTJ device (in percent) is given by Equation (1), provided below.

(RH - RL)

TMR =—2-—— . 100%

^RL

RH refers to the value of electrical resistance measured when a MTJ device is in a high resistance state and RL refers to the value of electrical resistance measured when the MTJ device is in a low resistance state When the tunnel barrier is highly lattice matched to the second ferromagnet (as well as to the fixed magnetic layer), the low resistance state of the MTJ device becomes small, yielding a higher TMR ratio.

A further embodiment of the storage layer includes a first ferromagnet and second ferromagnet that are doped with one or more metallic and non-metallic elements to reduce a parameter known as saturation magnetization, Ms, of the storage layer. Reduction in saturation magnetization can help make an MTJ device more stable.

Figure 1A is an illustration of a cross-sectional view of a SOT memory device 100 in accordance with an embodiment of the present disclosure. The SOT memory device 100 includes a spin orbit torque electrode 101 disposed in a dielectric layer 102 and a magnetic tunnel junction (MTJ) device 104, such as a perpendicular MTJ (pMTJ) device, disposed on the spin orbit torque electrode 101. In an embodiment, an SOT memory device 100 that includes a pMTJ device, is herein referred to as a perpendicular SOT memory device or a pSOT memory device. In an embodiment, the MTJ device 104 is disposed approximately in the center of the spin orbit torque electrode 101 as shown in the plan view illustration of Figure IB.

Referring again to Figure 1A, the MTJ device 104 includes a storage layer 106. The storage layer 106 includes a first ferromagnet 108 disposed on the spin orbit torque electrode

101, an antiferromagnetic coupling layer 110 disposed on the first ferromagnet 108 and a second ferromagnet 112 disposed on the antiferromagnetic coupling layer 110. The combination of the first ferromagnet 108, antiferromagnetic coupling layer 110 and the second ferromagnet 1 12 improves the switching speed of the storage layer 106 through an exchange coupling torque that is proportional to the strength of the antiferromagnetic exchange coupling between the first ferromagnet 108 and the second ferromagnet 1 12. The MTJ device 104 further includes a tunnel barrier 114 such as an MgO or AI2O3, disposed on the second ferromagnet 112 and a fixed magnetic layer 1 16 disposed on the tunnel barrier 114.

The spin orbit torque electrode 101 includes a metal with high degree of spin orbit coupling. A metal with a high degree of spin-orbit coupling has an ability to inject a large spin polarized current in to the storage layer 106. A large spin polarized current can exert a large amount of torque and influence the magnetization of the storage layer 106 to switch faster. In an embodiment, the spin orbit torque electrode 101 includes a metals such as but not limited to tantalum, tungsten, platinum or gadolinium. In an embodiment, the spin orbit torque electrode 101 includes a metal or metals such as but not limited to tantalum, tungsten, platinum or gadolinium. In an embodiment, spin orbit torque electrode 101 includes a beta phase tantalum or beta phase tungsten. A spin orbit torque electrode 101 including a beta phase tantalum or beta phase tungsten has a high spin hall efficiency. A high spin hall efficiency denotes that the spin orbit torque electrode 101 can generate a large spin hall current for a given charge current that is passed through the spin orbit torque electrode 101. In an embodiment, the spin orbit torque electrode 101 includes a multilayer stack including one or more layers of metals such as but not limited to tantalum, tungsten, platinum or gadolinium. In an embodiment, when the spin orbit torque electrode 101 includes a multilayer stack, the layer with the highest degree of spin-orbit coupling is disposed directly adjacent to the MTJ device. In an embodiment, the spin orbit torque electrode 101 has thickness of between 5nm-10nm.

In an embodiment, the first ferromagnet 108 includes a magnetic material such as Co, Ni, Fe or alloys of these materials. In an embodiment, the first ferromagnet 108 includes a magnetic material such as FeB, CoFe and CoFeB. In an embodiment, the first ferromagnet 108 includes a Coioo-x-_yFe_xBy, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the first ferromagnet 108 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy.

In an embodiment, the first ferromagnet 108 includes a material having a high spin orbit torque coupling to couple with the spin orbit torque (from the injected spin hall current). In one embodiment, the first ferromagnet 108 includes a layer of Co.

In an embodiment, the first ferromagnet 108 is doped with one or elements selected from the group consisting of molybdenum, tungsten, tantalum, silicon or zirconium. In an

embodiment, the total concentration of dopants is between 10-20 atomic percent of the total composition of the first ferromagnet 108. Doping the first ferromagnet 108 with the one or elements selected from the group consisting of molybdenum, tungsten, tantalum, silicon or zirconium can cause a reduction in a magnetism parameter, called the saturation magnetization, M_s, of the first ferromagnet 108. A reduction in the saturation magnetization, M_s, can enable increase in the stability of the storage layer 106.

In an embodiment, the first ferromagnet 108 has a thickness between 0.5nm-1.4nm for perpendicular MTJ devices. In an embodiment, the first ferromagnet 108 has a thickness between 1.5nm-3.0nm for in-plane MTJ devices.

Referring again to Figure 1 A, in an embodiment, the antiferromagnetic coupling layer 110 includes a non-magnetic material such as ruthenium. In an embodiment, the

antiferromagnetic coupling layer 1 10 includes a non-magnetic material such as but not limited to molybdenum, iridium, tungsten, or alloys of manganese for example Pt-Mn, Ir-Mn etc. In an embodiment, antiferromagnetic coupling layer 110 is molybdenum. In an embodiment, the antiferromagnetic coupling layer 1 10 has a thickness between 0.3-1.2nm. In an embodiment, the antiferromagnetic coupling layer 1 10 is molybdenum and has a thickness between 0.5nm-l ,2nm. When the antiferromagnetic coupling layer 1 10 is molybdenum and has a thickness between 0.5- 1.2nm the first ferromagnet 108 and the second ferromagnet 112 can be coupled anti- ferromagnetically. In an embodiment, the antiferromagnetic coupling layer 110 is ruthenium and has a thickness of between 0.3nm-0.5nm. When an antiferromagnetic coupling layer 1 10 is ruthenium and has a thickness between 0.3nm-0.5nm the first ferromagnet 108 and the second ferromagnet 112 can be coupled anti-ferromagnetically.

In an embodiment, the second ferromagnet 112 includes a magnetic material such as Co, Ni, Fe or alloys of these materials. In an embodiment, the second ferromagnet 112 includes a magnetic material such as FeB, CoFe and CoFeB. In an embodiment, the second ferromagnet 112 includes a Coioo-x-yFe_xB_y, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the second ferromagnet 112 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy.

In an embodiment, the second ferromagnet 112 includes a layer of CoFeB, the antiferromagnetic coupling layer 1 10 includes a layer of molybdenum and the tunnel barrier 1 14 includes a layer of MgO. The presence of molybdenum helps the second ferromagnet 1 12 to be textured in a desired orientation matching the crystal orientation of the tunnel barrier 114.

Lattice matching the crystal structure of the second ferromagnet 1 12 with the tunnel barrier 114 enables a higher tunneling magnetoresi stance (TMR) ratio in the MTJ device 100. In an embodiment, a second ferromagnet 112 including a Coioo-x-_yFe_xB_yi where X and Y each represent atomic percent, is highly lattice matched to a tunnel barrier 1 14 including an MgO.

In an embodiment, the second ferromagnet 112 is doped with one or elements selected from the group consisting of molybdenum, tungsten, tantalum, silicon or zirconium. In an embodiment, the total concentration of dopants is less than or equal to 10 atomic percent of the total composition of the second ferromagnet 112. Doping the second ferromagnet 1 12 with one or elements selected from the group consisting of molybdenum, tungsten, tantalum, silicon or zirconium can cause reduction in a magnetism parameter, called the saturation magnetization, M_s, of the second ferromagnet 112. A reduction in the saturation magnetization, Ms, of the second ferromagnet 1 12 can enable increase in the stability of the storage layer 106.

In an embodiment, the second ferromagnet 112 has a thickness between 0.9nm-2.0nm for perpendicular MTJ devices. In an embodiment, the second ferromagnet 1 12 has a thickness between 2. lnm-3.0nm for in-plane MTJ devices.

In an embodiment, the first ferromagnet 108 and the second ferromagnet 112 are a same material such as CoFeB. In other embodiments, the first ferromagnet 108 and the second ferromagnet 112 each include a different material. In a specific embodiment, the first ferromagnet 108 includes CoFe and the second ferromagnet 1 12 includes CoFeB.

In an embodiment, the first ferromagnet 108 is doped with one or elements selected from the group consisting of molybdenum, tungsten, tantalum, silicon or zirconium and the second ferromagnet 112 is doped with a one or elements selected from the group consisting of molybdenum, tungsten, tantalum, silicon or zirconium.

In an embodiment, the second ferromagnet 112 has a total concentration of dopants that is equal to a concentration of dopants in the first ferromagnet 108. In an embodiment, the second ferromagnet 112 has a total concentration of dopants that is more than a concentration of dopants in the first ferromagnet 108. In an embodiment, the second ferromagnet 112 has a total concentration of dopants that is less than a concentration of dopants in the first ferromagnet 108. In an embodiment, when the first ferromagnet 108 and the second ferromagnet 1 12 include a same material and a same dopant species, the saturation magnetization, Ms, of each ferromagnet can be different depending on the relative concentration of the dopant material. In an embodiment, the first ferromagnet 108 has a saturation magnetization, Msi, that is higher than a saturation magnetization, Ms2, of the second ferromagnet 112. In an embodiment, the first ferromagnet 108 has a saturation magnetization, Msi, that is lower than the saturation magnetization, Ms2, of the second ferromagnet 1 12. In an embodiment, the first ferromagnet 108 has a saturation magnetization, Msi, that is comparable to the saturation magnetization, Ms2, of the second ferromagnet 1 12.

In a different embodiment, a switching ferromagnet that is directly below the tunnel barrier includes a stack of at least two ferromagnetic materials as illustrated in Figure 2. In an embodiment, a second ferromagnet 212 having a bilayer stack is disposed above the

antiferromagnetic coupling layer 1 10. In an embodiment, the second ferromagnet 212 includes a lowermost ferromagnetic layer 212A in contact with the antiferromagnetic coupling layer 110 and an uppermost ferromagnetic layer 212B adjacent to the tunnel barrier 1 14. In an

embodiment, the uppermost ferromagnetic layer 212B is a material that has a (001) crystal structure which is lattice matched to the tunnel barrier 1 14.

In an embodiment, the uppermost ferromagnetic layer 212B includes a magnetic material such as Co, Ni, Fe or alloys of these materials. In an embodiment, the uppermost ferromagnetic layer 212B includes a magnetic material such as FeB, CoFe and CoFeB. In an embodiment, the uppermost ferromagnetic layer 212B includes a Coioo-x-yFe_xB_y, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20.

In an embodiment, the lowermost ferromagnetic layer 212A includes a magnetic material such as Co, CoFe, FeB or Fe. In an embodiment, the lowermost ferromagnetic layer 212A is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In an embodiment, the lowermost ferromagnetic layer 212A is doped with one or elements selected from the group consisting of molybdenum, tungsten, tantalum, silicon or zirconium. In an embodiment, the total concentration of dopants is less than or equal to 10 atomic percent of the total composition of the lowermost ferromagnetic layer 212A.

In an embodiment, the second ferromagnet 212 includes a bilayer stack of a layer of CoFeB disposed on a layer of Co. In an embodiment, the second ferromagnet 212 includes a bilayer stack of a layer of CoFeB disposed on a layer Fe.

In an embodiment, the uppermost ferromagnetic layer 212B has a thickness that is between 0.2nm-1.0nm and lowermost ferromagnetic layer 212A has a thickness that is between 0.2nm-0.4nm. In an embodiment, the second ferromagnet 212 has a thickness that between 0.4nm-1.4nm.

Referring again to Figure 1 A, in an embodiment, the tunnel barrier 114 is composed of a material suitable for allowing electron current having a majority spin to pass through the tunnel barrier 114, while impeding at least to some extent electron current having a minority spin from passing through the tunnel barrier 114. Thus, the tunnel barrier 114 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In one embodiment, the tunnel barrier 114 includes a material such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI2O3). In an embodiment, the tunnel barrier 114 including MgO has a crystal orientation that is (001) and is lattice matched to the second ferromagnet 112 as well as to the fixed magnet 116. In one embodiment, the tunnel barrier 1 14 is MgO and has a thickness of approximately lnm to 2 nm.

Referring again to Figure 1 A, in an embodiment, the fixed magnet 1 16 includes a material and has a thickness sufficient for maintaining a fixed magnetization. In an embodiment, the fixed magnet 1 16 of the MTJ device 104 includes an alloy such as CoFe and CoFeB. In an embodiment, the fixed magnet 116 comprises a Coioo-x-_yFe_xB_y, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnet 116 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy.

In an embodiment the fixed magnet 1 16 has a thickness that is between lnm- 3nm. In an embodiment, the fixed magnet 116 has a thin uppermost portion that is insufficient to maintain magnetization and is said to be magnetically dead. In an embodiment, the magnetically dead uppermost portion of the fixed magnet 116 has a thickness between 0.2nm-0.5nm. In one such embodiment, in spite of having a magnetically dead uppermost portion, the fixed magnet 1 16 has a remaining magnetic portion having a thickness that is sufficient for maintaining a fixed magnetization.

Referring again to Figure 1 A, the MTJ device 104 further includes a top electrode 120 disposed on the fixed magnet 116. In an embodiment, the top electrode 120 includes a material such as Ta or TiN. In an embodiment, the top electrode 120 has a thickness between 20-70nm.

In an embodiment, the substrate 122 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 122 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound. Logic devices such as MOSFET transistors and access transistors and may be formed on the substrate 122. Logic devices such as access transistors may be integrated with memory devices such as SOT memory devices to form embedded memory. Embedded memory including SOT memory devices and logic MOSFET transistors can be combined to form functional integrated circuit such as a system on chip.

Figure IB illustrates a plan view of the MTJ memory device 104 disposed on the spin orbit torque electrode, in accordance with an embodiment of the present disclosure. In an embodiment, the spin orbit torque electrode 101 has a rectangular plan view profile and the MTJ memory device 104 has a circular plan view profile as illustrated in Figure IB. In another embodiment, an MTJ memory device 104, such as an in-plane MTJ, has a plan view profile that is elliptical. In another embodiment, the MTJ memory device 104 has a plan view profile that is rectangular. In an embodiment, the spin orbit torque electrode 101 has a length, LSOT, between 100nm-500nm. In an embodiment, the spin orbit torque electrode 101 has a thickness between 2nm-10nm. In an embodiment, the spin orbit torque electrode 101 has a width, WSOT, between 10nm-50nm. In an embodiment, the MTJ memory device 104 has a broadest cross sectional width, WMTJ, that is similar or substantially similar to the width, WSOT. In an embodiment, the MTJ memory device 104 has a broadest cross sectional width, WMTJ, that is between lOnm- 50nm.

In an embodiment, the MTJ memory device 104 has a center, CMTJ and the spin orbit torque electrode 101 has a center, CSOT. In an embodiment, CMTJ is aligned CSOT in both x and y directions, as illustrated in Figure IB. In another embodiment, CMTJ is misaligned from the CSOT in the y-direction. The electrical resistivity of the spin orbit torque electrode 101 may play a role in positioning of the MTJ memory device 104 on the spin orbit torque electrode 101 along the y- direction in Figure IB.

Figure 1C illustrates a cross-sectional view depicting the storage layer 106 of the MTJ device 104 having a direction of magnetization (denoted by the direction of the arrow 154) that is anti -parallel to a direction of magnetization (denoted by the direction of the arrow 156) in the fixed magnet 1 16. When the direction of magnetization 154 in the storage layer 106 is opposite (anti-parallel) to the direction of magnetization 156 in the fixed magnet 116, the MTJ device 104 device is said to be in a high resistance state.

Conversely, Figure ID illustrates a cross-sectional view depicting the storage layer 106 of the MTJ device 104 having a direction of magnetization (denoted by the direction of the arrow 154) that is parallel to a direction of magnetization (denoted by the direction of the arrow 156) in the fixed magnet 1 16. When the direction of magnetization 154 in the storage layer 106 is parallel to the direction of magnetization 156 in the fixed magnet 1 16, the MTJ device 104 device is said to be in a low resistance state.

In an embodiment, the storage layer 106 and the fixed magnet 116 can have

approximately similar thicknesses and an injected spin polarized current which changes the direction of the magnetization 154 in the storage layer 106 can also affect the magnetization 156 of the fixed magnet 116. In an embodiment, to make the fixed magnet 116 more resistant to accidental flipping the fixed magnet 1 16 has a higher magnetic anisotropy than the storage layer 106. In another embodiment, a synthetic antiferromagnetic (SAF) structure can be disposed between the top electrode 120 and the fixed magnet 116 in order to prevent accidental flipping of the magnetization 156 in the fixed magnet 116.

Figure IE illustrates cross-sectional view of the synthetic antiferromagnetic (SAF) layer 118 in an accordance of an embodiment of the present invention. In an embodiment, the SAF layer 1 18 includes a non-magnetic layer 1 18B sandwiched between a first pinning ferromagnet 118A and a second pinning ferromagnetic layer 118C as depicted in Figure ID. The first pinning ferromagnet 118A and the second pinning ferromagnetic layer 118C are anti- ferromagnetically coupled to each other. In an embodiment, the first pinning ferromagnet 1 18A includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co Pd or a Co/Pt. In an embodiment, the non-magnetic layer 118B includes a ruthenium or an iridium layer. In an embodiment, the second pinning ferromagnetic layer 1 18C includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co Pd or a Co/Pt. In an embodiment, a ruthenium based non-magnetic layer 118B has a thickness between 4-9 Angstroms to ensure that the coupling between the first ferromagnet 118A and the second pinning ferromagnetic layer 118C is anti-ferromagnetic in nature.

It is to be appreciated that an additional layer of non-magnetic spacer material may be disposed on the fixed magnet 116, below the SAF layer 118. A non-magnetic spacer layer enables coupling between the SAF layer 118 and the fixed magnet 116. In an embodiment, a non-magnetic spacer layer may include a metal such as Ta, Ru or Ir.

Figures 3A-3C illustrate a mechanism for switching an MTJ device 104 formed on a spin orbit torque electrode 101.

Figure 3 A illustrates an MTJ device, such as an MTJ device 104 disposed on a spin orbit torque electrode 101, where a magnetization 154 of the storage layer 106 is in the same direction as a magnetization 156 of the fixed magnet 1 16. In an embodiment, the direction of

magnetization 154 of the storage layer 106 and the direction of magnetization 156 of the fixed magnet 116 are both in the negative z-direction as illustrated in Figure 3A. As discussed above, when the magnetization 154 of the storage layer 106 is in the same direction as a magnetization 156 of the fixed magnet 1 16, MTJ device 104 is in a low resistance state.

Figure 3B illustrates a spin orbit torque (SOT) memory device switched to a high resistance state. In an embodiment, a reversal in the direction of magnetization 154 of the storage layer 106 in Figure 3B compared to the direction of magnetization 154 of the storage layer 106 in Figure 3A is brought about by (a) inducing a spin diffusion current 168 in the spin orbit torque electrode 101 in the y-direction, (b) by applying an ISTTM current 170, and/or (c) by applying an external magnetic field, H_y, 170 in the y-direction.

In an embodiment, a charge current 160 is passed through the spin orbit torque electrode 101 in the negative y-direction. In response to the charge current 160, an electron current 162 flows in the positive y-direction. The electron current 162 includes electrons with two opposing spin orientations, a type I electron 166, having a spin oriented in the negative x-direction and a type II electron 164 having a spin oriented in the positive x-direction. In an embodiment, electrons constituting the electron current 162 experience a spin dependent scattering

phenomenon in the spin orbit torque electrode 101. The spin dependent scatterning

phenonmenon is brought about by a spin-orbit interaction between the nucleus of the atoms in the spin orbit torque electrode 101 and the electrons in the electron current 162. The spin dependent scattering phenomenon causes type 1 electrons 166, whose spins are oriented in the negative x-direction, to be deflected upwards towards an uppermost portion of the spin orbit torque electrode 101 and type 2 electrons 164 whose spins are oriented in the positive x-direction to be deflected downwards towards a lowermost portion of the spin orbit torque electrode 101. The separation between the type I electrons 166 and the type II electrons 164 induces a polarized spin diffusion current 168 in the spin orbit torque electrode 101. In an embodiment, the polarized spin diffusion current 168 is directed upwards toward the storage layer 106 of the MTJ device 104 as depicted in Figure 3B. The polarized spin diffusion current 168 induces a spin hall torque on the magnetization 154 of the storage layer 106. The ISTTM current 170 flowing through the MTJ device 104 exerts an additional torque on the magnetization 154 of the storage layer 106. The combination of spin hall torque and spin transfer torque causes flipping of

magnetization 154 in the storage layer 106 from the negative z-direction illustrated in Figure 3 A to a positive z-direction illustrated in Figure 3B. In an embodiment, an additional torque can be exerted on the storage layer by applying an external magnetic field, H_y, in the y-direction, as illustrated in Figure 3B, in addition to an ISTTM current 170. In an embodiment, an additional torque can be exerted on the storage layer by applying an external magnetic field, H_y, in the y- direction, as illustrated in Figure 3B, instead of applying an ISTTM current 170.

Figure 3C illustrates a spin orbit torque (SOT) memory device switched to a low resistance state. In an embodiment, a reversal in the direction of magnetization 154 of the storage layer 106 in Figure 3C compared to the direction of magnetization 154 of the storage layer 106 in Figure 3B is brought about by (a) reversing the direction of the spin diffusion current 168 in the spin orbit torque electrode 101, (b) by reversing the direction of the ISTTM current 170, and/or (c) by reversing the direction of the external magnetic field, H_y.

Figures 4A-4H illustrate cross-sectional views representing various operations in a method of fabricating spin orbit torque (SOT) memory device in accordance with embodiments of the present disclosure.

Figure 4A illustrates a cross-sectional view of the formation of a spin orbit torque electrode layer 401 on a dielectric layer 404 formed above a substrate 403 In an embodiment, the spin orbit torque electrode layer 401 is a material that is substantially similar to the spin orbit torque electrode 101. In an embodiment, the spin orbit torque electrode layer 401 includes a metal such as Pt, beta-tungsten and beta-tantalum. In an embodiment, the spin orbit torque electrode layer 401 is deposited using a physical vapor deposition process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the spin orbit torque electrode layer 401 has a thickness that is between 20nm-30nm.

In an embodiment, the spin orbit torque electrode layer 401 includes a multilayer stack of metals consisting of two or more layers of metals that can induce spin diffusion currents. In an embodiment, an uppermost layer of metal has a higher spin hall effect angle than a spin hall effect angle of a lowermost layer of metal. In one such embodiment, the multilayer stack of metals includes a layer of platinum deposited on the dielectric layer 404, a layer of beta-tungsten deposited on the layer of platinum and a layer of beta-tantalum deposited on the layer of beta- tungsten. In an embodiment, the combined total thickness of the multilayer stack of metals is between 4nm-10nm.

In an embodiment, the dielectric layer 404 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the substrate 403 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrates 403 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound.

Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of a photoresist mask 406 on the spin orbit torque electrode layer 401. In an embodiment, the photoresist mask 406 is formed by a lithographic process that is well known in the art. The photoresist mask 406 defines a size of a spin orbit torque electrode that will subsequently be formed. In an embodiment, the photoresist mask 406 has a rectangular shape as is depicted in the plan view illustration of Figure IB. In another embodiment, the photoresist mask 406 has a square shape.

Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following the patterning of the spin orbit torque electrode layer 401 to form a spin orbit torque electrode 402. In an embodiment, the spin orbit torque electrode layer 401 is patterned by a plasma etch process selectively to the photoresist mask 406. Upon completion of the etch process, any remaining photoresist mask is subsequently removed.

Figure 4D illustrates a cross-sectional view of the structure in Figure 4C following the deposition of a second dielectric layer 408 and a planarization process. In an embodiment, the second dielectric layer 408 is deposited on the spin orbit torque electrode 402 and on the dielectric layer 404. A planarization process is carried out to remove the second dielectric layer 408 above the spin orbit torque electrode 402 and an upper portion of the spin orbit torque electrode 402. In an embodiment, the spin orbit torque electrode 402 and the second dielectric layer 408 surrounding the spin orbit torque electrode 402 have uppermost surfaces that are substantially co-planar following the planarization process. In an embodiment, the planarization process is a chemical mechanical polish process. In an embodiment the planarization process forms a spin orbit torque electrode 402 having a topographically smooth uppermost surface with a surface roughness that is less than lnm. In an embodiment, the spin orbit torque electrode 402 has a resultant thickness between 5m-10nm after the planarization process.

The plan view Figure 4D (Α-Α'), illustrates the size and shape of the spin orbit torque electrode 402. The spin orbit torque electrode 402 has a length LSOT and a width WSOT. In an embodiment, the spin orbit torque electrode 402 has a length, LSOT, that is between 50nm to 500nm. In an embodiment, the spin orbit torque electrode 402 has a width, WSOT, between 20nm to 40nm.

Figure 4E illustrates a cross-sectional view of the structure in 4D following the formation of a storage layer 410 on the spin orbit torque electrode 402 and on the second dielectric layer 408. In an embodiment, formation of the storage layer 410 includes deposition of a first ferromagnetic layer 411, deposition of an antiferromagnetic coupling layer 413 on the first ferromagnetic layer 41 1 and deposition of a second ferromagnetic layer 415 on the

antiferromagnetic coupling layer 413, in accordance with an embodiment of the present disclosure.

In an embodiment, while the deposition process is carried without an air break, the individual layers are blanket deposited using a variety of deposition processes in a cluster tool. In an embodiment, some layers are deposited using a physical vapor deposition (PVD) process. In an embodiment, a co-sputter or a reactive sputtering process is utilized to deposit one or more layers of the storage layer 410.

In an embodiment, first ferromagnetic layer 41 1 is deposited by a physical vapor deposition (PVD) process. In an embodiment, the first ferromagnetic layer 411 includes Co, Ni or Fe. In an embodiment, the first ferromagnetic layer 411 includes depositing an alloy such as CoFe, FeB or a CoFeB. In an embodiment, the first ferromagnetic layer 41 1 is deposited to a thickness between 0.5-1 ,4nm. In an exemplary embodiment, the first ferromagnetic layer 41 1 includes a layer of Co deposited to a thickness of 1 Onm. In an embodiment, the thickness of the first ferromagnetic layer 411 is chosen to reduce attenuation of spin polarized current intensity reaching the second ferromagnetic layer 415.

In another embodiment, the deposition process for forming the first ferromagnetic layer 411, includes in-situ doping with one or more elements such as but not limited to molybdenum, tungsten, tantalum, silicon or zirconium. In an embodiment, the in-situ doping process includes a co-sputter depositing the one or more doping elements with the metal or alloy of the first ferromagnetic layer 41 1. The in-situ deposition process can lead to uniform distribution of the one or more doping elements throughout the thickness of the first ferromagnetic layer 41 1. In an embodiment, the total concentration of the one or more doping elements is between 10-20 atomic percent of the total composition of the first ferromagnetic layer 41 1.

The antiferromagnetic coupling layer 413 is deposited on the first ferromagnetic layer 411 to enable antiferromagnetic coupling between the first ferromagnetic layer 41 1 and a subsequent second ferromagnetic layer that will be formed. In an embodiment, the

antiferromagnetic coupling layer 413 is deposited using a PVD process. In an embodiment, the antiferromagnetic coupling layer 413 includes a non-magnetic material such as but not limited to molybdenum, iridium, tungsten, or alloys of manganese for example Pt-Mn, Ir-Mn etc. As discussed above, for a given choice of material, deposited, the thickness of the antiferromagnetic coupling layer 413 determines whether the first ferromagnetic layer 41 1 and a subsequent second ferromagnetic layer 415 can be coupled anti-ferromagnetically. In an embodiment, when the antiferromagnetic coupling layer 413 is a layer of molybdenum and is deposited to a thickness between 0.5-1.2nm the first ferromagnetic layer 41 1 and the second ferromagnetic layer 415 can be coupled anti-ferromagnetically.

However, in another embodiment, when the antiferromagnetic coupling layer 413 is a layer of ruthenium and is deposited to a thickness between 0.3nm-0.5nm the first ferromagnetic layer 411 and the second ferromagnetic layer 415 can be anti-ferromagnetically coupled.

Referring again to Figure 4E, a second ferromagnetic layer 415 is deposited on the conductive coupling layer 414. In an embodiment, the second ferromagnetic layer 415 is deposited using a PVD process. In an embodiment, the second ferromagnetic layer 415 includes a material similar to the material of the second ferromagnet 112. In an embodiment, the second ferromagnetic layer 415 includes a CoFeB. In an embodiment, the deposition process forms a second ferromagnetic layer 415 including CoFeB that is amorphous. In an embodiment, the second ferromagnetic layer 415 is deposited to a thickness between 0.9nm-2.5nm. In an embodiment, the second ferromagnetic layer 415 is deposited to a thickness between 0.9nm- 2.0nm to fabricate a perpendicular MTJ stack.

In an embodiment, the deposition process for forming the second ferromagnetic layer 415, includes in-situ doping with one or more elements such as but not limited to molybdenum, tungsten, tantalum, silicon or zirconium. In an embodiment, the in-situ doping process includes co-sputter depositing the one or more doping elements and the metal or alloy of second ferromagnetic layer 415. The in-situ deposition process can lead to uniform distribution of the one or more doping elements throughout the thickness of the second ferromagnetic layer 415. In an embodiment, the total concentration of the one or more doping elements is between 10-20 atomic percent of the total composition of the second ferromagnetic layer 415.

In an embodiment, the total concentration of the one or more doping elements is less than or equal to 10 atomic percent of the total composition of the second ferromagnetic layer 415. In an embodiment, the first ferromagnetic layer 41 1 and the second ferromagnetic layer 415 are each doped to different concentrations. In an embodiment, the first ferromagnetic layer 41 1 and the second ferromagnetic layer 415 are each doped to a similar concentration. In an

embodiment, the first ferromagnetic layer 41 1 and the second ferromagnetic layer 415 each include a different material and are each doped to different concentrations. In an embodiment, the first ferromagnetic layer 411 and the second ferromagnetic layer 415 each include a same material but are each doped to different concentrations.

Figure 4F illustrates a cross-sectional view of the structure in Figure 4E following the formation of a tunnel barrier layer 417 on the storage layer 410, a fixed magnetic layer 419 on the tunnel barrier layer 417 and a top electrode layer 421 on the fixed magnetic layer 419. In an embodiment, a tunnel barrier layer 417 is blanket deposited on the second ferromagnetic layer 415. In an embodiment, the tunnel barrier layer 417 includes a material such as MgO or AI2O3. In an embodiment, the tunnel barrier layer 417 is an MgO and is deposited using a reactive sputter process. In an embodiment, the reactive sputter process is carried out at room temperature. In an embodiment, the tunnel barrier layer 417 is deposited to a thickness between 0.8nm to lnm. In an embodiment, the deposition process is carried out in a manner that yields a tunnel barrier layer 417 having an amorphous structure. In an embodiment, the amorphous tunnel barrier layer 417 becomes crystalline after a high temperature anneal process to be described further below. In an embodiment, the tunnel barrier layer 417 is crystalline as deposited.

In an embodiment, the fixed magnetic layer 419 is blanket deposited on the uppermost surface of the tunnel barrier layer 417. In an embodiment, the deposition process includes a physical vapor deposition (PVD) or a plasma enhanced chemical vapor deposition process. In an embodiment, the PVD deposition process includes an RF or a DC sputtering process.

In an embodiment, the fixed magnetic layer 419 is Coioo-x-yFe_xB_y, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In an embodiment, the fixed magnetic layer 419 is similar to the fixed magnetic layer 116 described above. In an embodiment, the fixed magnetic layer 419 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In an embodiment the fixed magnetic layer 419 is deposited to a thickness between 2.0nm-3.0nm.

In an embodiment, a top electrode layer 421 is blanket deposited on the surface of the fixed magnetic layer 419. In an embodiment, the top electrode layer 421 includes a material that is suitable to act as a hardmask during a subsequent etching of the MTJ material layer stack 450 to form an MTJ device. In an embodiment, the top electrode layer 421 includes a material such as TiN, Ta or TaN. In an embodiment, the thickness of the top electrode layer ranges from 30nm-70nm. The thickness of the top electrode layer 421 is chosen to accommodate patterning requirements of the various sizes of the MTJ devices that will subsequently be fabricated. In an embodiment, a SAF structure similar to the SAF structure 1 18 is deposited on the fixed magnetic layer 419 prior to depositing the top electrode layer 421.

In an embodiment, the process of depositing the top electrode layer 421 causes in a small uppermost fraction of the fixed magnetic layer 419 to become magnetically dead. In an embodiment, the fixed magnetic layer 419 has magnetically dead portion that is less than 5% of the total thickness of the fixed magnetic layer 419. In an embodiment, the fixed magnetic layer 419 has magnetically dead portion that is between 5%-20% of the total thickness of the fixed magnetic layer 419. In an embodiment, magnetically dead portion of the fixed magnetic layer 419 is not continuous throughout the structure of the fixed magnetic layer 419. By depositing the fixed magnetic layer 419 to a thickness of at least 2.5nm, the fixed magnetic layer 419 can function as a fixed magnet.

In an embodiment, after all the layers in the MTJ material layer stack 450 are deposited, an anneal is performed under conditions well known in the art. In an embodiment, the anneal process enables formation of a crystalline MgO - tunnel barrier layer 417 to be formed. In an embodiment, the anneal is performed immediately post deposition but before patterning of the MTJ material layer stack 450. A post-deposition anneal of the MTJ material layer stack 450 is carried out in a furnace at a temperature between 300-350 degrees Celsius in a forming gas environment. In an embodiment, the forming gas includes a mixture of ¾ and N₂ gas. In an embodiment, the annealing process promotes solid phase epitaxy of the second ferromagnetic layer 415 to follow a crystalline template of the tunnel barrier layer 417 (e.g., MgO) that is directly above the second ferromagnetic layer 415. In an embodiment, the anneal also promotes solid phase epitaxy of the fixed magnetic layer 419 to follow a crystalline template of the tunnel barrier layer 417 (e.g., MgO) that is directly below the fixed magnetic layer 419. Lattice matching between the tunnel barrier layer 417 and the second ferromagnetic layer 415 and lattice matching between the tunnel barrier layer 417 and the fixed magnetic layer 419 enables a higher TMR ratio to be obtained in the MTJ material layer stack 450.

In an embodiment, when the second ferromagnetic layer 415 includes boron, the annealing process enables boron to diffuse away from an interface 430 between the second ferromagnetic layer 415 and the tunnel barrier layer 417. The process of diffusing boron away from the interface 430 enables lattice matching between the second ferromagnetic layer 415 and the tunnel barrier layer 417. In an embodiment, when the fixed magnetic layer 419 includes boron, the annealing process enables boron to diffuse away from an interface 432 between the fixed magnetic layer 419 and the tunnel barrier layer 417.

In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets the magnetization direction of the fixed magnetic layer 419, the second ferromagnetic layer 415 and the first ferromagnetic layer 41 1. In an embodiment, an applied magnetic field that is directed parallel to a vertical axis of the MTJ material layer stack 450, during the annealing process, enables a perpendicular anisotropy to be set in the fixed magnetic layer 419, in the second ferromagnetic layer 415 and in the first ferromagnetic layer 41 1. In an embodiment, the annealing process initially aligns the magnetization of the fixed magnetic layer 419, magnetization of the second ferromagnetic layer 415 and the magnetization of the first ferromagnetic layer 41 1 to be parallel to each other. While one MTJ material layer stack 450 has been described in this embodiment, a material layer stack for forming the MTJ device 202 illustrated in Figure 2 can also be fabricated by the deposition techniques described above.

Figure 4G illustrates a cross-sectional view of the structure in Figure 4F following patterning and etching of the MTJ material layer stack 450. In an embodiment, the patterning process includes lithographically patterning a layer of resist formed (not shown) over the MTJ material layer stack 450. The lithography process defines the shape and size of a MTJ device and a location where the MTJ device is to be subsequently formed with respect the spin orbit torque electrode 402. In an embodiment, the patterning process includes etching the top electrode layer 421 by a plasma etch process to form a top electrode 422. In an embodiment, plasma etch process possesses sufficient ion energy and chemical reactivity to render vertical etched profiles of the top electrode layer 421. In an embodiment, the remaining layer of resist above the top electrode 422 is then removed by a plasma ash process.

In an embodiment, the plasma etch process is then continued to pattern the remaining layers of the MTJ material layer stack 450 to form a MTJ memory device 470. The MTJ memory device 470 has a fixed magnet 420, a tunnel barrier 418, a second ferromagnet 412, a patterned antiferromagnetic coupling layer 414 and a first ferromagnet 416. The plasma etch process also exposes the spin orbit torque electrode 402 and the underlying second dielectric layer 408.

Figure 4H illustrates a cross-sectional view of the structure in Figure 4G following the formation of a dielectric spacer adjacent to the magnetic tunnel junction device. In an embodiment, a dielectric spacer layer is deposited on the MTI memory device 470 and on the uppermost surface of the spin orbit torque electrode 402 and on the second dielectric layer 408. In an embodiment, the dielectric spacer layer is deposited without a vacuum break following the plasma etch process. In an embodiment, the dielectric spacer layer includes a material such as but not limited silicon nitride, carbon doped silicon nitride or silicon carbide. In an embodiment, the dielectric spacer layer includes an insulator layer that does not have any oxygen content to prevent oxidation of magnetic layers. In an embodiment, the dielectric spacer layer is etched by a plasma etch process forming dielectric spacer 426 on sidewalls of the MTJ memory device 470. In an embodiment, the etch process may cause an uppermost portion of the second dielectric layer 408 to become partially recessed leading to partial exposure of sidewalls of the spin orbit torque electrode 402.

The MTJ memory device 470 formed over the spin orbit torque electrode 402, constitutes a spin orbit torque memory device 480. In an embodiment, when an MTJ memory device 470 is a perpendicular MTJ memory device 470, then the spin orbit torque memory device 480 is a perpendicular spin orbit torque (pSOT) memory device 480.

Figure 5 illustrates a spin orbit torque (SOT) memory device, such as the spin orbit torque memory device 480 coupled with a first transistor 500 and a second transistor 520 and a bit line 542. hi an embodiment, the first transistor 500 and second transistor 520 are disposed on a substrate 501.

In an embodiment, the first transistor 500 and second transistor 520 associated with substrate 501 are metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 501. In various implementations of the present disclosure, the transistor 508 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri- gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. In an embodiment, the first transistor 500 and second transistor 520 are tri-gate transistors that are horizontally disposed on a same plane as illustrated in Figure 5. The first transistor 500 and second transistor 520 are electrically isolated by a dielectric layer 545 although they are formed on a common substrate 501.

In an embodiment, the first transistor 500 has a source region 502, a drain region 504 and a gate 506. The first transistor 500 further includes a gate contact 514 disposed above and electrically coupled to the gate 506, a source contact 516 disposed above and electrically coupled to the source region 502, and a drain contact 518 disposed above and electrically coupled to the drain region 504 as is illustrated in Figure 5. In an embodiment, the second transistor 520 has a source region 524, a drain region 522 and a gate 526. The second transistor 520 further includes a gate contact 534 disposed above and electrically coupled to the gate 526, a source contact 536 disposed above and electrically coupled to the source region 524, and a drain contact 538 disposed above and electrically coupled to the drain region 522 as is illustrated in Figure 5. In an embodiment, the source contact 516 of the first transistor 500 and the source contact of the second transistor 520 are electrically connected (as indicated by dashed line 582).

In an embodiment, the spin orbit torque memory device 480 includes an MTJ memory device such as an MTJ memory device 470, described in association with Figure 4H, disposed on a spin orbit torque electrode such as a spin orbit torque electrode 402, described in association with Figure 4D. In an embodiment, the spin orbit torque electrode 402 is disposed above a dielectric layer 550 and is surrounded by a second dielectric layer 555. A portion of the spin orbit torque electrode 402 is disposed on and in electrical contact with the drain contact 538 of the second transistor 520. An MTJ contact 528 is disposed on and electrically coupled with the MTJ memory device 470. A spin orbit torque contact 540 is disposed on and electrically coupled with the spin orbit torque electrode 402. In an embodiment, the spin orbit contact 540 is connected to a bit line (BL) 542 of a memory array. In an embodiment, the BL 542 is connected to a spin orbit torque contact of a second spin orbit torque memory device (not shown). In an embodiment, the MTJ contact 528 is electrically connected to a drain contact 518 of the first transistor 500 (indicated by the dashed line 580). In an embodiment, the MTJ contact 528, connected to the drain contact 518, of the first transistor 500, enables flow of an STTM device current through the MTJ memory device 470. In an embodiment, the source contact 516 of the first transistor and the source contact 536 of the second transistor 520 are electrically connected to a shared source line (SL) 582. In an embodiment, the gate contact 514 of the first transistor 500 is electrically connected to a first wordline (WLi) 541 and the gate contact 534 of the second transistor 520 is electrically connected to a second wordline (WL2) 543, where WLi 541 and WL₂ 543 are independently programmable.

In an embodiment, when the second transistor 520 is energized in a manner that causes charge current to flow through the spin orbit torque electrode 402, a spin hall current is generated in the spin orbit torque electrode 402. The spin hall current will exert a torque on the magnetization of a storage layer 410 of the MTJ memory device 470. By energizing the first transistor 500 a charge current can flow from the drain contact 518, into the MTJ memory device 470 through the MTJ contact 528. The charge current is a source of a polarized STTM current, isTTM, that will exert a torque on the magnetization of the storage layer 410. In an embodiment, the torque transfer from the spin hall current and from the spin torque transfer current will change the direction of magnetization in the storage layer 410. In an embodiment, by appropriately biasing the first transistor 500 and the second transistor 520, write and erase operations may be enabled in the MTJ memory device. A read operation of the MTJ memory device 470 may be enabled by applying a biasing voltage between 0.1 V-0.2V between the SL 582 and the BL 542 and by applying an appropriate voltage bias on WLi 541, to energize the first transistor 520.

Referring again to Figure 5, in an embodiment, the underlying substrate 501 represents a surface used to manufacture integrated circuits. In an embodiment, the substrate 501 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, the substrate 501 includes other semiconductor materials such as germanium, silicon germanium, or a suitable group III-V or group III-N compound. The substrate 501 may also include semiconductor materials, metals, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the first transistor 500 includes a gate stack formed of at least two layers, a gate dielectric layer 510 and a gate electrode layer 512. The gate dielectric layer 510 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 510 to improve its quality when a high-k material is used.

The gate electrode layer 512 of the first transistor 500 is formed on the gate dielectric layer 510 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer 512 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode layer 512 with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode layer 512 with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode layer 512 may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode layer 512 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the present disclosure, the gate electrode layer 512 may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode layer 512 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some implementations of the present disclosure, a pair of gate dielectric layer 510 may be formed on opposing sides of the gate stack that bracket the gate stack. The gate dielectric layer 510 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source region 502 and drain region 504 are formed within the substrate adjacent to the gate stack of the first transistor 500. The source region 502 and drain region 504 are generally formed using either an implantation/diffusion process or an

etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 502 and drain region 504. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 502 and drain region 504. In some implementations, the source region 502 and drain region 504 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in-situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 502 and drain region 504 may be formed using one or more alternate semiconductor materials such as germanium or a suitable group III-V compound. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 502 and drain region 504.

In an embodiment, the second transistor 520 also includes a gate stack formed of at least two layers, a gate dielectric layer 530 and a gate electrode layer 532. In an embodiment, the second transistor 520 is similar or substantially similar to the first transistor 500. In an embodiment, the gate dielectric layer 530 and the gate electrode layer 532 of the second transistor 520 are substantially similar to the gate dielectric layer 510 and the gate electrode layer 512 of the first transi stor 500.

In an embodiment, the gate contact 514, source contact 516 and drain contact 518 of the first transistor 500 are partially formed in the dielectric layer 550 and partially formed in the second dielectric layer 555. Similarly, the gate contact 534, source contact 536 and drain contact 538 of the second transistor 520 are partially formed in the dielectric layer 550 and partially formed in the second dielectric layer 555. Figure 6 illustrates a computing device 600 in accordance with one embodiment of the disclosure. The computing device 600 houses a motherboard 602. The motherboard 602 may include a number of components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the motherboard 602. In some implementations the at least one communication chip 606 is also physically and electrically coupled to the motherboard 602. In further implementations, the communication chip 606 is part of the processsor 604.

Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to the motherboard 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more memory devices, such as a spin orbit torque memory device 480, built with a MTJ material layer stack 450 in accordance with embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606. In accordance with another implementation of an embodiment of the disclosure, the integrated circuit die of the communication chip includes spin orbit torque memory device 480 integrated with access transistors, built in accordance with embodiments of the present disclosure.

In further implementations, another component housed within the computing device 600 may contain a stand-alone integrated circuit memory die that includes one or more memory elements, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.

Figure 7 illustrates an integrated circuit (IC) structure 700 that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure 700 is an intervening substrate used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer mother, or another integrated circuit die. Generally, the purpose of an integrated circuit (IC) structure 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates 702/704 are attached to opposing sides of the integrated circuit (IC) structure 700. In other embodiments, the first and second substrates 702/704 are attached to the same side of the integrated circuit (IC) structure 700. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 700.

The integrated circuit (IC) structure 700 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 710. The integrated circuit (IC) structure 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, spin orbit torque memory devices, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 700. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 700.

Accordingly, one or more embodiments of the present disclosure relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present disclosure relate to the fabrication of a spin orbit torque memory device such as the spin orbit torque memory device 480. The spin orbit torque memory device 480 may be used in an embedded non-volatile memory application.

Thus, embodiments of the present disclosure include spin orbit torque memory devices with enhanced stability and methods to form the same.

Specific embodiments are described herein with respect to perpendicular spin orbit torque devices. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, magnetic random access memory (MRAM) devices, spin torque transfer memory (STTM) devices such as in-plane STTM or perpendicular STTM devices.

Example 1 : A spin orbit torque (SOT) memory device includes a spin orbit torque electrode and a magnetic tunnel junction (MTJ) memory device disposed above a portion of the spin orbit torque electrode. The MTJ memory device includes a free layer, wherein the free layer includes, a first free magnet, a conductive layer on the first free magnet and a second free magnet on the conductive layer. The conductive layer anti-ferromagnetically couples the first free magnet and the second free magnet, a tunnel barrier on the free layer, a fixed magnet on the tunnel barrier, and a top electrode on the fixed magnet.

Example 2: The SOT memory device of example 1, wherein the spin orbit torque electrode includes a metal selected from the group consisting of tantalum, tungsten and platinum.

Example 3 : The SOT memory device of example 1, wherein the first free magnet and the second free magnet includes a magnetic material selected from the group consisting of Co, Fe, FeB and CoFeB.

Example 4: The SOT memory device of example 1 or 3, wherein the first free magnet is doped with one or elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the first free magnet.

Example 5: The SOT memory device of example 1 or 3, wherein the second free magnet is doped with one or elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the first free magnet.

Example 6: The SOT memory device of example 1, 3 or 4, wherein the first free magnet has a thickness between 0.5nm and 2.5nm.

Example 7: The SOT memory device of example 1, 3 or 5, wherein the second free magnet has a thickness between 0.9nm and 2.0 nm.

Example 8: The SOT memory device of example 1, wherein the conductive layer includes a metal selected from the group consisting of molybdenum and ruthenium.

Example 9: The SOT memory device of example 1, wherein the conductive layer has a thickness between 0.3nm and 1.2nm.

Example 10: The SOT memory device of example 1, wherein the conductive layer is ruthenium and has a thickness between 0.3nm-0.5nm.

Example 11 : The SOT memory device of example 1 further includes a synthetic antiferromagnetic (SAF) structure between the fixed magnet and the top electrode.

Example 12: A perpendicular spin orbit torque (pSOT) memory device includes a spin orbit torque electrode and a MTJ memory device disposed above a portion of the spin orbit torque electrode. The MTJ memory device includes a free layer, wherein the free layer includes a first ferromagnet including a magnetic material selected from the group consisting of Co, Fe, FeB and CoFeB, a conductive layer including a material selected from the group consisting of Ru and Mo disposed on the first free magnet and a second ferromagnet including a magnetic material selected from the group consisting of Co, Fe, FeB and CoFeB, on the conductive layer. The memory device further includes a tunnel barrier disposed on the free layer and a fixed magnet disposed on the tunnel barrier. A SAF structure is disposed above the fixed magnet, a top electrode is disposed above the SAF structure, and a dielectric spacer surrounds the MTJ memory device.

Example 13 : The pSOT memory device of example 12, wherein the spin orbit torque electrode includes a metal selected from the group consisting of tantalum, tungsten and platinum.

Example 14: The pSOT memory device of example 12, wherein the first ferromagnet includes one or more elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the first free magnet.

Example 15 : The pSOT memory device of example 12, wherein the second ferromagnet includes one or more elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the second free magnet.

Example 16: The pSOT memory device of example 12 or 14, wherein the first free ferromagnet has a thickness between 0.5nm and 1.4nm.

Example 17: The pSOT memory device of example 12, wherein the conductive layer is ruthenium and has a thickness between 0.3nm and 0.5nm.

Example 18: The pSOT memory device of example 12 or 17, wherein the conductive layer is molybdenum and has a thickness between 0.0.5nm and 1.4nm.

Example 19: A method of fabricating a spin orbit torque (SOT) device includes, depositing a spin orbit toque electrode layer disposed above a substrate and patterning the spin orbit torque electrode layer to form a spin orbit torque electrode having an uppermost surface. The method further includes forming a material layer stack for a magnetic tunnel junction (MTJ) memory device on the uppermost surface of the spin orbit torque electrode, where the forming includes forming a magnetic storage layer, depositing a first ferromagnet on the spin orbit torque electrode, forming an antiferromagnetic coupled layer disposed above the first ferromagnet and depositing a second ferromagnetic layer on the non-magnetic spacer layer. The method further includes depositing a tunnel barrier layer on the magnetic storage layer, depositing a fixed magnetic layer on the tunnel barrier layer and depositing a top electrode layer on the fixed magnetic layer. The method further includes etching the material layer stack to form an MTJ device over a portion of the spin orbit torque electrode.

Example 20: The method of example 19, wherein forming the magnetic storage layer includes forming the first free magnetic layer and the second free magnetic layer using a physical vapor deposition process.

Example 21 : The method of example 19, further includes doping the first ferromagnet with one or elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the first ferromagnet.

Example 22: The method of example 19, further includes doping the second

ferromagnetic layer with one or elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the second ferromagnetic layer.

Example 23 : The method of example 19, wherein depositing the antiferromagnetic couples layer includes depositing to a thickness of less than 1.2nm to enable antiferromagnetic couples between the first ferromagnet and the second ferromagnetic layer.

Example 24: The method of example 19, wherein the process further includes performing a high temperature anneal to form the second free magnetic layer with a (001) crystal structure by templating off of a (001) crystal structure of the tunnel barrier layer.

Claims

What is claimed is: 1. A spin orbit torque (SOT) memory device, comprising:

a spin orbit torque electrode;

a magnetic tunnel junction (MTJ) memory device above a portion of the spin orbit torque electrode, the MTJ memory device comprising:

a free layer, wherein the free layer includes:

a first free magnet;

a conductive layer on the first free magnet;

a second free magnet on the conductive layer, the conductive layer antiferromagnetically coupling the first free magnet and the second free magnet;

a tunnel barrier on the free layer;

a fixed magnet on the tunnel barrier; and

a top electrode on the fixed magnet.

2. The SOT memory device of claim 1, wherein the spin orbit torque electrode comprises a metal selected from the group consisting of tantalum, tungsten and platinum.

3. The SOT memory device of claim 1, wherein the first free magnet and the second free magnet comprises a magnetic material selected from the group consisting of Co, Fe, FeB and CoFeB.

4. The SOT memory device of claim 3, wherein the first free magnet is doped with one or elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the first free magnet.

5. The SOT memory device of claim 3, wherein the second free magnet is doped with one or elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the first free magnet.

6. The SOT memory device of claim 3, wherein the first free magnet has a thickness between 0.5nm and 2.5nm.

7. The SOT memory device of claim 3, wherein the second free magnet has a thickness between 0.9nm and 2.0 nm.

8. The SOT memory device of claim 1, wherein the conductive layer comprises a metal selected from the group consisting of molybdenum and ruthenium.

9. The SOT memory device of claim 1, wherein the conductive layer has a thickness between 0.3nm and 1.2nm.

10. The SOT memory device of claim 1, wherein the conductive layer is ruthenium and has a thickness between 0.3nm-0.5nm.

11. The SOT memory device of claim 1 further includes a synthetic antiferromagnetic (SAF) structure between the fixed magnet and the top electrode.

12. A perpendicular spin orbit torque (pSOT) memory device, comprising:

a spin orbit torque electrode;

a MTJ memory device above a portion of the spin orbit torque electrode, the MTJ memory device comprising:

a free layer, wherein the free layer includes:

a first ferromagnet including a magnetic material selected from the group consisting of Co, Fe, FeB and CoFeB;

a conductive layer including a material selected from the group consisting of Ru and Mo disposed on the first free magnet;

a second ferromagnet including a magnetic material selected from the group consisting of Co, Fe, FeB and CoFeB, on the conductive layer;

a tunnel barrier on the free layer;

a fixed magnet on the tunnel barrier;

a SAF structure above the fixed magnet;

a top electrode above the SAF structure; and

a dielectric spacer surrounding the MTJ memory device.

13. The pSOT memory device of claim 12, wherein the spin orbit torque electrode comprises a metal selected from the group consisting of tantalum, tungsten and platinum.

14. The pSOT memory device of claim 12, wherein the first ferromagnet includes one or more elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the first free magnet.

15. The pSOT memory device of claim 12, wherein the second ferromagnet includes one or more elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the second free magnet.

16. The pSOT memory device of claim 12, wherein the first free ferromagnet has a thickness between 0.5nm and 1.4nm.

17. The pSOT memory device of claim 12, wherein the conductive layer is ruthenium and has a thickness between 0.3nm and 0.5nm.

18. The pSOT memory device of claim 12, wherein the conductive layer is molybdenum and has a thickness between 0.0.5nm and 1.4nm.

19. A method of fabricating a spin orbit torque (SOT) device, the method comprising:

depositing a spin orbit toque electrode layer above a substrate;

patterning the spin orbit torque electrode layer to form a spin orbit torque electrode having an uppermost surface;

forming a material layer stack for a magnetic tunnel junction (MTJ) memory device on the uppermost surface of the spin orbit torque electrode, the forming comprising:

forming a magnetic storage layer, the forming comprising:

depositing a first ferromagnet on the spin orbit torque electrode; forming an antiferromagnetic coupling layer above the first ferromagnet;

depositing a second ferromagnetic layer on the non-magnetic spacer layer;

depositing a tunnel barrier layer on the magnetic storage layer;

depositing a fixed magnetic layer on the tunnel barrier layer;

depositing a top electrode layer on the fixed magnetic layer;

etching the material layer stack to form an MTJ device over a portion of the spin orbit torque electrode.

20. The method of claim 1 , wherein forming the magnetic storage layer includes forming the first free magnetic layer and the second free magnetic layer using a physical vapor deposition process.

21. The method of claim 20 further includes doping the first ferromagnet with one or elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the first ferromagnet.

22. The method of claim 20 further includes doping the second ferromagnetic layer with one or elements selected from the group consisting of Mo, W, Ta, Si or Zr, wherein the total amount of the one or more elements is between 10-20 atomic percent of the total composition of the second ferromagnetic layer.

23. The method of claim 20, wherein depositing the antiferromagnetic coupling layer includes depositing to a thickness of less than 1.2nm to enable antiferromagnetic coupling between the first ferromagnet and the second ferromagnetic layer.

24. The method of claim 19, wherein the process further includes performing a high temperature anneal to form the second free magnetic layer with a (001) crystal structure by templating off of a (001) crystal structure of the tunnel barrier layer.