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US20170093435A1 - Data processing device and data processing method - Google Patents

Data processing device and data processing method Download PDF

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Publication number
US20170093435A1
US20170093435A1 US15/122,439 US201515122439A US2017093435A1 US 20170093435 A1 US20170093435 A1 US 20170093435A1 US 201515122439 A US201515122439 A US 201515122439A US 2017093435 A1 US2017093435 A1 US 2017093435A1
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Prior art keywords
parity check
bits
ldpc code
check matrix
code
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US15/122,439
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Ryoji IKEGAYA
Makiko YAMAMOTO
Yuji Shinohara
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Saturn Licensing LLC
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Sony Corp
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Publication of US20170093435A1 publication Critical patent/US20170093435A1/en
Assigned to SATURN LICENSING LLC reassignment SATURN LICENSING LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SONY CORPORATION
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
    • H03M13/356—Unequal error protection [UEP]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • the present technology relates to a data processing device and a data processing method, and more particularly, to a data processing device and a data processing method capable of securing excellent communication quality, for example, in data transmission using an LDPC code.
  • a low density parity check (LDPC) code has a high error correction capability, and in recent years, the LDPC code has widely been employed in transmission schemes of digital broadcasting such as Digital Video Broadcasting (DVB)-S.2, DVB-T.2, and DVB-C.2 of Europe and the like, or Advanced Television Systems Committee (ATSC) 3.0 of the USA and the like (for example, see Non-Patent Document 1).
  • DVD Digital Video Broadcasting
  • DVB-T.2 DVB-T.2
  • DVB-C.2 Advanced Television Systems Committee 3.0 of the USA and the like
  • the LDPC code has a property that a shortest distance is proportional to the code length, the LDPC code has advantages of a block error probability characteristic being superior and a so-called error floor phenomenon observed in a decoding characteristic of the turbo code or the like rarely occurring as characteristics thereof.
  • the LDPC code is converted into a symbol of a quadrature modulation (digital modulation) such as Quadrature Phase Shift Keying (QPSK), and the symbol is mapped to a signal point of the quadrature modulation and is transmitted.
  • a quadrature modulation digital modulation
  • QPSK Quadrature Phase Shift Keying
  • the data transmission using the LDPC code as above has spread worldwide, and there is a demand to secure excellent communication (transmission) quality.
  • the present technology is in consideration of such a situation and enables the securement of excellent communication quality in data transmission using an LDPC code.
  • a first data processing device/method including: a coding unit/step that performs LDPC coding on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15; a group-wise interleaving unit/step that performs group-wise interleave interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit/step that maps the LDPC code into one of 1024 signal points determined according to a modulation scheme in units of 10 bits, wherein, in the group-wise interleave, by using an (i+1)-th bit group from a head of the LDPC code as a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes information bits and parity bits
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits
  • the information matrix portion is represented by a parity check matrix initial value table
  • the parity check matrix initial value table is a table representing a position of an element “1” in the information matrix portion for every 360 columns and is
  • LDPC coding is performed on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15, group-wise interleave interleaving the LDPC code in units of bit groups of 360 bits is performed, and the LDPC code is mapped into one of 1024 signal points determined according to a modulation scheme in units of 10 bits.
  • group-wise interleave by using an (i+1)-th bit group from a head of the LDPC code as a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes information bits and parity bits
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits
  • the information matrix portion is represented by a parity check matrix initial value table
  • the parity check matrix initial value table is a table representing a position of an element “1” in the information matrix portion for every 360 columns and is
  • a second data processing device/method including a group-wise deinterleaving unit/step that returns a sequence of the LDPC code after the group-wise interleave that is acquired from data transmitted from a transmitting device to an original state.
  • the transmitting device includes: a coding unit that performs LDPC coding on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15; a group-wise interleaving unit that performs group-wise interleave interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit that maps the LDPC code into one of 1024 signal points determined according to a modulation scheme in units of 10 bits, wherein, in the group-wise interleave, by using an (i+1)-th bit group from a head of the LDPC code as a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes information bits and parity bits
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits
  • the information matrix portion is represented by a parity check matrix initial value table
  • the parity check matrix initial value table is a table representing a position of an element “1” in the information matrix portion for every 360 columns and is
  • a sequence of the LDPC code after the group-wise interleave that is acquired from data transmitted from a transmitting device is returned to an original state
  • the transmitting device includes: a coding unit that performs LDPC coding on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15; a group-wise interleaving unit that performs group-wise interleave interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit that maps the LDPC code into one of 1024 signal points determined according to a modulation scheme in units of 10 bits, wherein, in the group-wise interleave, by using an (i+1)-th bit group from a head of the LDPC code as a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes information bits and parity bits
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits
  • the information matrix portion is represented by a parity check matrix initial value table
  • the parity check matrix initial value table is a table representing a position of an element “1” in the information matrix portion for every 360 columns and is
  • a third data processing device/method including: a coding unit/step that performs LDPC coding on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15; a group-wise interleaving unit/step that performs group-wise interleave interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit/step that maps the LDPC code into one of 1024 signal points determined according to a modulation scheme in units of 10 bits, wherein, in the group-wise interleave, by using an (i+1)-th bit group from a head of the LDPC code as a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes information bits and parity bits
  • the LDPC code includes information bits and parity bits
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits
  • the information matrix portion is represented by a parity check matrix initial value table
  • the parity check matrix initial value table is a table representing a position of an element “1” in the information matrix portion for every 360 columns and is
  • LDPC coding is performed on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15, group-wise interleave interleaving the LDPC code in units of bit groups of 360 bits is performed, and the LDPC code is mapped into one of 1024 signal points determined according to a modulation scheme in units of 10 bits.
  • group-wise interleave by using an (i+1)-th bit group from a head of the LDPC code as a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes information bits and parity bits
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits
  • the information matrix portion is represented by a parity check matrix initial value table
  • the parity check matrix initial value table is a table representing a position of an element “1” in the information matrix portion for every 360 columns and is
  • a fourth data processing device/method including a group-wise deinterleaving unit/step that returns a sequence of the LDPC code after the group-wise interleave that is acquired from data transmitted from a transmitting device to an original state.
  • the transmitting device includes: a coding unit that performs LDPC coding on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15; a group-wise interleaving unit that performs group-wise interleave interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit that maps the LDPC code into one of 1024 signal points determined according to a modulation scheme in units of 10 bits, wherein, in the group-wise interleave, by using an (i+1)-th bit group from a head of the LDPC code as a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes information bits and parity bits
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits
  • the information matrix portion is represented by a parity check matrix initial value table
  • the parity check matrix initial value table is a table representing a position of an element “1” in the information matrix portion for every 360 columns and is
  • a sequence of the LDPC code after the group-wise interleave that is acquired from data transmitted from a transmitting device is returned to an original state
  • the transmitting device includes: a coding unit that performs LDPC coding on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15; a group-wise interleaving unit that performs group-wise interleave interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit that maps the LDPC code into one of 1024 signal points determined according to a modulation scheme in units of 10 bits, wherein, in the group-wise interleave, by using an (i+1)-th bit group from a head of the LDPC code as a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes information bits and parity bits
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits
  • the information matrix portion is represented by a parity check matrix initial value table
  • the parity check matrix initial value table is a table representing a position of an element “1” in the information matrix portion for every 360 columns and is
  • a fifth data processing device/method including: a coding unit/step that performs LDPC coding on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15; a group-wise interleaving unit/step that performs group-wise interleave interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit/step that maps the LDPC code into one of 1024 signal points determined according to a modulation scheme in units of 10 bits, wherein, in the group-wise interleave, by using an (i+1)-th bit group from a head of the LDPC code as a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes information bits and parity bits
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits
  • the information matrix portion is represented by a parity check matrix initial value table
  • the parity check matrix initial value table is a table representing a position of an element “1” in the information matrix portion for every 360 columns and is

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Algebra (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160211868A1 (en) * 2013-09-26 2016-07-21 Sony Corporation Data processing device and data processing method
US20190027485A1 (en) * 2017-07-19 2019-01-24 Infineon Technologies Ag Memory arrangement
US11177830B2 (en) 2019-09-10 2021-11-16 Samsung Electronics Co., Ltd. Method and apparatus for data decoding in communication or broadcasting system
US20230362048A1 (en) * 2021-01-15 2023-11-09 Huawei Technologies Co., Ltd. Data transmission method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015179960A (ja) * 2014-03-19 2015-10-08 ソニー株式会社 データ処理装置、及び、データ処理方法
JP6820192B2 (ja) * 2016-12-19 2021-01-27 日本放送協会 送信装置及び受信装置
JP6820193B2 (ja) * 2016-12-19 2021-01-27 日本放送協会 送信装置及び受信装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7334181B2 (en) 2003-09-04 2008-02-19 The Directv Group, Inc. Method and system for providing short block length low density parity check (LDPC) codes
US7555696B2 (en) * 2004-12-09 2009-06-30 General Instrument Corporation Method and apparatus for forward error correction in a content distribution system
US7451361B2 (en) * 2005-01-27 2008-11-11 General Instrument Corporation Method and apparatus for forward error correction in a content distribution system
JP4622654B2 (ja) * 2005-04-25 2011-02-02 ソニー株式会社 復号装置および復号方法
DE602006011240D1 (de) * 2005-06-21 2010-02-04 Samsung Electronics Co Ltd Vorrichtung und Methode zum Übermitteln/Empfangen von Daten in einem Mehrantennenkommunikationssystem unter Verwendung eines strukturierten Low Density Parity Check (LDPC) Codes
KR101435681B1 (ko) * 2007-11-08 2014-09-02 삼성전자주식회사 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서데이터 송수신 장치 및 방법
US8402337B2 (en) * 2007-11-26 2013-03-19 Sony Corporation Data processing apparatus and data processing method as well as encoding apparatus and encoding method
HUE025389T2 (en) * 2008-03-03 2016-02-29 Rai Radiotelevisione Italiana (S P A ) Bitermutation pattern for LDPC coded modulation and 64 QAM constellation patterns
EP2134051A1 (en) 2008-06-13 2009-12-16 THOMSON Licensing An adaptive QAM transmission scheme for improving performance on an AWGN channel
TWI427936B (zh) * 2009-05-29 2014-02-21 Sony Corp 接收設備，接收方法，程式，及接收系統
JP5664919B2 (ja) 2011-06-15 2015-02-04 ソニー株式会社 データ処理装置、及び、データ処理方法
WO2014123018A1 (ja) * 2013-02-08 2014-08-14 ソニー株式会社 データ処理装置、及びデータ処理方法
KR20160061328A (ko) * 2013-09-26 2016-05-31 소니 주식회사 데이터 처리 장치 및 데이터 처리 방법
WO2015045897A1 (ja) * 2013-09-26 2015-04-02 ソニー株式会社 データ処理装置、及びデータ処理方法
JP2015156532A (ja) * 2014-02-19 2015-08-27 ソニー株式会社 データ処理装置、及び、データ処理方法
JP2015156534A (ja) * 2014-02-19 2015-08-27 ソニー株式会社 データ処理装置、及び、データ処理方法
JP2015170912A (ja) * 2014-03-05 2015-09-28 ソニー株式会社 データ処理装置、及び、データ処理方法
JP2015179960A (ja) * 2014-03-19 2015-10-08 ソニー株式会社 データ処理装置、及び、データ処理方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160211868A1 (en) * 2013-09-26 2016-07-21 Sony Corporation Data processing device and data processing method
US20190027485A1 (en) * 2017-07-19 2019-01-24 Infineon Technologies Ag Memory arrangement
US10546866B2 (en) * 2017-07-19 2020-01-28 Infineon Technologies Ag Memory arrangement and detection circuit for data protection
US11177830B2 (en) 2019-09-10 2021-11-16 Samsung Electronics Co., Ltd. Method and apparatus for data decoding in communication or broadcasting system
US11876534B2 (en) 2019-09-10 2024-01-16 Samsung Electronics Co., Ltd. Method and apparatus for data decoding in communication or broadcasting system
US20230362048A1 (en) * 2021-01-15 2023-11-09 Huawei Technologies Co., Ltd. Data transmission method

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US11239863B2 (en) 2022-02-01
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US20200304152A1 (en) 2020-09-24
US10659080B2 (en) 2020-05-19
KR102113965B1 (ko) 2020-05-21
KR102062378B1 (ko) 2020-02-17
KR101929144B1 (ko) 2018-12-13
US20180337693A1 (en) 2018-11-22
KR102022212B1 (ko) 2019-09-17
MX376800B (es) 2025-03-07

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