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US20150123195A1 - Recessed channel access transistor device and fabrication method thereof - Google Patents

Recessed channel access transistor device and fabrication method thereof Download PDF

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Publication number
US20150123195A1
US20150123195A1 US14/070,589 US201314070589A US2015123195A1 US 20150123195 A1 US20150123195 A1 US 20150123195A1 US 201314070589 A US201314070589 A US 201314070589A US 2015123195 A1 US2015123195 A1 US 2015123195A1
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US
United States
Prior art keywords
doping region
trench
semiconductor substrate
access transistor
channel access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/070,589
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English (en)
Inventor
Tieh-Chiang Wu
Wei-Ming Liao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanya Technology Corp
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Priority to US14/070,589 priority Critical patent/US20150123195A1/en
Assigned to NANYA TECHNOLOGY CORP. reassignment NANYA TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIAO, Wei-ming, WU, TIEH-CHIANG
Priority to TW103100089A priority patent/TWI532181B/zh
Priority to CN201410026351.XA priority patent/CN104617140B/zh
Priority to US14/616,750 priority patent/US9343547B2/en
Publication of US20150123195A1 publication Critical patent/US20150123195A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H01L29/4236—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H01L29/66621—
    • H01L29/76—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/36—Unipolar devices
    • H10D64/013—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
    • H10P30/20—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

Definitions

  • the present invention relates generally to semiconductor devices. More particularly, the present invention relates to a recessed channel access transistor (RCAT) device for high-density dynamic random access memory (DRAM) applications.
  • RCAT recessed channel access transistor
  • Recessed channel access transistor devices have been developed to suppressing the short channel effect by physically increasing the gate channel length without an increase in a lateral area of a gate electrode.
  • an RCAT transistor has a gate oxide layer formed on sidewalls and the bottom surface of a recess etched into a substrate, where a conductive substance fills the recess. Contrary to a planar gate type transistor having a gate electrode formed on a planar surface of a substrate, the RCAT transistor has a U-shaped channel along the surface of the recess. Therefore, the integration of the recessed-gate transistor can be increased.
  • a drain voltage (Vd) when a drain voltage (Vd) is applied to a capacitor that is electrically connected to an NMOS transistor, agate induced drain leakage (GIDL) problem may occur.
  • Vd drain voltage
  • GIDL gate induced drain leakage
  • a recessed channel access transistor device is provided.
  • a semiconductor substrate having thereon a trench is provided. The trench extends from a main surface of the semiconductor substrate to a predetermined depth.
  • a buried gate electrode is disposed at a lower portion of the trench.
  • Agate oxide layer is formed between the buried gate electrode and the semiconductor substrate.
  • a drain doping region on a first side (cell side) of the trench in the semiconductor substrate and a source doping region on a second side (digit side) of the trench are formed.
  • the source doping region has a junction depth that is deeper than that of the drain doping region.
  • An L-shaped channel is defined along a sidewall surface on the first side and along a bottom surface of the trench between the drain doping region and the source doping region.
  • a method for fabricating a recessed channel access transistor device is provided.
  • a semiconductor substrate having thereon a trench extending from a main surface of the semiconductor substrate to a predetermined depth is prepared.
  • a gate oxide layer is formed on interior surface of the trench.
  • a buried gate electrode is formed at a lower portion of the trench.
  • the capping the buried gate electrode is capped with a dielectric layer.
  • a pad layer and hard mask layer are formed on the main surface of the semiconductor substrate.
  • a recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench, wherein a portion of the dielectric layer is revealed within the recess.
  • the hard mask layer is then removed.
  • the source doping region has a junction depth that is deeper than that of the drain doping region.
  • FIGS. 1-7 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a recessed channel access transistor (RCAT) device in accordance with one embodiment of the present invention
  • FIGS. 8-10 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a RCAT device in accordance with another embodiment of the present invention.
  • FIGS. 11-13 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a RCAT device in accordance with yet another embodiment of the present invention.
  • an oxidation process may be performed to form a gate oxide layer 14 on the interior surface of the trench 12 .
  • a gate electrode layer 16 is then deposited on the gate oxide layer 14 and fills the trench 12 .
  • the gate electrode layer 16 may comprise polysilicon, for example.
  • an etch back process may be performed to recess the gate electrode layer 16 such that the top surface of the recessed gate electrode layer 16 is lower than the main surface 10 a of the semiconductor substrate 10 .
  • a dielectric layer 18 such as a silicon oxide layer is deposited over the semiconductor substrate 10 in a blanket manner. The dielectric layer 18 fills the trench 12 , thereby forming a buried gate electrode 16 a at the lower portion of the trench 12 .
  • a planarization process such as a chemical mechanical polishing (CMP) process is carried out to remove excess dielectric layer 18 from the main surface 10 a of the semiconductor substrate 10 .
  • CMP chemical mechanical polishing
  • a lithographic process and a dry etching process are performed to from a recess 30 in the semiconductor substrate 10 on one single side of the trench 12 .
  • a portion of the dielectric layer 18 is revealed within the recess 30 .
  • a lower top surface 10 b of the semiconductor substrate 10 is formed.
  • the hard mask layer 24 is stripped off, while leaving the pad layer 22 substantially intact.
  • an ion implantation process 40 is performed to implant dopants such as N type dopants into the semiconductor substrate 10 on both sides of the trench 12 , that is, the digit side and the cell side in this embodiment, thereby forming a RCAT device 1 with asymmetric drain doping region 42 and source doping region 44 .
  • PN junction depth 44 a of the source doping region 44 on the digit side may be equal to the depth d of the trench 12 .
  • the PN junction depth 42 a of the drain doping region 42 on the cell side may be shallower in order to maintain an adequate operation current level when operating the RCAT device 1 .
  • a contact (not shown) may be formed on the source doping region 44 to couple to a digit line (not shown).
  • the RCAT device 1 comprises a semiconductor substrate 10 having thereon a trench 12 extending from a main surface 10 a of the semiconductor substrate 10 to a predetermined depth d, a buried gate electrode 16 a disposed at a lower portion of the trench 12 , a gate oxide layer 14 between the buried gate electrode 16 a and the semiconductor substrate 10 , a drain doping region 42 on a first side (cell side) of the trench in the semiconductor substrate 10 , and a source doping region 44 on a second side (digit side) of the trench.
  • the source doping region 44 has a junction depth that is deeper than that of the drain doping region 42 .
  • An L-shaped channel 50 is defined along a sidewall surface on the first side and along a bottom surface of the trench 12 between the drain doping region 42 and the source doping region 44 .
  • FIGS. 8-10 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a RCAT device in accordance with another embodiment of the present invention.
  • a planarization process such as a CMP process is carried out to remove excess dielectric layer 18 from the main surface 10 a of the semiconductor substrate 10 .
  • the polished top surface of the dielectric layer 18 is substantially flush with the main surface 10 a.
  • a pad layer 22 is then deposited in a blanket manner.
  • the pad layer 22 may be a silicon oxide layer.
  • a hard mask layer 24 such as a silicon nitride layer is then deposited on the pad layer 22 .
  • a lithographic process and a dry etching process are performed to from a recess 30 in the semiconductor substrate 10 on the digit side. At this point, a portion of the dielectric layer 18 is revealed within the recess 30 .
  • PN junction depth 44 a of the source doping region 44 on the digit side may be equal to the depth d of the trench 12 .
  • the PN junction depth 42 a of the drain doping region 42 on the cell side may be shallower in order to maintain an adequate operation current level when operating the RCAT device 1 .
  • a contact (not shown) may be formed on the source doping region 44 to couple to a digit line (not shown).
  • the hard mask layer 24 may be removed.
  • a pad layer 22 is then deposited in a blanket manner.
  • the pad layer 22 may be a silicon oxide layer.
  • a hard mask layer (not shown in this figure) such as a silicon nitride layer is then deposited on the pad layer 22 .
  • a lithographic process and a dry etching process are performed to from a recess 30 in the semiconductor substrate 10 on the digit side. At this point, a portion of the dielectric layer 18 is revealed within the recess 30 . Thereafter, the hard mask layer is stripped off, while leaving the pad layer 22 substantially intact.
  • a doped polysilicon layer (not shown) is then deposited on the semiconductor substrate 10 and fills the recess 30 .
  • a lithographic process and a dry etching process are performed to pattern the doped polysilicon layer into a contact element 60 situated directly on the recess 30 .
  • a thermal process may be performed to drive the dopants from the contact element 60 into the portion of the semiconductor substrate 10 that is in direct contact with the contact element 60 , thereby forming a source doping region 44 .
  • the PN junction depth 44 a of the source doping region 44 on the digit side may be equal to the depth d of the trench 12 .
  • the PN junction depth 42 a of the drain doping region 42 on the cell side may be shallower in order to maintain an adequate operation current level when operating the RCAT device 1 c .
  • the contact element 60 formed on the source doping region 44 may be coupled to a digit line (not shown).

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
US14/070,589 2013-11-04 2013-11-04 Recessed channel access transistor device and fabrication method thereof Abandoned US20150123195A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US14/070,589 US20150123195A1 (en) 2013-11-04 2013-11-04 Recessed channel access transistor device and fabrication method thereof
TW103100089A TWI532181B (zh) 2013-11-04 2014-01-02 凹入式通道存取電晶體元件及其製作方法
CN201410026351.XA CN104617140B (zh) 2013-11-04 2014-01-21 凹入式沟道存取晶体管器件及其制作方法
US14/616,750 US9343547B2 (en) 2013-11-04 2015-02-09 Method for fabricating a recessed channel access transistor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/070,589 US20150123195A1 (en) 2013-11-04 2013-11-04 Recessed channel access transistor device and fabrication method thereof

Related Child Applications (1)

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CN (1) CN104617140B (zh)
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Cited By (2)

* Cited by examiner, † Cited by third party
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US20220045185A1 (en) * 2020-06-01 2022-02-10 Nanya Technology Corporation Semiconductor device
US20220102484A1 (en) * 2019-10-23 2022-03-31 Nanya Technology Corporation Method of fabricating semiconductor structure

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Publication number Priority date Publication date Assignee Title
CN109390341A (zh) * 2018-08-17 2019-02-26 刘文剑 一种漏电过程自控的凹入式沟道动态随机存储器单元
CN113097302B (zh) * 2020-01-09 2022-09-27 长鑫存储技术有限公司 晶体管及其制作方法
CN115224119A (zh) * 2021-04-21 2022-10-21 长鑫存储技术有限公司 半导体结构及半导体结构的制备方法

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US7888734B2 (en) * 2008-12-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. High-voltage MOS devices having gates extending into recesses of substrates
JP2012174866A (ja) * 2011-02-21 2012-09-10 Elpida Memory Inc 半導体装置およびその製造方法
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US20120273859A1 (en) * 2011-04-28 2012-11-01 Elpida Memory, Inc. Semiconductor device and method of forming the same
US20120299090A1 (en) * 2011-05-25 2012-11-29 Ji-Young Kim Semiconductor Devices Including Dual Gate Electrode Structures And Related Methods
US20140001525A1 (en) * 2012-06-28 2014-01-02 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220102484A1 (en) * 2019-10-23 2022-03-31 Nanya Technology Corporation Method of fabricating semiconductor structure
US11848353B2 (en) * 2019-10-23 2023-12-19 Nanya Technology Corporation Method of fabricating semiconductor structure
US20220045185A1 (en) * 2020-06-01 2022-02-10 Nanya Technology Corporation Semiconductor device
US12021127B2 (en) * 2020-06-01 2024-06-25 Nanya Technology Corporation Semiconductor device including a buried channel array transistor structure

Also Published As

Publication number Publication date
TW201519447A (zh) 2015-05-16
US20150155367A1 (en) 2015-06-04
CN104617140A (zh) 2015-05-13
CN104617140B (zh) 2018-05-22
TWI532181B (zh) 2016-05-01
US9343547B2 (en) 2016-05-17

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Owner name: NANYA TECHNOLOGY CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WU, TIEH-CHIANG;LIAO, WEI-MING;REEL/FRAME:031533/0629

Effective date: 20131031

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION