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US20140231997A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
US20140231997A1
US20140231997A1 US14/021,002 US201314021002A US2014231997A1 US 20140231997 A1 US20140231997 A1 US 20140231997A1 US 201314021002 A US201314021002 A US 201314021002A US 2014231997 A1 US2014231997 A1 US 2014231997A1
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United States
Prior art keywords
layer
interlayer
semiconductor device
semiconductor
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US14/021,002
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English (en)
Inventor
Fumio Sasaki
Hisao Kawasaki
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Toshiba Corp
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Toshiba Corp
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Filing date
Publication date
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KAWASAKI, HISAO, SASAKI, FUMIO
Publication of US20140231997A1 publication Critical patent/US20140231997A1/en
Priority to US14/822,224 priority Critical patent/US9269619B2/en
Abandoned legal-status Critical Current

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    • H10W20/057—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H10W72/00—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H10P95/90—
    • H10W20/023—
    • H10W20/042—
    • H10W20/4441—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
    • H10W72/923—
    • H10W72/9415—
    • H10W72/942—
    • H10W72/952—

Definitions

  • An embodiment relates to a semiconductor device and a method for manufacturing the same.
  • an electrode provided on a surface of the semiconductor layer and a back electrode provided on a back surface of the semiconductor layer are electrically connected using a via hole.
  • a surface side electrode is grounded and operation of the semiconductor device is stabilized.
  • the surface side electrode consists of an alloy layer containing gold germanium (AuGe), nickel (Ni) and gold (Au), and a reaction layer which is formed by reaction of the alloy layer and the semiconductor layer.
  • a hole of the via hole is formed by etching the semiconductor layer selectively using an RIE (Reactive Ion Etching) method, for example.
  • Etching gas contains chlorine, for example.
  • the surface side electrode may deform with the heat at the time of mounting the semiconductor device on a package or a mounting board, and thereby a contact between the surface side electrode and the back electrode may become unstable.
  • the embodiment supplies a reliable semiconductor device in which a connection between a surface side electrode and a back electrode through a via hole is stable.
  • FIGS. 1A and 1B are schematic diagrams showing a semiconductor device concerning an embodiment
  • FIG. 2 is a flow chart showing a manufacture process of the semiconductor device concerning the embodiment
  • FIGS. 3A-3F are schematic sectional views showing the manufacture process of the semiconductor device concerning the embodiment.
  • FIGS. 4A and 4B are schematic sectional views showing a semiconductor device concerning a comparative example.
  • a semiconductor device includes a semiconductor layer, an interlayer, an electrode provided on the interlayer, and an electrical conductive layer which is electrically connected to the electrode.
  • the semiconductor layer has a first surface and a second surface which is opposite to the first surface.
  • the interlayer is provided on the first surface, and includes a metal layer consisting of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency.
  • the electrical conductive layer covers an inside of a hole which is formed in the semiconductor layer so as to reach the interlayer from the second surface, and is electrically connected to the electrode via the interlayer which is exposed to a bottom of the hole.
  • FIG. 1A and FIG. 1B are schematic diagrams showing a semiconductor device 1 concerning the embodiment.
  • FIG. 1A is a top view showing a part of the semiconductor device.
  • FIG. 1B is a sectional view taken along line 1 B - 1 B shown in FIG. 1A .
  • the semiconductor device 1 is a field effect transistor, for example, and is provided with a functional part 7 and a pad electrode 10 .
  • the functional part 7 contains source electrodes 3 , drain electrodes 4 , and gate electrodes 5 .
  • the pad electrode 10 is connected to a plurality of the source electrodes 3 .
  • the semiconductor device 1 is provided with a semiconductor layer 20 , an electrical conductive layer 30 , and an interlayer 40 .
  • the semiconductor layer 20 has a first surface 20 a , and a second surface 20 b that is opposite to the first surface 20 a.
  • the interlayer 40 is formed in contact with the first side 20 a of the semiconductor layer 20 .
  • the pad electrode 10 is formed on the interlayer 40 .
  • Another layer which has conductivity may be provided between the pad electrode 10 and the interlayer 40 .
  • the semiconductor layer 20 has a via hole 17 .
  • the via hole 17 includes a hole 17 a which penetrates the semiconductor layer 20 in the direction facing to the pad electrode 10 from the second surface 20 b and reaches the interlayer 40 from the second surface 20 b, and a via contact 30 a which covers an inside of the hole 17 a.
  • the electrical conductive layer 30 contains the via contact 30 a and a back electrode 30 b provided on the second surface 20 a.
  • the via contact 30 a is in contact with the interlayer 40 which is exposed to a bottom 17 b of the hole 17 a.
  • the interlayer 40 is an electrical conductive layer containing platinum (Pt), for example, and the electrical conductive layer 30 is electrically connected to the pad electrode 10 via the interlayer 40 .
  • the interlayer 40 contains a metal layer 13 and a reaction layer 15 which is formed by reaction of the metal layer 13 and the semiconductor layer 20 .
  • the electrical conductive layer 30 is in contact with the reaction layer 15 .
  • the reaction layer 15 may be removed at the bottom 17 b of the hole 17 and the electrical conductive layer 30 may be contact with the metal layer 13 directly.
  • the metal layer 13 consists of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency, for example.
  • the interlayer 40 is apart from the functional part 7 which is electrically connected to the pad electrode 10 . That is, the interlayer 40 should just be under the pad electrode 10 , and does not need to be provide under the functional part 7 and a part which connects the functional part 7 and the pad electrode 10 .
  • FIG. 2 is a flow chart showing the manufacture process of the semiconductor device 1 concerning the embodiment.
  • FIGS. 3A-3F are schematic sectional views showing the manufacture process of the semiconductor device concerning the embodiment.
  • FIGS. 3A-3F correspond to steps 01-06 shown in FIG. 2 and show partial cross section of a wafer in each step.
  • the metal layer 13 is formed on the first surface 20 a of the semiconductor layer 20 as shown in FIG. 3A (S 01 ).
  • the semiconductor layer 20 is a high resistance layer of semi-insulation, and gallium arsenide (GaAs), indium phosphate (InP), or gallium nitride (GaN) can be used as the semiconductor layer 20 , for example. Also, a GaAs board or InP board of semi-insulation may be sufficient as the semiconductor layer 20 .
  • GaAs gallium arsenide
  • InP indium phosphate
  • GaN gallium nitride
  • the metal layer 13 is selectively formed on a part of the semiconductor layer 20 on which the pad electrode 10 is formed.
  • the metal layer 13 is desirable to have tolerance for the dry etching which is used for formation of the hole 17 a for the via hole 17 . That is, a metal which is chemically stable and does not react to the active element contained in an etching gas is used as the metal layer 13 .
  • the etching gas contains chlorine when the semiconductor layer 20 is a GaAs layer or an InP layer, for example. Therefore, it is preferable to use platinum (Pt) which is stable chemically to chlorine as the metal layer 13 .
  • the specific resistance of platinum is larger than the specific resistance of gold (Au) which is used for the pad electrode 10 .
  • Au gold
  • the thickness of the metal layer 13 it is desirable that it is not larger than 60 nm, for example.
  • the reaction layer 15 containing platinum is formed between the semiconductor layer 20 and the metal layer 13 .
  • the pad electrode 10 is formed on the metal layer 13 (S 03 ).
  • the pad electrode 10 is a source pad, for example, and is formed so as to be connected to the source electrodes 3 .
  • An Au layer can be used as the pad electrode 10 , for example.
  • the semiconductor layer 20 is thinned (S 04 ).
  • the semiconductor layer 20 is thinned to thickness of several 10 ⁇ m by grinding or polishing.
  • an epitaxially grown layer separated from a growth board may be used as the semiconductor layer 20 .
  • the hole 17 a is formed in the direction which faces to the pad electrode 10 from the second surface 20 b of the semiconductor layer 20 which has been thinned (S 05 ).
  • the semiconductor layer 20 is selectively etched using the RIE (Reactive Ion Etching) method, for example, to thereby form the hole 17 a.
  • An etching gas contains chlorine, for example.
  • the hole 17 a reaches either of the reaction layer 15 and the metal layers 13 .
  • the reaction layer 15 contains platinum.
  • the etching rate of the reaction layer 15 becomes lower than the etching rate of the semiconductor layer 20 . Thereby, it becomes easy to stop etching at the reaction layer 15 . That is, the reaction layer 15 can be exposed to the second surface side of the semiconductor layer 20 . Also, the reaction layer 15 may be removed to thereby expose the metal layer 13 .
  • the electrical conductive layer 30 which covers the inside of the hole 17 a is formed and thereby the via hole 17 is formed (S 06 ).
  • the electrical conductive layer 30 is a gold plate layer, for example.
  • a seed layer 21 is formed on the inside of the hole 17 a and the second surface 20 b, for example.
  • electrolytic plating of gold is performed while flowing current through the seed layer 21 and a gold plate layer is formed on the seed layer 21 .
  • a two-layer film in which titanium (Ti) and gold (Au) are laminated in order from the semiconductor layer 20 side can be used as the seed layer 21 , for example.
  • Ti film raises the adhesion power between the semiconductor layer 20 and the electrical conductive layer 30 , and raises the adhesion power between the reaction layer 15 and the electrical conductive layer 30 .
  • the above-mentioned manufacture process can form a via-structure which electrically connects the pad electrode 10 provided on first surface 20 a of the semiconductor layer 20 and the electrical conductive layer 30 provided in the second surface 20 b side.
  • FIGS. 4A and 4B are schematic sectional views showing a semiconductor device 2 concerning a comparative example.
  • FIG. 4A shows a cross section (refer to FIG. 1B ) taken along an I B -I B line.
  • FIG. 4B is an enlarged drawing of a part A shown in FIG. 4A , and shows a connection structure between the pad electrode 10 and the electrical conductive layer 30 .
  • the semiconductor device 2 includes a metal layer 23 and a reaction layer 25 .
  • the metal layer 23 contains a metal whose standard oxidation-reduction potential is lower than 0 (zero) V in an ionization tendency, for example.
  • the reaction layer 25 contains a metal whose standard oxidation-reduction potential is lower than 0 (zero) V in an ionization tendency, for example.
  • the metal layer 23 contains gold germanium (AuGe), nickel (nickel) and gold (Au) which were laminated in order from the semiconductor layer 20 side, for example, because the semiconductor device 2 uses a metal layer which is simultaneously formed with the ohmic electrode as a surface side electrode. That is, the metal layer 23 contains nickel which reacts chemically with chlorine. And the reaction layer 25 which is formed by heat-treating the metal layer 23 and the semiconductor layer 20 also contains nickel.
  • the semiconductor layer 20 is etched in the direction which faces to the pad electrode 10 from the second surface 20 b of the semiconductor layer 20 by dry etching and thereby the hole 17 a is formed. And the reaction layer 25 is exposed to the second surface 20 b side. At this time, nickel contained in the reaction layer 25 reacts with chlorine contained in an etching gas, and thereby chlorination nickel (NiCl2) is produced on an exposed surface of the reaction layer 25 .
  • Chlorination nickel corrodes the reaction layer 25 in the formation process of the electrical conductive layer 30 , and forms voids 31 in the surface of the reaction layer 25 as shown in FIG. 4B .
  • plating liquid enters into the voids 31 in the process of gold-plating which forms an electrical conductive layer 30 , and the plating liquid may remain in the void 31 as it is.
  • the plating liquid which remains inside the void 31 evaporate to thereby raise the internal pressure of the void 31 .
  • the phenomenon in which the reaction layer 25 is dissociated from the electrical conductive layer 30 , and in which the reaction layer 25 , the metal layer 23 and pad electrode 10 are inflated occurs.
  • an electrical connection between the electrical conductive layer 30 and the pad electrode 10 may be lost, and operation of the semiconductor device 2 may become unstable.
  • the metal layer 13 is chemically stable to chlorine contained in the etching gas. That is, the metal layer 13 does not contain any element that reacts with the active element contained in the etching gas. Even if the metal layer 13 contains such an element that reacts with the active element contained in the etching gas, the concentration of such element is not higher than a level detectable using the measuring means, such as an SIMS (Secondary Ion Mass Spectrometry) and a Auger spectroscopy.
  • SIMS Single Ion Mass Spectrometry
  • the reaction layer 15 that is formed by reaction of the metal layer 13 and the semiconductor layer 20 does not contain any unstable element to chlorine contained in the etching gas. For this reason, the void 31 is not formed between the reaction layer 15 and the electrical conductive layer 30 , and deformation of the reaction layer 15 , the metal layer 13 and the pad electrode 10 can be suppressed. And the electrical connection between the electrical conductive layer 30 and the pad electrode 10 is held stable, and the reliability of the semiconductor device can be improved.
  • a metal which is chemically unstable to chlorine contained in the etching gas is metal whose standard oxidation-reduction potential is lower than 0 (zero) V in an ionization tendency.
  • a metal which is chemically stable to chlorine contained in the etching gas is a metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency. Copper (Cu), palladium (Pd), platinum (Pt), gold (Au), etc. out of the metals used in a semiconductor process in many cases, correspond to such a metal.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
US14/021,002 2013-02-21 2013-09-09 Semiconductor device and method for manufacturing the same Abandoned US20140231997A1 (en)

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JP2013032528 2013-02-21
JP2013-032528 2013-02-21
JP2013-109204 2013-05-23
JP2013109204A JP6034747B2 (ja) 2013-02-21 2013-05-23 半導体装置およびその製造方法

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US (2) US20140231997A1 (zh)
EP (1) EP2770529B1 (zh)
JP (1) JP6034747B2 (zh)
KR (2) KR20140104887A (zh)
CN (1) CN104009017A (zh)
TW (1) TWI570868B (zh)

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US12382697B2 (en) 2020-12-22 2025-08-05 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same
WO2026010661A1 (en) * 2024-07-02 2026-01-08 Macom Technology Solutions Holdings, Inc. Enhanced back via landing metal layer adhesion

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12382697B2 (en) 2020-12-22 2025-08-05 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same
WO2026010661A1 (en) * 2024-07-02 2026-01-08 Macom Technology Solutions Holdings, Inc. Enhanced back via landing metal layer adhesion

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JP6034747B2 (ja) 2016-11-30
TWI570868B (zh) 2017-02-11
EP2770529B1 (en) 2020-02-12
EP2770529A2 (en) 2014-08-27
TW201434126A (zh) 2014-09-01
US20150348841A1 (en) 2015-12-03
KR20140104887A (ko) 2014-08-29
US9269619B2 (en) 2016-02-23
KR20150099493A (ko) 2015-08-31
EP2770529A3 (en) 2016-07-27
CN104009017A (zh) 2014-08-27
JP2014187342A (ja) 2014-10-02

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