US20120327623A1

US20120327623A1 - Printed circuit board and layout method thereof

Info

Publication number: US20120327623A1
Application number: US13/596,066
Authority: US
Inventors: Yung-Chieh Chen; Cheng-Hsien Li; Shou-Kuo Hsu
Original assignee: Hon Hai Precision Industry Co Ltd
Current assignee: Hon Hai Precision Industry Co Ltd
Priority date: 2008-07-15
Filing date: 2012-08-28
Publication date: 2012-12-27
Also published as: CN101631425A; US20100012363A1; US8418357B2; CN101631425B

Abstract

A printed circuit board includes first and second layout layers, first and second components, and a pair of connecting portions. The first layout layer includes a pair of first conducting portions connected to a control chip. The second layout layer includes pairs of second to fourth conducting portions. The connecting portions connect the first and third conducting portions together. When an electronic device is connected to the second conducting portions, and the first and second components are connected to the third and fourth conducting portions to form a first route, signals generated by the control chip are transmitted to the electronic device through the first route. When the electronic device is connected to the fourth conducting portions, and the first and second components are connected to the second and third conducting portions to form a second route, the signals are transmitted to the electronic device through the second route.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This present application is a continuation application of U.S. patent application, entitled “PRINTED CIRCUIT BOARD LAYOUT METHOD”, with application Ser. No. 12/329,614, filed on Dec. 7, 2008, which claims foreign priority based on Chinese Patent application No. 200810302746.2, filed in China on Jul. 15, 2008. The contents of the above-referenced applications are hereby incorporated by reference.

BACKGROUND

1. Technical Field
The present disclosure relates to printed circuit boards (PCBs), and more particularly to a PCB and a layout method of the PCB.
2. Description of Related Art
PCBs are designed for coupling control chips to electronic devices in two alternative modes to transmit signals such as high-speed differential signals.
Referring to FIG. 4, a known PCB 1 includes a pair of first transmission lines 11A, 11B, a pair of second transmission lines 12A, 12B, and a pair of third transmission lines 13A, 13B sequentially arranged thereon.
Referring to FIG. 5, in a first coupling mode, a control chip 14 is coupled to the first transmission lines 11A, 11B, and a first electronic device 15 is coupled between the second transmission lines 12A, 12B, and the first transmission lines 11A, 11B. The control chip 14 generates a pair of high-speed signals S1, S2 such as high-speed differential signals. However, a circuit stub is thus created.
Referring to FIG. 6, in a second coupling mode, the control chip 14 is coupled to the first transmission lines 11A, 11B, a second electronic device 16 is coupled to ends of the third transmission lines 13A, 13B away from the control chip 14, and a pair of resistors R1, R2 must be added to connect the second transmission lines 12A, 12B to the third transmission lines 13A, 13B. Cost of the PCB 1 is increased accordingly.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is an exploded, isometric view of a printed circuit board (PCB) in a first coupling mode, in accordance with an embodiment of the present disclosure.

FIG. 2 is an exploded, isometric view of the PCB of FIG. 1 in a second coupling mode.

FIGS. 3A and 3B are flowcharts of a layout method of a PCB in accordance with an embodiment of the present disclosure.

FIG. 4 is a schematic view of a known PCB.

FIG. 5 is a schematic view of the known PCB of FIG. 4, showing a first electronic device coupled therewith.

FIG. 6 is a schematic view of the known PCB of FIG. 4, showing a second electronic device coupled therewith.

DETAILED DESCRIPTION

The disclosure, including the accompanying drawings, is illustrated by way of examples and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.
Referring to FIG. 1, an embodiment of a printed circuit board (PCB) 2 includes an electronic device 4, a first component 21, and a second component 22 connectable in two alternate coupling modes to the PCB 2. The PCB 2 also includes a first layout layer 24, a second layout layer 23, an isolating layer (not shown) positioned between the first layout layer 24 and the second layout layer 23, a pair of connecting portions 29A, 29B, and a control chip 3. The PCB 2 can be, for example, a motherboard.
The first layout layer 24 includes a pair of first parallel conducting portions 25A, 25B, such as, a pair of solder pads.
The second layout layer 23 includes a pair of second parallel conducting portions 26A, 26B, a pair of third parallel conducting portions 27A, 27B, and a pair of fourth parallel conducting portions 28A, 28B, arranged on the second layout layer 23 in corresponding linear alignments. The third conducting portions 27A, 27B electrically connected to the first conducting portions 25A, 25B through the connecting portions 29A, 29B. The connecting portions 29A, 29B are a pair of vias or embedded vias.
For example, the first component 21 and the second component 22 can be capacitors or resistors. In this embodiment, the first component 21 and the second component 22 are alternating current (AC) coupling capacitors.
In a first coupling mode, the control chip 3 is electrically connected to the first conducting portions 25A, 25B and generates a pair of high-speed differential signals S3, S4. The high-speed signals S3, S4 are transmitted to the third conducting portions 27A, 27B through a pair of transmission lines (not labeled), the first conducting portions 25A, 25B, and the connecting portions 29A, 29B. The electronic device 4 is electrically connected to the second conducting portions 26A, 26B. Two ends of the first component 21 are electrically connected to the second conducting portion 26A and the third conducting portion 27A respectively. Two ends of the second component 22 are electrically connected to the second conducting portion 26B and third conducting portion 27B respectively. The high-speed signals S3, S4 are transmitted to the electronic device 4, passing through the first conducting portions 25A, 25B, the connecting portions 29A, 29B, the third conducting portions 27A, 27B, the first component 21, the second component 22, and the second conducting portions 26A, 26B.
Referring to FIG. 2, in a second coupling mode, the electronic device 4 is electrically connected to the fourth conducting portions 28A, 28B. Two ends of the first component 21 are electrically connected to the third conducting portion 27A and the fourth conducting portion 28A respectively. Two ends of the second component 22 are electrically connected to the third conducting portion 27B and the fourth conducting portion 28B respectively. The control chip 3 remains electrically connected to the first conducting portions 25A, 25B. The high-speed signals S3, S4 are transmitted to the electronic device 4, passing through the first conducting portions 25A, 25B, the connecting portions 29A, 29B, the third conducting portions 27A, 27B, the first component 21, the second component 22, and the fourth conducting portions 28A, 28B.
Referring to FIGS. 3A and 3B, a layout method of a PCB 2 includes the following steps.
In step S01, providing a PCB 2 with a first layout layer 24, and a second layout layer 23.
In step S02, a pair of first conducting portions 25A, 25B is positioned on the first layout layer 24 of the PCB 2 to electrically connected to a control chip.
In step S03, a pair of second conducting portions 26A, 26B, a pair of third conducting portions 27A, 27B, and a pair fourth conducting portions 28A, 28B are positioned on a second layout layer 23 of the PCB 2 in corresponding linear alignments.
In step S04, a pair of connecting portions 29A, 29B is electrically connected to the third conducting portions 27A, 27B and the first conducting portions 25A, 25B.
In step S05, in a first coupling mode, an electronic device 4 is electrically connected to the second conducting portions 26A, 26B, a first component 21 electrically connects the second conducting portion 26A to the third conducting portion 27A, and a second component 22 electrically connects the second conducting portion 26B to the third conducting portion 27B.
In step S06, in a second coupling mode, the electronic device 4 is electrically connected to the fourth conducting portions 28A, 28B, the first component 21 electrically connects the third conducting portion 27A to the fourth conducting portion 28A, and the second component 22 electrically connects the third conducting portion 27B to the fourth conducting portion 28B.
The PCB 2 layout allows the first component 21, the second component 22, and the electronic device 4 to be arranged in two different coupling modes. In this way, it is unnecessary for the PCB 2 to bear additional components to satisfy two alternative coupling positions.
Even though numerous characteristics and advantages of the disclosure have been set forth in the foregoing description, together with details of the structure and function of the disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in the matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.

Claims

1. A printed circuit board (PCB), comprising:

a first layout layer and a second layout layer;

a control chip;

a pair of first conducting portions positioned on the first layout layer and electrically connected to the control chip; and

a pair of second conducing portions, a pair of third conducting portions, and a pair of fourth conducting portions positioned on the second layout layer;

a pair of connecting portions electrically connecting the first conducting portions of the first layout layer to the third conducting portions of the second layout layer; and

a first component and a second component;

wherein in response to an electronic device being electrically connected to the second conducting portions, the first component electrically connecting one of the second conducting portions to a corresponding one of the third conducting portions, and the second component electrically connecting the other one of the second conducting portions to the other one of the third conducting portions, such that a pair of high-speed differential signals generated by the control chip is transmitted to the electronic device, through the first conducting portions, the connecting portions, the third conducting portions, the first and second components, and the second conducting portions in turn; and

wherein in response to the electronic device being electrically connected to the fourth conducting portions, the first component electrically connecting one of the fourth conducting portions to a corresponding one of the third conducting portions, and the second component electrically connecting the other one of the fourth conducting portions to the other one of the third conducting portions, such that the pair of high-speed differential signals is transmitted to the electronic device, through the first conducting portions, the connecting portions, the third conducting portions, the first and second components, and the fourth conducting portions in turn.

2. The PCB of claim 1, wherein the connecting portions are a pair of vias.

3. The PCB of claim 1, wherein the connecting portions are a pair of embedded vias.

4. The PCB of claim 1, wherein the first component and the second component are resistors.

5. The PCB of claim 1, wherein the first component and the second component are capacitors.

6. The PCB of claim 5, wherein each capacitor is an alternating current coupling capacitor.

7. The PCB of claim 1, wherein the pair of second conducting portions, the pair of third conducting portions and the pair of fourth conducting portions are arranged on the second layout layer in corresponding linear alignments.

8. A printed circuit board (PCB) layout method, comprising:

providing a PCB comprising a first layout layer and a second layout layer;

positioning a pair of first conducting portions on the first layout layer to electrically couple to a control chip;

positioning a pair of second conducting portions, a pair of third conducting portions, and a pair of fourth conducting portions on the second layout layer;

providing a pair of connecting portions to electrically connect the first conducting portions of the first layout layer to the third conducting portions of the second layout layer;

electrically connecting an electronic device to the second conducting portions, and providing a first component to electrically connect one of the second conducting portions to a corresponding one of the third conducting portions, and a second component to electrically connect the other one of the second conducting portions to the other one of the third conducting portions to form a first route; or electrically connecting the electronic device to the fourth conducting portions, and providing the first component to electrically connect one of the fourth conducting portions to a corresponding one of the third conducting portions, and the second component to electrically connect the other one of the fourth conducting portions to the other one of the third conducting portions to form a second route; and

transmitting a pair of high-speed differential signals generated by the control chip to the electronic device, through the first conducting portions, the connecting portions, the third conducting portions, the first and second components, and the second conducting portions in turn in response to the first route being formed, or through the first conducting portions, the connecting portions, the third conducting portions, the first and second components, and the fourth conducting portions in turn in response to the second route being formed.

9. The method of claim 8, wherein the connecting portions are a pair of vias.

10. The method of claim 8, wherein the connecting portions are a pair of embedded vias.

11. The method of claim 8, wherein each of the first component and the second component is a resistor.

12. The method of claim 8, wherein each of the first component and the second component is a capacitor.

13. The method of claim 12, wherein each capacitor is an alternating current coupling capacitor.

14. The method of claim 8, wherein in the positioning a pair of second conducting portions, a pair of third conducting portions, and a pair of fourth conducting portions on the second layout layer step, the pair of second conducting portions, the pair of third conducting portions and the pair of fourth conducting portions are arranged on the second layout layer in corresponding linear alignments.