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US20110154658A1 - Circuit substrate and manufacturing method thereof - Google Patents

Circuit substrate and manufacturing method thereof Download PDF

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Publication number
US20110154658A1
US20110154658A1 US12/979,334 US97933410A US2011154658A1 US 20110154658 A1 US20110154658 A1 US 20110154658A1 US 97933410 A US97933410 A US 97933410A US 2011154658 A1 US2011154658 A1 US 2011154658A1
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United States
Prior art keywords
layers
layer
conductive
patterned
insulating
Prior art date
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Abandoned
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US12/979,334
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English (en)
Inventor
Chih-Hong Chuang
Tzu-Wei Huang
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Subtron Technology Co Ltd
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Subtron Technology Co Ltd
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Filing date
Publication date
Application filed by Subtron Technology Co Ltd filed Critical Subtron Technology Co Ltd
Assigned to SUBTRON TECHNOLOGY CO. LTD. reassignment SUBTRON TECHNOLOGY CO. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHUANG, CHIH-HONG, HUANG, TZU-WEI
Publication of US20110154658A1 publication Critical patent/US20110154658A1/en
Priority to US13/552,654 priority Critical patent/US9603263B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0228—Cutting, sawing, milling or shearing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1536—Temporarily stacked PCBs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Definitions

  • Taiwan application serial no. 98145638 filed on Dec. 29, 2009
  • Taiwan application serial no. 99112313 filed on Apr. 20, 2010,
  • Taiwan application serial no. 99141954 filed on Dec. 2, 2010.
  • the entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of specification.
  • the invention relates to a circuit substrate and a manufacturing method thereof. Particularly, the invention relates to a coreless circuit substrate and a manufacturing method thereof.
  • a chip package carrier is one of commonly used packaging components.
  • the chip package carrier is, for example, a multi-layer circuit board, which is mainly formed by alternately stacking multiple circuit layers and a multiple dielectric layers, where the dielectric layer is disposed between any two adjacent circuit layers, and the circuit layers can be electrically connected to each other through plating through holes (PTHs) or conductive vias passing through the dielectric layers.
  • PTHs plating through holes
  • conductive vias passing through the dielectric layers. Since the chip package carrier has advantages of fine circuit layout, compact assembly, and good performance, it becomes a mainstream of chip package structures.
  • a circuit structure of the multi-layer circuit board is fabricated according to a build up method or a laminated method, so as to achieve features of high circuit density and small wiring space. Since a super-thin substrate has inadequate rigidity, a substrate with a certain thickness has to be first provided to serve as a support carrier. Then, a large amount of adhesives is coated and multiple circuit layers and multiple dielectric layers are alternately arranged on two opposite surfaces of the substrate. Then, the adhesive is removed to separate the circuit layers, the dielectric layers from the substrate, so as to form two multi-layer circuit boards separated to each other.
  • a blind hole is first formed to expose the circuit layer under the dielectric layer. Then, a copper layer is electroplated in the blind hole and on the dielectric layer through an electroplating method, so as to form another circuit layer and the PTH or the conductive via.
  • the substrate with a certain thickness hast to be provided to serve as the support carrier of a copper foil layer according to the conventional technique, if a material of the substrate is a metal material, material cost thereof is relatively high, so that manufacturing cost of the multi-layer circuit board is increased. Moreover, a large amount of adhesive is required for fixing the copper foil layer and the substrate, so that the adhesive is hard to be removed, and a production yield cannot be improved.
  • the circuit layer formed through electroplating copper thickness evenness thereof is poor, so that when the required thickness of the circuit layer is relatively thin, a thinning process (for example, an etching process) is required to reduce the thickness of the circuit layer. Therefore, not only the manufacturing steps of the multi-layer circuit board are increased, the production yield of the multi-layer circuit board is also reduced.
  • the invention is directed to a circuit substrate and a manufacturing method thereof, which can reduce manufacturing steps and production cost, and improve production yield to improve reliability of products.
  • the invention provides a manufacturing method of a circuit substrate, which includes following steps. Peripheries of two metal layers are bonded to form a sealed area. At least a through hole passing through the sealed area is formed. Two insulating layers are formed on the two metal layers. Two conductive layers are formed on the two insulating layers. The two insulating layers and the two conductive layers are laminated to the two metal layers, where the two metal layers bonded to each other are embedded between the two insulating layers, and the two insulating layers are filled into the through hole. The sealed area of the two metal layers is separated to form two separated circuit substrates.
  • a method of bonding the peripheries of the two metal layers includes welding, spot welding or using an adhesive, where a material of the adhesive includes cyanoacrylate ester or polypropylene resin.
  • the manufacturing method of the circuit substrate further includes following steps. After the two insulating layers and the two conductive layers are laminated to the two metal layers, a part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. After the sealed area of the two metal layers is separated, the conductive material, the metal layer and the conductive layer are patterned.
  • the manufacturing method of the circuit substrate further includes following steps. After the two insulating layers and the two conductive layers are laminated to the two metal layers, a part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers.
  • the two conductive layers are thinned.
  • Two electroplating seed layers are formed on the two thinned conductive layers and in the blind holes.
  • the metal layer is exposed.
  • a patterned photoresist layer is formed on the electroplating seed layer and the exposed metal layer, respectively.
  • the patterned photoresist layers are taken as a mask to electroplate the electroplating seed layers.
  • the patterned photoresist layers and a part of the electroplating seed layers covered by the patterned photoresist layers are removed.
  • the manufacturing method of the circuit substrate further includes following steps. After the two insulating layers and the two conductive layers are laminated to the two metal layers, the two conductive layers are patterned to form two patterned conductive layers. Two other insulating layers are formed on the two patterned conductive layers, and two other conductive layers are formed on the two other insulating layers. The insulating layers and the two other conductive layers are laminated, and the two patterned conductive layers are embedded in the insulating layers. After the sealed area of the two metal layers is separated, a part of the insulating layers, a part of the metal layer and a part of the other conductive layer are removed to form a plurality of blind holes exposing the patterned conductive layer. A conductive material is formed in the blind holes, and on the remained metal layer and the other conductive layer. The conductive material, the metal layer and the other conductive layer are patterned.
  • the manufacturing method of the circuit substrate further includes following steps. After the two insulating layers and the two conductive layers are laminated to the two metal layers, the two conductive layers are patterned to form two patterned conductive layers. Two other insulating layers are formed on the two patterned conductive layers, and two other conductive layers are formed on the two other insulating layers. The insulating layers and the two other conductive layers are laminated, and the two patterned conductive layers are embedded in the insulating layers. After the sealed area of the two metal layers is separated, a part of the insulating layers, a part of the metal layer and a part of the other conductive layer are removed to form a plurality of blind holes exposing the patterned conductive layer.
  • the other conductive layer and the metal layer are removed to expose the insulating layers.
  • Two electroplating seed layers are formed on the insulating layers and in the blind holes.
  • Two patterned photoresist layers are formed on the two electroplating seed layers.
  • the patterned photoresist layers are taken as a mask to electroplate the electroplating seed layers.
  • the patterned photoresist layers and a part of the electroplating seed layers covered by the patterned photoresist layers are removed.
  • the manufacturing method of the circuit substrate further includes following steps. After the two insulating layers and the two conductive layers are laminated to the two metal layers, a part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of first blind holes exposing the two metal layers. The two conductive layers are removed to expose the two insulating layers. Two electroplating seed layers are formed on the two insulating layers and in the first blind holes. Two patterned photoresist layers are formed on the electroplating seed layers. The patterned photoresist layers are taken as a mask to electroplate the electroplating seed layers.
  • the patterned photoresist layers and a part of the electroplating seed layers covered by the patterned photoresist layers are removed to form two patterned conductive layers and a plurality of conductive through hole structures on the two insulating layers.
  • Two other insulating layers are formed on the two patterned conductive layers, and two other conductive layers are formed on the two other insulating layers.
  • the insulating layers and the two other conductive layers are laminated, and the two patterned conductive layers are embedded in the insulating layers. After the sealed area of the two metal layers is separated, a part of the insulating layers, the metal layer and the other conductive layer are removed to form a plurality of second blind holes exposing the patterned conductive layer.
  • Two other electroplating seed layers are formed on the two other insulating layers, one ends of the first blind holes and in the second blind holes.
  • Two other patterned photoresist layers are formed on the two other electroplating seed layers.
  • the two other patterned photoresist layers are taken as a mask to electroplate the two other electroplating seed layers.
  • the two other patterned photoresist layers and a part of the two other electroplating seed layers covered by the two other patterned photoresist layers are removed.
  • the two metal layers respectively includes a first copper foil layer and a second copper foil layer, and a thickness of each of the second copper foil layers is substantially greater than a thickness of each of the first copper foil layers.
  • the second copper foil layers are bonded to each other.
  • the manufacturing method of the circuit substrate further includes following steps. After the two insulating layers and the two conductive layers are laminated to the two metal layers, the two conductive layers are patterned to from a first patterned conductive layer and a second patterned conductive layer. A plurality of first through holes extending from the first patterned conductive layer to the second patterned conductive layer is formed. After the sealed area of the two metal layers is separated, the second copper foil layer is removed. A first insulating layer is formed on the first patterned conductive layer, and a first conductive layer is formed on the first insulating layer. The first insulating layer and the first conductive layer are laminated, and the first patterned conductive layer is embedded in the insulating layer and the first insulating layer.
  • a part of the insulating layer, the first insulating layer, a part of the first copper foil layer and a part of the first conductive layer are removed to form a plurality of first blind holes exposing the first patterned conductive layer.
  • An electroplating seed layer is formed on the remained first copper foil layer and in the first blind holes and on the remained first conductive layer and in the first blind holes, respectively.
  • Two patterned photoresist layers are formed on the electroplating seed layers.
  • the patterned photoresist layers are taken as a mask to electroplate the electroplating seed layers to form a plurality of conductive blind hole structures in the first blind holes.
  • the patterned photoresist layers and a part of the electroplating seed layers covered by the patterned photoresist layers are removed.
  • the first insulating layer is formed on the first patterned conductive layer and the first conductive layer is formed on the first insulating layer after the sealed area of the two metal layers is separated.
  • the first insulating layer is formed on the first patterned conductive layer and the first conductive layer is formed on the first insulating layer before the sealed area of the two metal layers is separated.
  • the manufacturing method of the circuit substrate further includes following steps.
  • a second insulating layer is formed on the second patterned conductive layer and a second conductive layer is formed on the second insulating layer.
  • the manufacturing method of the circuit substrate further includes following steps. After the patterned photoresist layers and a part of the electroplating seed layers covered by the patterned photoresist layers are removed, a first passivation layer is formed on the first insulating layer, and a second passivation layer is formed on the insulating layer, where the first passivation layer and the second passivation layer cover the conductive blind hole structures. A grinding process is performed to remove a part of the first passivation layer and a part of the second passivation layer to expose the conductive blind hole structures. The remained first passivation layer and the remained second passivation layer are removed.
  • the manufacturing method of the circuit substrate further includes following steps. After the patterned photoresist layers and a part of the electroplating seed layers covered by the patterned photoresist layers are removed, a first solder mask layer is formed on the first insulating layer, and a second solder mask layer is formed on the insulating layer, where the first solder mask layer has a plurality of first openings, and the second solder mask layer has a plurality of second openings, and the first openings and the second openings expose a part of the conductive blind hole structure.
  • the invention provides a circuit substrate including a patterned metal layer, a patterned conductive layer, an insulating layer and a conductive material.
  • the insulating layer is located between the patterned metal layer and the patterned conductive layer.
  • the conductive material is filled in a plurality of blind holes, where the blind holes pass through the insulating layer, and the conductive material is electrically connected to the patterned metal layer and the patterned conductive layer.
  • the invention provides a circuit substrate including a patterned metal layer, a first patterned conductive layer, a second patterned conductive layer, two insulating layers and a conductive material.
  • the second partnered conductive layer is located between the patterned metal layer and the first patterned conductive layer.
  • the insulating layers are respectively located between the patterned metal layer and the second patterned conductive layer and between the first patterned conductive layer and the second patterned conductive layer.
  • the conductive material is filled in a plurality of blind holes, where the blind holes pass through the insulating layers, and the conductive material is electrically connected between the patterned metal layer and the second patterned conductive layer and between the first patterned conductive layer and the second patterned conductive layer.
  • the peripheries of two metal layers are first bonded to form a sealed area. After lamination of two insulating layers and two conductive layers is completed, the two metal layers are separated. Therefore, compared to the conventional technique, the manufacturing method of the circuit substrate of the invention does not require a metal substrate to serve as a support carrier, namely, a coreless circuit substrate structure is achieved, which may effectively reduce the manufacturing cost of the circuit substrate and improve reliability thereof, and effectively reduce a time required for manufacturing the circuit substrate.
  • FIG. 1A to FIG. 1H are cross-sectional views illustrating a manufacturing method of a circuit substrate according to an embodiment of the invention.
  • FIG. 1A to FIG. 1E and FIG. 1 F′ to FIG. 1 J′ are cross-sectional views illustrating a manufacturing method of a circuit substrate according to another embodiment of the invention.
  • FIG. 2A to FIG. 2I are cross-sectional views illustrating a manufacturing method of a circuit substrate according to another embodiment of the invention.
  • FIG. 2A to FIG. 2G and FIG. 2 H′ to FIG. 2 K′ are cross-sectional views illustrating a manufacturing method of a circuit substrate according to another embodiment of the invention.
  • FIG. 2A to FIG. 2C and FIG. 2 D′′ to FIG. 2 M′′ are cross-sectional views illustrating a manufacturing method of a circuit substrate according to another embodiment of the invention.
  • FIG. 3A to FIG. 3P are cross-sectional views illustrating a manufacturing method of a circuit substrate according to another embodiment of the invention.
  • FIG. 4A and FIG. 4B are cross-sectional views illustrating a manufacturing method of a circuit substrate according to another embodiment of the invention.
  • FIG. 1A to FIG. 1H are cross-sectional views illustrating a manufacturing method of a circuit substrate according to an embodiment of the invention.
  • the manufacturing method of the circuit substrate can be described as follow.
  • two metal layers 102 are provided, where the two metal layers 102 are, for example, copper foils or other metal foils, and peripheries of the two metal layers 102 are bonded to form a sealed area 104 .
  • a method of bonding the peripheries of the two metal layers 102 includes welding or spot welding, so that the two metal layers 102 are temporarily bonded to avoid reagents used in follow-up processes from infiltrating there between.
  • an adhesive can also be used to temporarily bond the peripheries of the two metal layers 102 , where a material of the adhesive includes cyanoacrylate ester or polypropylene resin, or other adhesives. It should be noticed that the metal layers 102 can be regarded as a coreless structure layer.
  • a through hole H passing through the sealed area 104 is formed (only two through holes are schematically illustrated in FIG. 1B ).
  • a method of forming the through holes H includes laser drilling or mechanical drilling. Since a diameter of the through hole H is smaller than a size of the sealed area 104 , tightness of the sealed area 104 is not spoiled by theses through holes H.
  • two insulating layers 112 are formed on the metal layers 102 , and two conductive layers 122 are formed on the insulating layers 112 , and then the insulating layers 112 and the conductive layers 122 are laminated, so that the metal layers 102 bonded to each other are embedded between the insulating layers 112 . Meanwhile, the insulating layers 112 are filled into the through holes H of the sealed area 104 during the lamination. Since sizes of the insulating layers 112 are greater than sizes of the metal layers 102 , the metal layers 102 can be entirely encapsulated in the insulating layers 112 without being contaminated by external impurities or reagents.
  • a part of the insulating layers 112 and a part of the conductive layers 122 are removed to form a plurality of blind holes V exposing the metal layers 102 .
  • a method of forming the blind holes V includes laser drilling, and a method of removing the conductive layers 122 includes laser etching or photolithography etching, etc.
  • a conductive material 124 is formed in the blind holes V and on the remained conductive layers 122 , where a method of forming the conductive material 124 includes electroplating, and the conductive material 124 is, for example, copper or other metals. It should be noticed that since the metal layers 102 can be entirely encapsulated in the insulating layers 112 without being contaminated by external impurities or reagents, when the conductive material 124 is formed in the blind holes V and on the remained conductive layers 122 through electroplating, the original size and thickness of the metal layers 102 embedded in the insulating layers 112 are not influenced.
  • the sealed area 104 of the metal layers 102 is separated to form two separated circuit substrates 100 a ′.
  • a forming machine or other tools can be used to remove the sealed area 104 encapsulated the metal layers 102 while taking the through holes H as reference points, so as to totally separate the metal layers 102 .
  • the method of separating the metal layers 102 is not limited to the above method.
  • each of the circuit substrates 100 a includes a patterned metal layer 102 , a patterned conductive layer 122 , an insulating layer 112 and a conductive material 124 , where the insulating layer 112 is located between the patterned metal layer 102 and the patterned conductive layer 122 .
  • the conductive material 124 is located in the blind holes V, where the blind holes V pass through the insulating layer 112 , so that the conductive material 124 is electrically connected to the patterned metal layer 102 and the patterned conductive layer 122 . Now, fabrication of the coreless circuit substrate 100 a is completed.
  • FIG. 1A to FIG. 1E and FIG. 1 F′ to FIG. 1 J′ are cross-sectional views illustrating a manufacturing method of a circuit substrate according to another embodiment of the invention.
  • the manufacturing method of the circuit substrate 100 b of the present embodiment is similar to the manufacturing method of the circuit substrate 100 a, and differences there between are as follows.
  • FIG. 1E namely, a part of the insulating layers 112 and a part of the conductive layers 122 are removed to form a plurality of the blind holes V exposing the metal layers 102 , referring to FIG. 1E and FIG.
  • the conductive layers 122 are thinned to form a plurality of conductive layers 122 ′, and two electroplating seed layers 132 are formed on the conductive layers 122 ′ and in the blind holes V, where the electroplating seed layers 132 totally encapsulate the conductive layers 122 ′ and inner walls of the blind holes V and a part of the metal layers 102 .
  • the sealed area 104 of the metal layers 102 is separated to expose the metal layer 102 .
  • a patterned photoresist layer 134 is formed on the electroplating layer 132 and the exposed metal layer 102 , respectively.
  • FIG. 1 F′ the conductive layers 122 are thinned to form a plurality of conductive layers 122 ′, and two electroplating seed layers 132 are formed on the conductive layers 122 ′ and in the blind holes V, where the electroplating seed layers 132 totally encapsulate the conductive layers 122 ′ and inner walls of the blind holes V and a part of the metal layers 102
  • the patterned photoresist layers 134 are taken as a mask to electroplate the electroplating seed layer 132 and the metal layer 102 to form a conductive material 124 ′.
  • the patterned photoresist layers 134 and a part of the electroplating seed layer 132 covered by the patterned photoresist layers 134 and a part of the metal layer 102 covered by the patterned photoresist layers 134 are removed to expose a part of an upper surface 112 a and a part of a lower surface 112 b of the insulating layer 112 , so as to form a first patterned conductive material layer 124 a, a second patterned conductive material layer 124 b and a conductive blind hole structure 124 c, where the conductive blind hole structure 124 c is electrically connected to the first patterned conductive material layer 124 a and the second patterned conductive material layer 124 b.
  • circuit substrates 100 a and 100 b of two layers are formed, though in another embodiment, the circuit substrates 100 a and 100 b of two layers can be used as core layers to sequentially fabricate circuit substrates of four layers, six layers or more than six layers, and manufacturing methods thereof are the same to the manufacturing method of the general circuit substrate, which are not repeated herein. Moreover, in order to manufacture the circuit substrates of odd-numbered layers, the invention provides another manufacturing method of the circuit substrate.
  • FIG. 2A to FIG. 2I are cross-sectional views illustrating a manufacturing method of a circuit substrate according to another embodiment of the invention.
  • two metal layers 202 are provided, which are, for example, copper foils or other metal foils, and the peripheries of the metal layers 202 are bonded to form a sealed area 204 , where a method of bonding the peripheries of the metal layers 202 includes welding or spot welding, so that the metal layers 202 are temporarily bonded to avoid reagents used in follow-up processes from infiltrating there between.
  • an adhesive can also be used to temporarily bond the peripheries of the metal layers 202 , where a material of the adhesive includes cyanoacrylate ester or polypropylene resin, or other adhesives. It should be noticed that the metal layers 202 can be regarded as a coreless structure layer.
  • a method of forming the through holes H includes laser drilling or mechanical drilling.
  • two insulating layers 212 are formed on the metal layers 202 , and two conductive layers 222 are formed on the insulating layers 212 .
  • the two conductive layers 222 can be patterned to form two patterned conductive layers 222 a in case that the metal layers 202 are in the sealed state.
  • two other insulating layers 232 are formed on the patterned conductive layers 222 a, and two other conductive layers 242 are formed on the insulating layers 232 .
  • the insulating layers 212 and the conductive layers 222 are laminated, so that the metal layers 202 bonded to each other are embedded in the insulating layers 212 .
  • FIG. 2C the insulating layers 212 and the conductive layers 222 are laminated, so that the metal layers 202 bonded to each other are embedded in the insulating layers 212 .
  • FIG. 1 the metal layers 202 bonded to each other are embedded in the insulating layers 212 .
  • the insulating layers 232 and 212 and the conductive layers 242 are laminated, so that the patterned conductive layers 222 a are embedded in the insulating layers 232 and 212 . Meanwhile, when the insulating layers 212 are laminated, the insulating layers 212 can be filled in the through holes H of the sealed area 204 . Since sizes of the insulating layers 212 are greater than sizes of the metal layers 202 , the metal layers 202 can be totally encapsulated in the insulating layers 212 without being contaminated by external impurities or reagents.
  • the sealed area 204 of the two metal layers 202 is separated to form two separated circuit substrates 200 a ′.
  • the circuit substrates 200 a ′ respectively have three layers of circuit.
  • a forming machine or other tools can be used to remove the sealed area 204 encapsulating the metal layers 202 while taking the through holes H (referring to FIG. 2E ) as reference points, so as to totally separate the metal layers 202 .
  • the method of separating the metal layers 202 is not limited to the above method.
  • FIG. 2G in which only one circuit substrate 200 a ′ is illustrated.
  • a part of the insulating layers 212 and 232 , a part of the metal layer 202 and a part of the conductive layer 242 are removed to form a plurality of blind holes V exposing the patterned conductive layer 222 a, where a method of forming the blind holes V includes laser drilling.
  • a conductive material 224 is formed in the blind holes V, and on the remained metal layer 202 and the conductive layer 242 , where a method of forming the conductive material 244 includes electroplating, and the conductive material 244 is, for example, copper or other metals.
  • the patterned conductive material 244 , the metal layer 202 and the conductive layer 242 are patterned to form required circuits on the respective circuit substrate 200 a ′, so as to complete fabricating the circuit substrate 200 a.
  • the circuit substrate 200 a ′ having three layers of circuit shown in FIG. 2I includes a patterned metal layer 202 , a patterned conductive layer 242 , a patterned conductive layer 222 a, two insulating layers 212 and 232 , and a conductive material 244 .
  • the patterned conductive layer 222 a is located between the patterned metal layer 202 and the patterned conductive layer 242 .
  • the insulating layers 212 and 232 are respectively located between the patterned metal layer 202 and the patterned conductive layer 222 a and between the patterned conductive layer 242 and the patterned conductive layer 222 a.
  • the conductive material 244 is located in the blind holes V, and the blind holes V pass through the insulating layers 212 and 232 , so that the conductive material 244 is electrically connected between the patterned metal layer 202 and the patterned conductive layer 222 a, and between the patterned, conductive layer 242 and the patterned conductive layer 222 a.
  • FIG. 2A to FIG. 2G and FIG. 2 H′ to FIG. 2 K′ are cross-sectional views illustrating a manufacturing method of a circuit substrate according to another embodiment of the invention.
  • the manufacturing method of the circuit substrate 200 b of the present embodiment is similar to the manufacturing method of the circuit substrate 200 a, and differences there between are as follows.
  • a part of the insulating layers 212 and 232 a part of the metal layer 202 and a part of the conductive layer 242 are removed to form a plurality of the blind holes V exposing the patterned conductive layer 222 a, referring to FIG.
  • the conductive layer 242 and the metal layer 202 are removed to expose the insulating layers 232 and 212 , and two electroplating seed layers 252 are formed on the insulating layers 212 and 232 and in the blind holes V.
  • two patterned photoresist layers 254 are formed on the electroplating seed layers. 252 .
  • the patterned photoresist layers 254 are taken as a mask to electroplate the electroplating seed layers 252 to form a conductive material 244 ′.
  • the patterned photoresist layers 254 and a part of the electroplating seed layers 252 covered by the patterned photoresist layers 254 are removed to expose a part of an upper surface 232 a of the insulating layer 232 and a part of a lower surface 212 b of the insulating layer 212 , so as to form a first patterned conductive material layer 244 a, a second patterned conductive material layer 244 b and a plurality of conductive blind hole structures 244 c, where the blind hole structures 244 c are electrically connected between the first patterned conductive material layer 244 a and the patterned conductive layer 222 a and between the patterned conductive layer 222 a and the second patterned conductive layer 244 b.
  • fabrication of the circuit substrate 200 b is completed.
  • FIG. 2A to FIG. 2C and FIG. 2 D′′ to FIG. 2 M′′ are cross-sectional views illustrating a manufacturing method of a circuit substrate according to another embodiment of the invention.
  • the manufacturing method of the circuit substrate 200 c of the present embodiment is similar to the manufacturing method of the circuit substrate 200 a, and differences there between are as follows.
  • FIG. 2C After the step of FIG. 2C , namely, after the insulating layers 212 and the conductive layers 222 are laminated to the metal layers 202 , referring to FIG. 2 D′′, a part of the insulating layers 212 and a part of the conductive layers 222 are removed to form a plurality of first blind holes V 1 exposing the metal layers 202 .
  • FIG. 2 D′′ a part of the insulating layers 212 and a part of the conductive layers 222 are removed to form a plurality of first blind holes V 1 exposing the metal layers 202 .
  • the conductive layers 222 are removed to expose the insulating layers 212 , and two electroplating seed layers 252 are formed on the insulating layers 212 and in the first blind holes V 1 .
  • two patterned photoresist layers 254 are formed on the electroplating seed layers 252 .
  • the patterned photoresist layers 254 are taken as a mask to electroplate the electroplating seed layers 252 to form a conductive material 246 .
  • FIG. 2 E′′ the conductive layers 222 are removed to expose the insulating layers 212 , and two electroplating seed layers 252 are formed on the insulating layers 212 and in the first blind holes V 1 .
  • two patterned photoresist layers 254 are formed on the electroplating seed layers 252 .
  • the patterned photoresist layers 254 are taken as a mask to electroplate the electroplating seed layers 252 to form a conductive material 246 .
  • the patterned photoresist layers 254 and a part of the electroplating seed layers 252 covered by the patterned photoresist layers 254 are removed to form two patterned conductive material layers 246 a and a plurality of conductive through hole structures 246 b on the electroplating seed layers 252 .
  • FIG. 2 I′′ two other insulating layers 234 are formed on the patterned conductive layers 246 a, and two other conductive layers 248 are formed on the insulating layers 234 . Then, the insulating layers 234 and the conductive layers 248 are laminated, and the patterned conductive layers 246 a are embedded in the insulating layers 212 and 234 . Then, referring to FIG. 2 J′′, the sealed area 204 of the metal layers 202 is separated to form two separated circuit substrates 200 c ′. It should be noticed that, in FIG. 2 J′′, only one of the circuit substrates 200 c ′ is illustrated. Then, referring to FIG.
  • a part of the insulating layers 234 , the metal layer 202 and the conductive layer 248 are removed to form a plurality of second blind holes V 2 exposing the patterned conductive layer 246 a.
  • two other electroplating seed layers 256 are formed on the insulating layers 212 and 234 , one ends of the first blind holes V 1 and in the second blind holes V 2 .
  • two other patterned photoresist layers 258 are formed on the electroplating seed layers 256 , and the patterned photoresist layers 258 are taken as a mask to electroplate the electroplating seed layers 256 to form a conductive material 249 .
  • the patterned photoresist layers 258 and a part of the electroplating seed layers 256 covered by the patterned photoresist layers 258 are removed to from two patterned conductive material layer 249 a and a plurality of conductive through hole structures 249 b on the insulating layers 212 and 234 .
  • the conductive through hole structures 246 b and 249 b are electrically connected to the patterned conductive layer 246 a and the patterned conductive material layers 249 a.
  • circuit substrates 200 a, 200 b and 200 c of three layers of circuit are formed, though other embodiments that are not illustrated, the circuit substrates 200 a, 200 b and 200 c of three layers of circuit can be used as core layers to sequentially fabricate circuit substrates of five layers, seven layers or more than seven layers, and manufacturing methods thereof are the same to the manufacturing method of the general circuit substrate, which can be implemented by those skilled in the art with reference of the aforementioned embodiments by using the aforementioned components according to actual design requirements, so that detailed descriptions thereof are not repeated.
  • the odd-numbered layers of the circuits and the even-numbered layers of the circuits can all be fabricated according to the manufacturing methods of the above circuit substrates 100 a, 100 b, 200 a, 200 b and 200 c, so that not only the circuit substrates 100 a, 100 b, 200 a, 200 b and 200 c can be manufactured within the same manufacturing time to speed manufacture of the multi-layer circuit substrate, a problem of warping of the circuit substrates 100 a, 100 b, 200 a, 200 b and 200 c can also be avoided.
  • the manufacturing methods of the circuit substrates 100 a, 100 b, 200 a, 200 b and 200 c do not require a metal substrate to serve as a support carrier, namely, a coreless circuit substrate is achieved, which may effectively reduce the manufacturing cost of the circuit substrates 100 a, 100 b, 200 a, 200 b and 200 c and improve reliability thereof, and effectively reduce a time required for manufacturing the circuit substrates 100 a, 100 b, 200 a, 200 b and 200 c.
  • patterns of the metal layers 102 and 202 are not limited by the invention, and although the above metal layers 102 and 202 are respectively embodied by a pattern of a single metal layer, in other embodiments, the metal layers 102 and 202 can also be metal layers formed by multiple layers of copper foil layers, which is still belonged to the technical solutions of the invention without departing from a protection scope of the invention.
  • FIG. 3A to FIG. 3P are cross-sectional views illustrating a manufacturing method of a circuit substrate according to another embodiment of the invention.
  • the metal layer 310 ′ is formed by a first copper foil layer 310 a and a second copper foil layer 310 b located on the first copper foil layer 310 a
  • the metal layer 310 ′′ is formed by a third copper foil layer 310 c and a fourth copper foil layer 310 d located on the third copper foil layer 310 c.
  • the second copper foil layer 310 b is partially bonded to the fourth copper foil layer 310 d through an adhesive 320 .
  • the adhesive 320 is located between the second copper foil layer 310 b and the fourth copper foil layer 310 d, and is partially adhered to the second copper foil layer 310 b and the fourth copper foil layer 310 d.
  • the first copper foil layer 310 a and the second copper foil layer 310 b thereon can be regarded as a coreless structure layer.
  • the third copper foil layer 310 c and the fourth copper foil layer 310 d thereon can be regarded as a coreless structure layer.
  • a thickness of the second copper foil layer 310 b is substantially greater than a thickness of the first copper foil layer 310 a, where the thickness of the first copper foil layer 310 a is, for example, 3 ⁇ m, and the thickness of the second copper foil layer 310 b is, for example, 12 ⁇ m.
  • the thickness of the first copper foil layer 310 a is substantially the same to a thickness of the third copper foil layer 310 c, namely, the thickness of the third copper foil layer 310 c is also 3 ⁇ m.
  • the thickness of the second copper foil layer 310 b is substantially the same to a thickness of the fourth copper foil layer 310 d, namely, the thickness of the fourth copper foil layer 310 d is also 12 ⁇ m.
  • the second copper foil layer 310 b can be used to support the first copper foil layer 310 a.
  • the fourth copper foil layer 310 d can be used to support the third copper foil layer 310 c. Therefore, in the present embodiment, it is unnecessary to use a metal substrate to serve as a support carrier as that does of the conventional technique, so that manufacturing cost can be effectively reduced.
  • the adhesive 320 is, for example, cyanoacrylate ester (which is generally referred to as 3 second glue) or polypropylene resin (i.e. PP glue).
  • the adhesive 320 is used to bond the second copper foil layer 310 b and the fourth copper foil layer 310 d
  • the second copper foil layer 310 b and the fourth copper foil layer 310 d can also be bonded by welding copper foil, and now the adhesive 320 is melted copper foil.
  • bonding method is still belonged to a pattern within the scope of the invention.
  • a plurality of first through holes 332 extending from the first copper foil layer 310 a to the third copper foil layer 310 c is formed. Namely, the first through holes 332 at least pass through the first copper foil layer 310 a, the second copper foil layer 310 b, the fourth copper foil layer 310 d and the third copper foil layer 310 c.
  • a method of forming the first through holes 332 includes mechanical drilling.
  • a first insulating layer 350 a and a first conductive layer 342 located on the first insulating layer 350 a are laminated to the first copper foil layer 310 a, and meanwhile a second insulating layer 350 b and a second conductive layer 344 located on the second insulating layer 350 b are laminated to the third copper foil layer 310 c.
  • the first insulating layer 350 a and the second insulating layer 350 b respectively face to the first copper foil layer 310 a and the third copper foil layer 310 c, and during the lamination, a part of the first insulating layer 350 a and a part of the second insulating layer 350 b are filled in the first through holes 332 to fill up the first through holes 332 .
  • a material of the first conductive layer 342 and the second conductive layer 344 is, for example, copper.
  • a thickness of the first insulating layer 350 a plus a thickness of the first conductive layer 342 is greater than the thickness of the first copper foil layer 310 a plus the thickness of the second copper foil layer 310 b.
  • the thickness of the first insulating layer 350 a is, for example, 40 ⁇ m
  • the thickness of the first conductive layer 342 is, for example, 18 ⁇ m.
  • a thickness of the second insulating layer 350 b plus a thickness of the second conductive layer 344 is greater than the thickness of the third copper foil layer 310 c plus the thickness of the fourth copper foil layer 310 d.
  • the thickness of the second insulating layer 350 b is substantially the same to that of the first insulating layer 350 a, which is, for example, 40 ⁇ m, and the thickness of the second conductive layer 344 is substantially the same to that of the first conductive layer 342 , which is, for example, 18 ⁇ m.
  • a plurality of second through holes 334 extending from the first conductive layer 342 to the second conductive layer 344 is formed, where the second through holes 334 at least pass through the first conductive layer 342 , the first insulating layer 350 a, the first copper foil layer 310 a, the second copper foil layer 310 b, the fourth copper foil layer 310 d, the third copper foil layer 310 c, the second insulating layer 350 b and the second conductive layer 344 .
  • the second through holes 334 can be used to assist removing the adhesive 320 in a follow-up process, namely, removing a bonding area of the second copper foil layer 310 b and the fourth copper foil layer 310 d.
  • the first conductive layer 342 and the second conductive layer 344 may respectively have a plurality of metal patterns (not shown), and the metal patterns can serve as reference points for positioning and alignment in follow-up processes. Namely, the metal patterns of the first conductive layer 342 and the second conductive layer 344 can serve as a reference for positioning and aligning the first copper foil layer 310 a and the third copper foil layer 310 c, and can serve as a reference for positioning and aligning a fifth copper foil layer 310 e (shown in FIG. 3G ).
  • the first conductive layer 342 and the second conductive layer 344 are patterned to form a first circuit layer 342 a and a second circuit layer 344 a, where a method for patterning the first conductive layer 342 and the second conductive layer 344 includes a photolithography etching process.
  • the first conductive layer 342 and the second conductive layer 344 are respectively laminated to the first insulating layer 350 a and the second insulating layer 350 b, and are patterned to form the first circuit layer 342 a and the second circuit layer 344 a, compared to the conventional technique of forming a circuit layer through electroplating, the first circuit layer 342 a and the second circuit layer 344 a of the present embodiment has better copper thickness evenness.
  • first copper foil layer 310 a, the second copper foil layer 310 b, the third copper foil layer 310 c and the fourth copper foil layer 310 d of the present embodiment are all embedded in the first insulating layer 350 a and the second insulating layer 350 b due to thermal lamination, when the first conductive layer 342 and the second conductive layer 344 are patterned, contaminations of external impurities and reagents can be avoided, so as to maintain sizes and thickness of the first copper foil layer 310 a, the second copper foil layer 310 b, the third copper foil layer 310 c and the fourth copper foil layer 310 d.
  • the adhesive 320 is removed to form a first circuit substrate 360 a and a second circuit substrate 360 b separated from each other.
  • the second through holes 334 can be used to assist removing the adhesive 320 . Namely, by forming the second through holes 334 , adhesion between the adhesive 320 and the second copper foil layer 310 b and the fourth copper foil layer 310 d can be spoiled, so as to easily remove the adhesive 320 .
  • a method of removing the adhesive 320 is, for example, mechanical drilling or milling treatment.
  • the step of removing the adhesive 320 of the present embodiment is simple and has a low difficulty, so that a production yield can be improved.
  • the first circuit substrate 360 a and the second circuit substrate 360 b formed after the adhesive 320 is removed are symmetric structures.
  • the first circuit substrate 360 a sequentially includes the first circuit layer 342 a, the first insulating layer 350 a, the first copper foil layer 310 a and the second copper foil layer 310 b.
  • the second circuit substrate 360 b sequentially includes the second circuit layer 344 a, the second insulating layer 350 b, the third copper foil layer 310 c and the fourth copper foil layer 310 d.
  • only the first circuit substrate 360 a is taken as an example to describe follow-up fabrication processes of the circuit substrate.
  • the second copper foil layer 310 b is removed, and a third insulating layer 350 c and the fifth copper foil layer 310 e on the third insulating layer 350 c are laminated to the first circuit layer 342 a.
  • a method of removing the second copper foil layer 310 b is, for example, a lift-off method, namely, the lift-off method is used to peel off the second copper foil layer 310 b from the first copper foil layer 310 a.
  • the third insulating layer 350 c and the fifth copper foil layer 310 e are laminated to the first circuit layer 342 a, so that the first circuit layer 342 a is changed to an internal circuit layer.
  • the first circuit layer 342 a is embedded between the third insulating layer 350 c and the first insulating layer 350 a.
  • the fifth copper foil layer 310 e is laminated to the first circuit layer 342 a with a reference of the metal patterns (not shown) on the first circuit layer 342 a (the original first conductive layer 342 ), so as to ensure that the first copper foil layer 310 a, the first circuit layer 342 a and the fifth copper foil layer 310 e have a better alignment accuracy.
  • a thickness of the fifth copper foil layer 310 e is relatively thin, which is, for example, 3 ⁇ m, so that when the fifth copper foil layer 310 e is to be laminated, a copper foil layer with relatively thick thickness (not shown) is generally added on the fifth copper foil layer 310 e first, where the thickness thereof is, for example, 12 ⁇ m, so as to prevent a bending phenomenon of the fifth copper foil layer 310 e after the lamination, and maintain a surface flatness of the fifth copper foil layer 310 e. Then, after the lamination, the copper foil layer with the relatively thick thickness is peeled off, and the fifth copper foil layer 310 e with the relatively thin thickness is remained for follow-up processes.
  • the third insulating layer 350 c and the fifth copper foil layer 310 e located on the third insulating layer 350 c are laminated to the first circuit layer 342 a after the adhesive 320 is removed.
  • a sequence of the steps of laminating the third insulating layer 350 c and the fifth copper foil layer 310 e located thereon and removing the adhesive 320 is not limited by the invention.
  • the third insulating layer 350 c and the fifth copper foil layer 310 e located on the third insulating layer 350 c can be laminated to the first circuit layer 342 a before the adhesive 320 is removed.
  • the third insulating layer 350 c and the fifth copper foil layer 310 e located on the third insulating layer 350 c are first laminated to the first circuit layer 342 a, and meanwhile a fourth insulating layer 350 d and a sixth copper foil layer 310 f located on the fourth insulating layer 350 d are laminated to the second circuit layer 344 a. Then, as shown in FIG. 4B , the adhesive 320 , the second copper foil layer 310 b and the fourth copper foil layer 310 d are removed to form a third circuit substrate 400 c and a fourth circuit substrate 400 d separated from each other.
  • the third circuit substrate 400 c and the fourth circuit substrate 400 d formed after the adhesive 320 , the second copper foil layer 310 b and the fourth copper foil layer 310 d are removed are symmetric structures, where the third circuit substrate 400 c sequentially includes the fifth copper foil layer 310 e, the third insulating layer 350 c, the first circuit layer 342 a, the first insulating layer 350 a and the first copper foil layer 310 a. Similarly, the fourth circuit substrate 400 d sequentially includes the sixth copper foil layer 310 f, the fourth insulating layer 350 d, the second circuit layer 344 a, the second insulating layer 350 b and the third copper foil layer 310 c.
  • sequence of the steps of laminating the insulating layer and the copper foil layer located thereon to the circuit layer and removing the adhesive 320 can be selectively adjusted according to an actual requirement, so that the steps shown in FIG. 3F to FIG. 3G are only used as an example, and the invention is not limited thereto.
  • the fabrication of the first circuit substrate 400 a is completed, where the first circuit substrate 400 a sequentially includes the fifth copper foil layer 310 e, the third insulating layer 350 c, the first circuit layer 342 a, the first insulating layer 350 a and the first copper foil layer 310 a.
  • a drilling process is performed to the fifth copper foil layer 310 e and the first copper foil layer 310 a to form a plurality of first blind holes 412 extending from the fifth copper foil layer 310 e to the first circuit layer 342 a and a plurality of second blind holes 414 extending from the first copper foil layer 310 a to the first circuit layer 342 a, where the first blind holes 412 and the second blind holes 414 expose a part of the first circuit layer 342 a.
  • the drilling process is, for example, the laser drilling, namely, the first blind holes 412 and the second blind holes 414 are formed through laser ablation.
  • a chemical copper layer 420 is formed in the first blind holes 412 and the second blind holes 414 , where the chemical copper layer 420 is connected to the fifth copper foil layer 310 e and the first circuit layer 342 a and connected to the first copper foil layer 310 a and the first circuit layer 342 a.
  • the chemical copper layer 420 covers the fifth copper foil layer 310 e, the first blind holes 412 , the first copper foil layer 310 a and the second blind holes 414 , and the fifth copper foil layer 310 e is electrically connected to the first circuit layer 342 a through the chemical copper layer 420 , and the first copper foil layer 310 a is electrically connected to the first circuit layer 342 a through the chemical copper layer 420 .
  • a method of forming the chemical copper layer 420 includes an electroless plating process.
  • a first patterned dry film photoresist layer 432 is formed on the fifth copper foil layer 310 e, and a second patterned dry film photoresist layer 434 is formed on the first copper foil layer 310 a, where the first patterned dry film photoresist layer 432 at least exposes the first blind holes 412 , and the second patterned dry film photoresist layer 434 at least exposes the second blind holes 414 .
  • the first patterned dry film photoresist layer 432 exposes the chemical copper layer 420 located in the first blind holes 412 and the chemical copper layer 420 located on a part of the fifth copper foil layer 310 e.
  • the second patterned dry film photoresist layer 434 exposes the chemical copper layer 420 located in the second blind holes 414 and the chemical copper layer 420 located on a part of the first copper foil layer 310 a.
  • an electroplating copper layer 440 is formed in at least the first blind holes 412 and the second blind holes 414 , where the electroplating copper layer 440 fills up the first blind holes 412 and the second blind holes 414 , and covers a part of the chemical copper layer 420 .
  • the electroplating copper layer 440 is formed in the first blind holes 412 , the second blind holes 414 and on the chemical copper layers 420 that are not covered by the first patterned dry film photoresist layer 432 and the second patterned dry film photoresist layer 434 through a via filling plating method.
  • the first patterned dry film photoresist layer 432 and a part of the chemical copper layer 420 and a part of the fifth copper foil layer 310 e located under the first patterned dry film photoresist layer 432 are removed, and the second patterned dry film photoresist layer 434 and a part of the chemical copper layer 420 and a part of the first copper foil layer 310 a located under the second patterned dry film photoresist layer 434 are removed, so as to expose a part of the third insulating layer 350 c and a part of the first insulating layer 350 a, and form first conductive blind hole structures 412 a in the first blind holes 412 and form second conductive blind hole structures 414 a in the second blind holes 414 .
  • a method of removing the first patterned dry film photoresist layer 432 and a part of the chemical copper layer 420 and a part of the fifth copper foil layer 310 e located under the first patterned dry film photoresist layer 432 and removing the second patterned dry film photoresist layer 434 and a part of the chemical copper layer 420 and a part of the first copper foil layer 310 a located under the second patterned dry film photoresist layer 434 includes an etching process.
  • the first conductive blind hole structures 412 a and the second conductive blind hole structures 414 a electrically connected to the first circuit layer 342 a are formed.
  • a first passivation layer 452 is formed on the third insulating layer 350 c, and a second passivation layer 454 is formed on the first insulating layer 350 a.
  • the first passivation layer 452 covers the third insulating layer 350 c and the first conductive blind hole structures 412 a exposed on the third insulating layer 350 c for protecting pattern integrity of the first conductive blind hole structures 412 a.
  • the second passivation layer 454 covers the first insulating layer 350 a and the second conductive blind hole structures 414 a exposed on the first insulating layer 350 a for protecting pattern integrity of the second conductive blind hole structures 414 a.
  • a method of forming the first passivation layer 452 and the second passivation layer 454 is, for example, screen printing, and a material of the first passivation layer 452 and the second passivation layer 454 is, for example, ink.
  • a grinding process is performed to remove a part of the first passivation layer 452 to expose surfaces of the first conductive blind hole structures 412 a and remove a part of the second passivation layer 454 to expose surfaces of the second conductive blind hole structures 414 a.
  • a surface of the first passivation layer 452 is substantially aligned to the surfaces of the first conductive blind hole structures 412 a
  • a surface of the second passivation layer 454 is substantially aligned to the surfaces of the second conductive blind hole structures 414 a.
  • the remained first passivation layer 452 and the second passivation layer 454 are removed to expose a part of the third insulating layer 350 c, the first conductive blind hole structures 412 a exposed on the third insulating layer 350 c, a part of the first insulating layer 350 a and the second conductive blind hole structures 414 a exposed on the first insulating layer 350 a.
  • a purpose of the sequential steps of forming the first passivation layer 452 and the second passivation layer 454 , performing the grinding process and removing the first passivation layer 452 and the second passivation layer 454 is to obtain better surface flatness of the surfaces of the first conductive blind hole structures 412 a and the surfaces of the second conductive blind hole structures 414 a, so as to facilitate follow-up processes and a chip packaging process.
  • a first solder mask layer 462 is formed on the third insulating layer 350 c, and a second solder mask layer 464 is formed on the first insulating layer 350 a.
  • the first solder mask layer 462 has a plurality of first openings 462 a, where the first openings 462 a expose a part of the first conductive blind hole structures 412 a, which can be used as bonding pads.
  • the second solder mask layer 464 has a plurality of second openings 464 a, where the second openings 462 a expose a part of the second conductive blind hole structures 414 a, which can be used as bonding pads.
  • the circuit substrate 300 of the present embodiment is adapted to serve as a chip packaging carrier.
  • the manufacturing method of the circuit substrate 300 of the present embodiment can effectively reduce the fabrication cost.
  • the first conductive layer 342 and the second conductive layer 344 are laminated, and are patterned to form the first circuit layer 342 a and the second circuit layer 344 a, compared to the conventional technique of forming a circuit layer through electroplating, the first circuit layer 342 a and the second circuit layer 344 a of the present embodiment has better copper thickness evenness.
  • the first circuit layer 342 a (the original first conductive layer 342 ) is used as a reference for positioning and aligning the first copper foil layer 310 a and the fifth copper foil layer 310 e. In this way, alignment accuracy of the circuit substrate 300 can be effectively improved, so as to achieve better production yield and reliability of the circuit substrate 300 .
  • the peripheries of two metal layers are first bonded to form a sealed area. After lamination of two insulating layers and two conductive layers is completed, the two metal layers are separated. Therefore, compared to the conventional technique, the manufacturing method of the circuit substrate of the invention does not require a metal substrate to serve as a support carrier, namely, a coreless circuit substrate is achieved, which may effectively reduce the manufacturing cost of the circuit substrate and improve reliability thereof, and effectively reduce a time required for manufacturing the circuit substrate.
  • the conductive layers can be laminated, and then the conductive layers can be patterned to form the circuit layers.

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US20120279630A1 (en) 2012-11-08

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