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US20080305722A1 - Method for the single-sided polishing of bare semiconductor wafers - Google Patents

Method for the single-sided polishing of bare semiconductor wafers Download PDF

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Publication number
US20080305722A1
US20080305722A1 US12/154,347 US15434708A US2008305722A1 US 20080305722 A1 US20080305722 A1 US 20080305722A1 US 15434708 A US15434708 A US 15434708A US 2008305722 A1 US2008305722 A1 US 2008305722A1
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US
United States
Prior art keywords
polishing
semiconductor wafer
membrane
polished
polishing cloth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/154,347
Inventor
Klaus Roettger
Klaus-Peter Meier
Norbert Graeml
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Siltronic AG
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Siltronic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic AG filed Critical Siltronic AG
Assigned to SILTRONIC AG reassignment SILTRONIC AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GRAEML, NORBERT, MEIER, KLAUS-PETER, ROETTGER, KLAUS
Publication of US20080305722A1 publication Critical patent/US20080305722A1/en
Priority to US15/931,561 priority Critical patent/US11452291B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/30—Work carriers for single side lapping of plane surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

Definitions

  • the invention relates to a method for the single-sided polishing (CMP, chemical-mechanical polishing) of bare (nonstructured) semiconductor wafers by using a polishing head with a membrane made of a resilient material, by which the polishing pressure is transmitted onto the backside of the semiconductor wafer to be polished.
  • CMP single-sided polishing
  • Polishing heads or carrier heads with a membrane (membrane carrier) are used in particular to planarize structures of electronic components. Occasionally, there are however also reports of their use for the polishing of bare semiconductor wafers. An example of this may be found in US 2002/0077039 A. It is a central aim of CMP to achieve both maximally high global and local planarity of the polished semiconductor wafer.
  • the polishing cloths are often provided with a surface structure (texture) formed by grooves.
  • the grooves promote uniform distribution of the polishing agent on the polishing cloth and therefore also uniform polishing of the semiconductor wafers.
  • US 2005/0202761 A1 describes a CMP method that uses a polishing cloth provided with grooves, which is optimized with respect to the distribution and the consumption of the polishing agent.
  • a method for the single-sided polishing of a bare semiconductor wafer by using a polishing head with a membrane made of a resilient material, by which the polishing pressure is transmitted onto the backside of the semiconductor wafer to be polished, wherein the semiconductor wafer is pressed against a polishing cloth with a smooth surface while supplying a polishing agent and is prevented from sliding off the membrane by a retainer ring, and wherein the retainer ring is provided with channels on a side surface facing the polishing cloth.
  • FIG. 1 illustrates the nanotopography of a bare wafer polished in accordance with the present invention
  • FIG. 2 illustrates the nanotopography of a wafer polished with a textured cloth as used in the prior art to planarize wafers structured with electronic device features.
  • the inventors have unexpectedly discovered that unfavorable nanotopography is essentially attributable to the surface structure of the polishing cloth being used.
  • the polishing cloth was provided with a pattern of grooves, in order to achieve a surface-wide supply of polishing agent to the polishing cloth and to facilitate lifting of the semiconductor wafer from the polishing cloth after polishing.
  • the claimed method does not use such polishing cloths, in order that the requisite nanotopography can be achieved.
  • the semiconductor wafer is polished on a polishing cloth without texture, i.e. with a smooth surface, a smooth surface being intended to mean a surface which has no artificially added indentations, for example grooves or recesses, and no artificially added elevations, for example ridges or bumps.
  • the surface of the polishing cloth needs to be smooth only in those regions which come in contact with the semiconductor wafer during the polishing.
  • the use of a polishing cloth with a smooth surface also entails a problem which could be avoided by using a textured polishing cloth.
  • the grooves in the polishing cloth facilitate lifting of the semiconductor wafer from the polishing cloth after polishing.
  • the polishing agent contained between the polishing cloth and the semiconductor wafer ensures strong adhesion of the semiconductor wafer to the polishing cloth.
  • the membrane of the polishing head is comparatively soft, so that the semiconductor wafer is susceptible to tilting and being separated from the membrane when the polishing head is lifted from a smooth polishing cloth. When attempting to lift the wafer with the polishing head from the polishing cloth, the semiconductor wafer may therefore remain on the polishing cloth.
  • the polishing head is lifted from the polishing cloth after the polishing with a speed which is preferably no slower than 30 mm/min and no faster than 50 mm/min. With higher speeds, it often happens that the semiconductor wafer is left behind on the polishing cloth.
  • This likewise serves to reduce the adhesion of the semiconductor wafer.
  • the groove lies in a region of the polishing cloth which is not covered by the semiconductor wafer during the polishing, preferably in an edge region, because according to the invention a smooth polishing cloth is required for polishing.
  • haze Another quality parameter, which must be considered for the polishing of bare semiconductor wafers, is the haze (microroughness). It has been found that particularly low haze values are obtained when a retainer ring, which is provided with channels on a side surface facing the polishing cloth, is used for the polishing.
  • a suitable retainer ring is described, for example in U.S. Pat. No. 6,224,472 B1, which is incorporated herein by reference.
  • the number of channels is preferably at least 30, more preferably at least 45, because the haze (microroughness) tends to decrease with an increasing number of channels.
  • the membrane of the polishing head which is in direct contact with the semiconductor wafer during the polishing, must therefore consist of a suitable material. It should as far as possible release no metals and have the lowest possible coefficient of friction, so that as few particles as possible are formed. Membranes made of silicone have proven to be particularly suitable.
  • FIGS. 1 and 2 show the result of the nanotopography measurement on a semiconductor wafer of the example and a semiconductor wafer of the comparative example, respectively. Traces of the texture of the polishing cloth may be seen clearly ( FIG. 2 ) in the case of the semiconductor wafer of the comparative example, which means that the nanotopography has been impaired.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

Single-sided polishing of bare semiconductor wafers is accomplished by using a polishing head with a membrane made of a resilient material by which polishing pressure is transmitted onto the backside of the semiconductor wafer to be polished, wherein the semiconductor wafer is pressed against a polishing cloth with a smooth surface while supplying a polishing agent, and is prevented from sliding off the membrane by a retainer ring. The retainer ring is provided with channels on a side surface facing the polishing cloth.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates to a method for the single-sided polishing (CMP, chemical-mechanical polishing) of bare (nonstructured) semiconductor wafers by using a polishing head with a membrane made of a resilient material, by which the polishing pressure is transmitted onto the backside of the semiconductor wafer to be polished.
  • 2. Background Art
  • Polishing heads (or carrier heads) with a membrane (membrane carrier) are used in particular to planarize structures of electronic components. Occasionally, there are however also reports of their use for the polishing of bare semiconductor wafers. An example of this may be found in US 2002/0077039 A. It is a central aim of CMP to achieve both maximally high global and local planarity of the polished semiconductor wafer.
  • The polishing cloths are often provided with a surface structure (texture) formed by grooves. The grooves promote uniform distribution of the polishing agent on the polishing cloth and therefore also uniform polishing of the semiconductor wafers. US 2005/0202761 A1 describes a CMP method that uses a polishing cloth provided with grooves, which is optimized with respect to the distribution and the consumption of the polishing agent.
  • The requirements for the properties of bare semiconductor wafers with respect to local planarity are increasing constantly, especially in the nanotopography wavelength spectrum, and special efforts are necessary in order to be able to satisfy these requirements. Experiments by the present inventors have shown that the result of using membrane polishing heads to polish bare semiconductor wafers, in combination with textured polishing cloths, is that the nanotopography of the polished semiconductor wafers does not satisfy the requirements expected of polished wafers.
    • SUMMARY OF THE INVENTION
  • It was therefore an object of the present invention to overcome the previously described disadvantages, and to provide a method for the single-sided polishing of a bare semiconductor wafer by using a polishing head with a membrane made of a resilient material, which complies in full scope with modern requirements. These and other objects are achieved by a method for the single-sided polishing of a bare semiconductor wafer by using a polishing head with a membrane made of a resilient material, by which the polishing pressure is transmitted onto the backside of the semiconductor wafer to be polished, wherein the semiconductor wafer is pressed against a polishing cloth with a smooth surface while supplying a polishing agent and is prevented from sliding off the membrane by a retainer ring, and wherein the retainer ring is provided with channels on a side surface facing the polishing cloth.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates the nanotopography of a bare wafer polished in accordance with the present invention; and
  • FIG. 2 illustrates the nanotopography of a wafer polished with a textured cloth as used in the prior art to planarize wafers structured with electronic device features.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
  • The inventors have unexpectedly discovered that unfavorable nanotopography is essentially attributable to the surface structure of the polishing cloth being used. The polishing cloth was provided with a pattern of grooves, in order to achieve a surface-wide supply of polishing agent to the polishing cloth and to facilitate lifting of the semiconductor wafer from the polishing cloth after polishing.
  • The claimed method does not use such polishing cloths, in order that the requisite nanotopography can be achieved. Instead, the semiconductor wafer is polished on a polishing cloth without texture, i.e. with a smooth surface, a smooth surface being intended to mean a surface which has no artificially added indentations, for example grooves or recesses, and no artificially added elevations, for example ridges or bumps. The surface of the polishing cloth needs to be smooth only in those regions which come in contact with the semiconductor wafer during the polishing.
  • The use of a polishing cloth with a smooth surface, however, also entails a problem which could be avoided by using a textured polishing cloth. The grooves in the polishing cloth facilitate lifting of the semiconductor wafer from the polishing cloth after polishing. The polishing agent contained between the polishing cloth and the semiconductor wafer ensures strong adhesion of the semiconductor wafer to the polishing cloth. The membrane of the polishing head is comparatively soft, so that the semiconductor wafer is susceptible to tilting and being separated from the membrane when the polishing head is lifted from a smooth polishing cloth. When attempting to lift the wafer with the polishing head from the polishing cloth, the semiconductor wafer may therefore remain on the polishing cloth. In order to prevent this, in the method according to the invention the polishing head is lifted from the polishing cloth after the polishing with a speed which is preferably no slower than 30 mm/min and no faster than 50 mm/min. With higher speeds, it often happens that the semiconductor wafer is left behind on the polishing cloth.
  • It is furthermore preferable to guide the polishing head by means of a groove in the polishing cloth or by means of the edge of the polishing plate after the polishing and before lifting the polishing cloth off. This likewise serves to reduce the adhesion of the semiconductor wafer. The groove lies in a region of the polishing cloth which is not covered by the semiconductor wafer during the polishing, preferably in an edge region, because according to the invention a smooth polishing cloth is required for polishing.
  • Another quality parameter, which must be considered for the polishing of bare semiconductor wafers, is the haze (microroughness). It has been found that particularly low haze values are obtained when a retainer ring, which is provided with channels on a side surface facing the polishing cloth, is used for the polishing. A suitable retainer ring is described, for example in U.S. Pat. No. 6,224,472 B1, which is incorporated herein by reference. For polishing bare semiconductor wafers with a diameter of 300 mm, the number of channels is preferably at least 30, more preferably at least 45, because the haze (microroughness) tends to decrease with an increasing number of channels.
  • Bare semiconductor wafers must be protected against contamination due to metallic impurities or particles. The membrane of the polishing head, which is in direct contact with the semiconductor wafer during the polishing, must therefore consist of a suitable material. It should as far as possible release no metals and have the lowest possible coefficient of friction, so that as few particles as possible are formed. Membranes made of silicone have proven to be particularly suitable.
  • The success of the invention will be demonstrated below by comparing one embodiment of the subject invention example with a comparative example.
    • EXAMPLE AND COMPARATIVE EXAMPLE
  • Semiconductor wafers made of silicon with a diameter of 300 mm were subjected to single-sided polishing, and the polishing result was examined in respect of the nanotopography. The groups of semiconductor wafers which were polished by the method according to the invention exhibited superior nanotopography after polishing, even though they were polished under the same conditions as the semiconductor wafers of the comparative example. The only difference was that the semiconductor wafers of the comparative example were polished on a textured polishing cloth. FIGS. 1 and 2 show the result of the nanotopography measurement on a semiconductor wafer of the example and a semiconductor wafer of the comparative example, respectively. Traces of the texture of the polishing cloth may be seen clearly (FIG. 2) in the case of the semiconductor wafer of the comparative example, which means that the nanotopography has been impaired.
  • While embodiments of the invention have been illustrated and described, it is not intended that these embodiments illustrate and describe all possible forms of the invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the invention.

Claims (16)

1. A method for the single-sided polishing of a bare semiconductor wafer comprising polishing with a polishing head with a membrane made of resilient material by which polishing pressure is transmitted onto the backside of the semiconductor wafer to be polished, wherein the front side of the semiconductor wafer is pressed against a polishing cloth with a smooth surface while supplying a polishing agent, and is prevented from sliding off the membrane by a retainer ring, wherein the retainer ring is provided with channels on a side surface thereof, facing the polishing cloth.
2. The method of claim 1, wherein the retainer ring has at least 30 channels.
3. The method of claim 1, wherein the semiconductor wafer is guided by means of a groove in the polishing cloth or the edge of the polishing cloth after the polishing and before lifting the polishing head from the polishing cloth, wherein the groove is not located on a portion of the polishing cloth which will contact the wafer surface during polishing.
4. The method of claim 2, wherein the semiconductor wafer is guided by means of a groove in the polishing cloth or the edge of the polishing cloth after the polishing and before lifting the polishing head from the polishing cloth, wherein the groove is not located on a portion of the polishing cloth which will contact the wafer surface during polishing.
5. The method of claim 1, wherein the polishing head is lifted from the polishing cloth after polishing with a speed which is no faster than 50 mm/min.
6. The method of claim 2, wherein the polishing head is lifted from the polishing cloth after polishing with a speed which is no faster than 50 mm/min.
7. The method of claim 3, wherein the polishing head is lifted from the polishing cloth after polishing with a speed which is no faster than 50 mm/min.
8. The method of claim 4, wherein the polishing head is lifted from the polishing cloth after polishing with a speed which is no faster than 50 mm/min.
9. The method of claim 1, wherein the semiconductor wafer is polished with the aid of a membrane comprising silicone.
10. The method of claim 2, wherein the semiconductor wafer is polished with the aid of a membrane comprising silicone.
11. The method of claim 3, wherein the semiconductor wafer is polished with the aid of a membrane comprising silicone.
12. The method of claim 4, wherein the semiconductor wafer is polished with the aid of a membrane comprising silicone.
13. The method of claim 5, wherein the semiconductor wafer is polished with the aid of a membrane comprising silicone.
14. The method of claim 6, wherein the semiconductor wafer is polished with the aid of a membrane comprising silicone.
15. The method of claim 7, wherein the semiconductor wafer is polished with the aid of a membrane comprising silicone.
16. The method of claim 8, wherein the semiconductor wafer is polished with the aid of a membrane comprising silicone.
US12/154,347 2007-05-14 2008-05-22 Method for the single-sided polishing of bare semiconductor wafers Abandoned US20080305722A1 (en)

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DE102007026292A DE102007026292A1 (en) 2007-06-06 2007-06-06 Process for one-sided polishing of unstructured semiconductor wafers
DE102007026292.4 2007-06-06

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JP (1) JP2008306189A (en)
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DE (1) DE102007026292A1 (en)
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TW (1) TW200849357A (en)

Cited By (17)

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US20100327414A1 (en) * 2009-06-24 2010-12-30 Siltronic Ag Method For Producing A Semiconductor Wafer
US20100330881A1 (en) * 2009-06-24 2010-12-30 Siltronic Ag Method For The Double Sided Polishing Of A Semiconductor Wafer
WO2011023297A1 (en) 2009-08-26 2011-03-03 Siltronic Ag Method for producing a semiconductor wafer
DE102009051008A1 (en) 2009-10-28 2011-05-05 Siltronic Ag Method for producing a semiconductor wafer
US20110111677A1 (en) * 2009-11-11 2011-05-12 Siltronic Ag Method for polishing a semiconductor wafer
DE102010005904A1 (en) 2010-01-27 2011-07-28 Siltronic AG, 81737 Method for producing a semiconductor wafer
DE102010010885A1 (en) 2010-03-10 2011-09-15 Siltronic Ag Method for polishing a semiconductor wafer
DE102010013520A1 (en) 2010-03-31 2011-10-06 Siltronic Ag Process for double-sided polishing of a semiconductor wafer
DE102010014874A1 (en) 2010-04-14 2011-10-20 Siltronic Ag Method for producing a semiconductor wafer
DE102010024040A1 (en) 2010-06-16 2011-12-22 Siltronic Ag Process for polishing a semiconductor wafer
DE102011082777A1 (en) 2011-09-15 2012-02-09 Siltronic Ag Method for double-sided polishing of semiconductor wafer e.g. silicon wafer, involves forming channel-shaped recesses in surface of polishing cloth of semiconductor wafer
DE102011089362A1 (en) 2011-12-21 2013-06-27 Siltronic Ag Method for polishing e.g. n-type silicon wafer, involves terminating polishing of semiconductor material made substrate by lifting surface of substrate covered with polishing pad and flushing surface of substrate with water at time
DE102012201516A1 (en) 2012-02-02 2013-08-08 Siltronic Ag Semiconductor wafer polishing method for semiconductor industry, involves performing removal polishing on front and back sides of wafer, and single-sided polishing on front side of wafer in presence of polishing agent
DE102013204839A1 (en) 2013-03-19 2014-09-25 Siltronic Ag Method of polishing a wafer of semiconductor material
DE102013213838A1 (en) 2013-07-15 2014-09-25 Siltronic Ag A method of polishing a substrate of semiconductor material
DE102013205448A1 (en) 2013-03-27 2014-10-16 Siltronic Ag A method of polishing a substrate of semiconductor material
DE102015217109A1 (en) 2015-09-08 2017-03-09 Siltronic Ag A method of polishing a substrate of semiconductor material

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CN102263024A (en) * 2011-07-18 2011-11-30 北京通美晶体技术有限公司 Back side anticorrosion method of single side polishing wafer

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