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US20070080416A1 - Semiconductor device and a method of manufacturing the same - Google Patents

Semiconductor device and a method of manufacturing the same Download PDF

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Publication number
US20070080416A1
US20070080416A1 US11/543,859 US54385906A US2007080416A1 US 20070080416 A1 US20070080416 A1 US 20070080416A1 US 54385906 A US54385906 A US 54385906A US 2007080416 A1 US2007080416 A1 US 2007080416A1
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US
United States
Prior art keywords
pad
bump electrode
semiconductor device
connection portion
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/543,859
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English (en)
Inventor
Akihiko Yoshioka
Shinya Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. CORRECTION TO ASSIGNMENT COVER SHEET Assignors: SUZUKI, SHINYA, YOSHIOKA, AKIHIKO
Publication of US20070080416A1 publication Critical patent/US20070080416A1/en
Priority to US11/953,068 priority Critical patent/US7728442B2/en
Priority to US11/953,055 priority patent/US7538430B2/en
Priority to US12/766,567 priority patent/US8183142B2/en
Priority to US13/396,456 priority patent/US8338968B2/en
Priority to US13/682,672 priority patent/US8624403B2/en
Priority to US14/109,827 priority patent/US9159650B2/en
Priority to US14/836,342 priority patent/US9576924B2/en
Priority to US15/366,794 priority patent/US9929185B2/en
Priority to US15/898,975 priority patent/US10304867B2/en
Priority to US16/385,129 priority patent/US20190244978A1/en
Priority to US16/842,315 priority patent/US10957719B2/en
Abandoned legal-status Critical Current

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Classifications

    • H10D64/011—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10W20/40—
    • H10W72/00—
    • H10W74/131—
    • H10W95/00—
    • H10W70/60—
    • H10W72/01255—
    • H10W72/072—
    • H10W72/07254—
    • H10W72/074—
    • H10W72/227—
    • H10W72/244—
    • H10W72/247—
    • H10W72/251—
    • H10W72/29—
    • H10W72/321—
    • H10W72/325—
    • H10W72/352—
    • H10W72/354—
    • H10W72/5524—
    • H10W72/856—
    • H10W72/926—
    • H10W74/15—

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same and more particularly to a technique which is useful for semiconductor devices used in LCD (Liquid Crystal Display) drivers.
  • LCD Liquid Crystal Display
  • Japanese Unexamined Patent Publication No. Hei 10 discloses a technique which reduces the chip area and achieves production efficiency improvement and cost reduction regarding semiconductor integrated circuits such as driver ICs with many output pads and electronic circuit devices such as electronic clocks.
  • an output pads is placed over a drive transistor to be connected with the output pad or over a logic circuit so that they overlap each other as seen in a plan view.
  • bump electrodes or barrier metals are used for semiconductor device wiring interconnection.
  • electrical connections are made by directly connecting solder bumps of the semiconductor integrated circuit with wires of the printed circuit board.
  • bump electrodes as external connection terminals for the semiconductor integrated circuit are stacked over transistors.
  • FIG. 18 of the above patent document shows that a bump output pad lies over a drive transistor.
  • the drive transistor and the output pad overlap as seen in a plan view, the chip area can be reduced.
  • FIG. 26 of the document shows that one diffusion area and another diffusion area are electrically connected by bump interconnection. This structure makes it possible to have one more wiring layer as compared with the conventional structure.
  • An LCD driver comprises a semiconductor chip, which is typically mounted on a glass substrate.
  • the semiconductor chip which constitutes the LCD driver has a structure that plural transistors and multilayer interconnections are formed over a semiconductor substrate with bump electrodes on its surface.
  • the chip is mounted over the glass substrate through the bump electrodes formed on the surface.
  • the semiconductor chip and the glass substrate are connected through the bump electrodes.
  • the bump electrode area is enlarged to increase the area of contact between the semiconductor chip and the glass substrate.
  • bump electrodes of a semiconductor chip which constitutes an LCD driver are much larger than bump electrodes of semiconductor chips for general purposes.
  • an insulating film which functions as a passivation film is formed under bump electrodes and connected with pads formed in the top layer of the multilayer interconnection through openings in the insulating film.
  • the area of an opening and the area of a pad are determined according to the area of a bump electrode so that they are almost equal.
  • pads which match large bump electrodes are formed in the top layer of the semiconductor chip multilayer interconnection. More specifically, pads which have almost the same area as the bump electrodes are formed in the top layer. This means that in order to leave space for forming interconnection wires different from pads in the top layer of the multilayer interconnection, the semiconductor chip size must be larger.
  • Another problem is that in a normal structure in which bump electrodes are formed just above bonding pads, the positions of bump electrodes are fixed and there are limitations about the layout arrangement of wiring elements such as pads. Consequently it is difficult to adopt a layout arrangement which permits efficient reduction of semiconductor chip size.
  • An object of the present invention is to provide a technique which permits reduction of semiconductor chip size.
  • Another object of the invention is to provide a technique which permits greater latitude in the layout arrangement of interconnection wires formed in the semiconductor chip.
  • a semiconductor device includes a semiconductor chip which comprises: (a) a pad formed over a semiconductor substrate; (b) an insulating film having an opening over the pad; and (c) a bump electrode formed over the insulating film including the opening.
  • the bump electrode is larger than the pad; and a wire different from the pad is formed in a layer under the bump electrode through the insulating film.
  • a semiconductor device includes a semiconductor chip which comprises: (a) a pad formed over a semiconductor substrate; (b) an insulating film having an opening over the pad; and (c) a bump electrode formed over the insulating film including the opening.
  • the bump electrode is larger than the pad; and the bump electrode includes a first portion with a small width and a second portion with a width larger than the width of the first portion.
  • a method of manufacturing a semiconductor device comprises the steps of: (a) forming, in a layer over a semiconductor substrate, a pad and a wire which is different from the pad; (b) forming an insulating film over the pad and the wire different from the pad; (c) making an opening in the insulating film to expose a surface of the pad; and (d) forming a bump electrode over the insulating film including the opening.
  • the pad and the wire different from the pad are formed in a layer under the bump electrode through the insulating film.
  • a method of manufacturing a semiconductor device comprises the steps of (a) forming a pad over a semiconductor substrate and (b) forming an insulating film over the pad. It further comprises the steps of (c) making an opening in the insulating film to expose a surface of the pad and (d) forming a bump electrode over the insulating film including the opening.
  • the bump electrode includes a first portion with a small width and a second portion with a width larger than the width of the first portion.
  • the space beneath a bump electrode can be used effectively and the semiconductor chip size can be reduced. Pads can be arranged regardless of bump electrode positions, which permits greater latitude in the layout arrangement of interconnection wires including pads.
  • FIG. 1 is a plan view of a semiconductor chip according to a first embodiment of the present invention
  • FIG. 2 is a sectional view taken along the line A-A′ of FIG. 1 .
  • FIG. 3 is a sectional view taken along the line B-B′ of FIG. 1 ;
  • FIG. 4 is an enlarged plan view of a region as indicated by line C of FIG. 1 showing that wires are formed just beneath linearly arranged bump electrodes;
  • FIG. 5 is an enlarged plan view of a region as indicated by line D of FIG. 1 showing that wires are formed just beneath bump electrodes arranged in a zigzag pattern;
  • FIG. 6 is a sectional view showing a step in a semiconductor device manufacturing process according to the first embodiment
  • FIG. 7 is a sectional view showing a step next to the step of FIG. 6 in the semiconductor device manufacturing process
  • FIG. 8 is a sectional view showing a step next to the step of FIG. 7 in the semiconductor device manufacturing process
  • FIG. 9 is a sectional view showing a step next to the step of FIG. 8 in the semiconductor device manufacturing process.
  • FIG. 10 is a sectional view showing a step next to the step of FIG. 9 in the semiconductor device manufacturing process
  • FIG. 11 is a sectional view showing a step next to the step of FIG. 10 in the semiconductor device manufacturing process
  • FIG. 12 shows that a semiconductor chip is. mounted on a glass substrate
  • FIG. 13 is an enlarged view of the semiconductor chip mounted on the glass substrate
  • FIG. 14 shows the general structure of an LCD
  • FIG. 15 shows the general structure of another type of LCD
  • FIG. 16 shows how a semiconductor chip is mounted on a packaging substrate in the TCP (Tape Carrier Package) form
  • FIG. 17 shows an example in which a semiconductor chip packaged in the TCP form lies between a glass substrate and a printed circuit board
  • FIG. 18 shows how a semiconductor chip is mounted on a packaging substrate in the COF (Chip On Film) form
  • FIG. 19 shows an example in which a semiconductor chip packaged in the COF form lies between a glass substrate and a printed circuit board
  • FIG. 20 is a fragmentary plan view of a semiconductor chip according to a second embodiment of the invention.
  • FIG. 21 is a plan view showing a variation of the second embodiment.
  • FIG. 22 is a plan view showing another variation of the second embodiment.
  • FIG. 1 is a plan view showing the structure of a semiconductor chip 1 (semiconductor device) according to the first embodiment.
  • the semiconductor chip 1 according to the first embodiment is a driver for an LCD.
  • the semiconductor chip 1 has a semiconductor substrate 2 which takes the form of, for example, an elongated rectangle, and for example, an LCD driver which drives a liquid crystal display is formed on its main surface.
  • This driver has the function of controlling the orientations of liquid crystal molecules by supplying voltage to each pixel in a cell array constituting the LCD and includes gate drive circuits 3 , a source drive circuit 4 , a liquid crystal circuit 5 , graphic RAMs (Random Access Memories) 6 , and peripheral circuits 7 .
  • a plurality of bump electrodes 8 are arranged at regular intervals along the periphery of the semiconductor chip 1 . These bump electrodes 8 lie over active regions where elements and interconnection wires of the semiconductor chip 1 are located.
  • the plural bump electrodes 8 include bump electrodes for integrated circuits which are necessary for an integrated circuit configuration and dummy electrodes which are not necessary for the integrated circuit configuration. Bump electrodes 8 are arranged in a zigzag pattern in the vicinities of one long edge and the two short edges of the semiconductor chip 1 .
  • the plural bump electrodes 8 arranged in a zigzag pattern are mainly used as bump electrodes for gate output signals or source output signals.
  • the bump electrodes 8 arranged in a zigzag pattern around the center of the long edge of the semiconductor chip 1 are bump electrodes for source output signals and those arranged in a zigzag pattern along the long edge of the semiconductor chip 1 in the vicinities of its corners and those arranged in a zigzag pattern along the short edges of the semiconductor chip 1 are bump electrodes for gate output signals.
  • This zigzag pattern allows arrangement of many bump electrodes necessary for gate output signals and source output signals while eliminating the need for increase in the size of the semiconductor chip 1 . In other words, it is possible to reduce the chip size and increase the number of bump electrodes at the same time.
  • bump electrodes 8 are arranged not in a zigzag pattern but linearly.
  • the linearly arranged bump electrodes 8 are bump electrodes for digital input signals or analog input signals.
  • dummy bump electrodes are arranged around the four corners of the semiconductor chip 1 .
  • bump electrodes 8 for gate output signals or source output signals are arranged in a zigzag pattern and bump electrodes 8 for digital input signals or analog input signals are arranged linearly.
  • bump electrodes 8 for gate output signals or source output signals are arranged linearly and bump electrodes 8 for digital input signals or analog input signals are arranged in a zigzag pattern.
  • FIG. 2 is a sectional view taken along the line A-A′ of FIG. 1 .
  • the layers under the top layer are omitted.
  • a semiconductor element such as a MTSFET (Metal Insulator Semiconductor Field Effect Transistor) is formed over the semiconductor substrate and a multilayer interconnection is made over the semiconductor element.
  • FIG. 2 shows the multilayer interconnection above the top layer of the multilayer interconnection structure.
  • top layer interconnection wiring is made over the insulating film 9 of, for example, oxide silicon.
  • the top layer interconnection wiring includes, for example, a pad 10 and wires different from the pad 10 , 11 a and 11 b .
  • the wires 11 a and 11 b are, for example, signal wires for signals or power wires for power supply or dummy wires.
  • the pad 10 and wires 11 a and 11 b consist of, for example, an aluminum film.
  • a surface protective film (passivation film) 12 is formed over the pad 10 and wires 11 a and 11 b so as to cover the pad 10 and wires 11 a and 11 b .
  • the surface protective film 12 consists of an insulating film of silicon nitride.
  • An opening 13 is made in the surface protective film 12 to expose a surface of the pad 10 and a bump electrode 8 is formed over the surface protective film 12 including the inside of the opening 13 through a UBM film 14 as an undercoat metal film.
  • the wiring layer including the pad 10 and wires 11 a , 11 b are the wiring layer including the pad 10 and wires 11 a , 11 b , and plural other wiring layers (not shown) lying under the wiring layer including the pad 10 and wires 11 a , 11 b .
  • a semiconductor element such as the abovementioned MISFET (not shown) is formed under the bump electrode 8 .
  • this embodiment makes it possible to reduce the chip area of the semiconductor chip 1 by efficient use of space under the bump electrode 8 .
  • the opening 13 and the pad 10 are smaller than the bump electrode 8 .
  • an opening 13 whose size is almost equal to the bump electrode 8 has been formed under the bump electrode 8 and a pad 10 larger than the bump electrode 8 has been formed under the opening 13 .
  • the pad 10 has been formed under the bump electrode 8 and the size of the pad 10 has been almost the same as the size of the bump electrode 8 .
  • the bump electrode 8 should be enlarged in order to ensure its adhesion to the glass substrate.
  • the pad 10 which is formed in a layer under the bump electrode 8 should be larger.
  • the opening 13 and the pad 10 are smaller than the bump electrode 8 as shown in FIG. 2 .
  • the bump electrode 8 is larger than the pad 10 .
  • the pad 10 is smaller than the bump electrode 8 , space available for formation of other wires 11 a and 11 b is left just beneath the bump electrode 8 in the same top layer in which the pad 10 lies. Therefore, it is possible to form wires 11 a and 11 b just beneath the bump electrode 8 in addition to the pad 10 , so that space just beneath the bump electrode 8 can be used effectively and the size of the semiconductor chip 1 can be reduced.
  • the first embodiment is characterized in that the size of the bump electrode 8 remains unchanged and the pad 10 is smaller than the bump electrode 8 , leaving space for formation of wires different from the pad 10 for the bump electrode 8 .
  • the area of the bump electrode 8 to adhere to the glass substrate is large enough, space for wires different from the pad 10 is left so that the size of the semiconductor chip 1 can be reduced.
  • This technical idea is not described nor suggested even in the patent document cited earlier under the heading “BACKGROUND OF THE INVENTION” and unique to this first embodiment. For example, it is possible to make the bump electrode larger than the pad by increasing the size of the bump electrode without changing the pad size; however, in this case, the size of the pad itself is not reduced and space left by reducing the pad size cannot be obtained.
  • a larger bump electrode leads to a larger semiconductor chip, which means that it is impossible to reduce the size of the semiconductor chip.
  • the pad width may be smaller than a relatively wide wire different from the pad, such as a power wire.
  • FIG. 3 is a sectional view taken along the line B-B′ of FIG. 1 .
  • a pad 10 is formed over the insulating film 9 and a surface protective film 12 is formed so as to cover the pad 10 .
  • An opening 13 is made in the surface protective film 12 and a surface of the pad 10 is exposed at the bottom of the opening 13 .
  • a bump electrode 8 is formed over the surface protective film 12 including the inside of the opening 13 through a UBM film 14 .
  • the width of the pad 10 is almost equal to, or larger than, the width of the bump electrode 8 .
  • the width of the pad 10 is smaller than the width of the bump electrode 8 , and the pad 10 and other signal wires and power wires are formed just beneath the bump electrode 8 .
  • the width of the pad 10 formed just beneath the bump electrode 8 is almost equal to that of the bump electrode 8 .
  • FIG. 4 is an enlarged plan view of region C of FIG. 1 showing that wires are formed just beneath linearly arranged bump electrodes 8 .
  • rectangular bump electrodes 8 lie side by side along the short edge direction (perpendicular to the long edge direction).
  • a surface protective film 12 is. formed under the bump electrodes 8 and openings 13 are made in the surface protective film 12 .
  • a pad 10 is formed in a layer under the opening 13 made in the surface protective film 12 .
  • the pad 10 is electrically connected with a bump electrode 8 partially buried in the opening.
  • the pad 10 is square and one edge thereof is slightly longer than the short edge of the bump electrode 8 . Consequently as shown in FIG.
  • the length of the pad 10 is slightly larger than the length of the bump electrode 8 in the short edge direction of the bump electrode 8 .
  • the length of the pad 10 is far smaller than the length of the bump electrode 8 in the long edge direction of the bump electrode 8 .
  • the pad 10 is smaller than the bump electrode 8 and the pad 10 lies only under one end of the bump electrode 8 . Therefore, in the long edge direction of the bump electrode 8 , space is left in the same wiring layer in which the pad 10 lies. Wires 11 a to 11 c which are different from the pad 10 are formed in this space.
  • wires 11 a to 11 c can be formed just beneath the bump electrode 8 in the same layer in which the pad 10 lies. Since space just beneath the rectangular large bump electrode 8 can be used effectively, the size of the semiconductor chip can be reduced.
  • the wires 11 a to 11 c are signal wires, power wires or dummy wires and may have different widths.
  • FIG. 4 indicates that the wire 11 c is wider than the wires 11 a and 11 b .
  • the pad size has been similar to the size of the bump electrode 8 and the pad width is relatively large as compared with other wires.
  • the pad 10 is smaller than the bump electrode 8 and space available for formation of wires is left just beneath the bump electrode 8 . Therefore, the width of the pad 10 may be smaller than, for example, the width of a power wire formed in the abovementioned space.
  • the width of the pad 10 may be smaller than the width of another wire.
  • the wires 11 a to 11 c extend along the direction perpendicular to the long edge direction of the bump electrode 8 . Although it is desirable from the viewpoint of effective use of space that the wires 11 a to 11 c should be perpendicular to the long edge direction of the bump electrodes 8 , they need not necessarily be perpendicular to the long edge direction of the bump electrodes 8 .
  • the wires may obliquely intersect with the long edges of the bump electrodes 8 depending on the interconnection pattern. Even if that is the case, space just beneath the bump electrode 8 is available and the semiconductor chip can be smaller.
  • FIG. 5 is an enlarged plan view of region D of FIG. 1 showing that wires lie just beneath bump electrodes 8 arranged in a zigzag pattern.
  • the width of the bump electrode 8 is far larger than the width of the pad 10 , and space is left in the long edge direction of the bump electrode 8 in the same layer in which the pad 10 lies. Wires 11 d to 11 k are formed in this space.
  • bump electrodes 8 are arranged in a zigzag pattern, they form two rows as shown in FIG. 5 . Therefore, space left just beneath bump electrodes 8 is larger than when bump electrodes 8 form one row.
  • bump electrodes 8 are arranged in a zigzag pattern, space just beneath the bump electrodes 8 can be used almost as effectively as when they are arranged in one row.
  • wires can be formed not only beneath bump electrodes 8 arranged in one row but also beneath the ones in a zigzag pattern and the semiconductor chip size can be thus reduced.
  • the number of bump electrodes 8 in region D of FIG. 1 ( FIG. 5 ) is larger than in region C of FIG. ( FIG. 4 ). This is because more bump electrodes 8 are needed in region D of FIG. 1 in order to drive elements of an LCD screen area 20 (described later) as shown in FIG. 15 .
  • the bump electrodes 8 in region D of FIG. 1 are mainly used for gates and sources of elements of the LCD screen area 20 .
  • FIG. 6 shows wires formed in the top layer where the layers under the wires in the top layer are omitted.
  • an insulating film 9 of oxide silicon is formed as shown in FIG. 6 .
  • the insulating film 9 maybe formed using a CVD (Chemical Vapor Deposition) process.
  • a titanium or titanium nitride film, an aluminum film and a titanium or titanium nitride film are stacked over the insulating film 9 .
  • patterning is done on the stacked films by photolithography or etching and a pad 10 and wires 11 a and 11 b are formed by this patterning process.
  • the pad 10 thus formed is smaller than a bump electrode formed by a process which will be described later.
  • the wires 11 a and 11 b are formed just beneath a bump electrode.
  • a surface protective film 12 is formed over the insulating film 9 in which the pad 10 and wires 11 a and 11 b are formed.
  • the surface protective film 12 consists of, for example, a silicon nitride film and is made by a CVD process.
  • an opening 13 is made in the surface protective film 12 by photolithography or etching. This opening 13 lies over the pad 10 and exposes a surface of the pad 10 .
  • the opening 13 should be smaller than the pad 10 .
  • a UBM (Under Bump Metal) film 14 is formed over the surface protective film 12 including the inside of the opening 13 .
  • the UBM film 14 is made by sputtering and consists of a single film of titanium, nickel, palladium, titanium-tungsten alloy, titanium nitride or gold or a laminate of films of these materials.
  • the UBM film 14 has not only the function of improving the adhesion of the bump electrode 8 to the pad 10 and surface protective film 12 but also the barrier function which suppresses or prevents movement of the metal element of a conductive film 16 made by a subsequent process toward the wire 11 a , 11 b or the like, or movement of the metal element of the wire 11 a , 11 b or the like toward the conductive film 16 .
  • the plan view size of the UBM film 14 is larger than that of the opening 13 and almost equal to that of the conductive film 16 .
  • a resist film 15 is coated over the UBM film 14 .
  • Patterning is done in a way not to leave the resist film 15 in the bump electrode formation region.
  • a gold film is formed as a conductive film 16 by plating.
  • a bump electrode 8 consisting of a conductive film 16 and a UBM film 14 , is formed by removing the pattern resist film 15 and the UBM film 14 portion covered by the resist film 15 .
  • separate semiconductor chips are produced by dicing the semiconductor substrate.
  • wires 11 a and 11 b can be formed beneath the bump electrode 8 .
  • the pad 10 and the wires 11 a and 11 b can be formed in the same layer just beneath the bump electrode 8 , so that the space left just beneath the bump electrode 8 can be effectively used and the semiconductor chip size can be reduced.
  • the method of manufacturing a semiconductor device according to the first embodiment is the same as conventional semiconductor device manufacturing methods except that patterning is done in a way to form, just beneath the bump electrode 8 , the pad 10 and the wires 11 a and 11 b which should lie in the same layer as the pad 10 . Therefore, a semiconductor device according to the first embodiment is manufactured without complicating the manufacturing process. This means that an advantageous effect is achieved without any drastic change in the manufacturing process.
  • FIG. 12 shows a case that the semiconductor chip 1 is mounted over a glass substrate 17 a (COG: Chip On Glass).
  • a glass substrate 17 b is mounted on the glass substrate 17 a , forming an LCD screen area.
  • a semiconductor chip 1 as an LCD driver is mounted on the glass substrate 17 a in the vicinity of the LCD screen area.
  • the semiconductor chip 1 has bump electrodes 8 where the bump electrodes 8 are connected with terminals formed on the glass substrate 17 a through anisotropic conductive film 19 .
  • the glass substrate 17 a and a flexible printed circuit 18 are also connected through the anisotropic conductive film 19 .
  • a bump electrode 8 for output is electrically connected with the LCD screen area and a bump electrode 8 for input is connected with the flexible printed circuit board 18 .
  • FIG. 13 is an enlarged view of the semiconductor chip 1 mounted on the glass substrate 17 a .
  • terminals 20 a lie over the glass substrate 17 a and bump electrodes 8 of the semiconductor chip 1 are electrically connected with the terminals 20 a .
  • the bump electrodes 8 and the terminals 20 a are connected not directly but through the anisotropic conductive film 19 .
  • FIG. 14 shows the general structure of the LCD.
  • the LCD screen area 20 lies over the glass substrate and an image appears on the screen area 20 .
  • the semiconductor chip 1 as an LCD driver is mounted over the glass substrate in the vicinity of the screen area 20 .
  • the flexible printed circuit board 18 is mounted in the vicinity of the semiconductor chip 1 and the semiconductor chip 1 as a driver lies between the printed circuit board 18 and the LCD screen area 20 .
  • the semiconductor chip 1 may be mounted over the glass substrate 17 a in this way.
  • FIG. 15 shows a TCP (Tape Carrier Package) form 21 and a COF (Chip On Film) form 22 as non-COG examples of semiconductor chip packaging.
  • FIG. 16 shows how a semiconductor chip 1 is mounted on a packaging substrate in the TCP form.
  • the packaging substrate is a film substrate in the tape form (tape substrate) 23 and for example, a lead wire of copper 24 is formed over the film substrate 23 .
  • the semiconductor chip 1 is mounted over the film substrate 23 so that a bump electrode 8 adheres to the lead wire 24 .
  • the semiconductor chip 1 is sealed with resin 25 .
  • FIG. 17 shows an example in which a semiconductor chip 1 packaged in the TCP form lies between the glass substrate 17 a and the printed circuit board 28 . As illustrated in FIG. 17 , the glass substrate 17 a is connected with the lead wire 24 formed over the film substrate 23 through anisotropic conductive film 26 and similarly the lead wire 24 formed over the film substrate 23 is connected with the printed circuit board 28 through anisotropic conductive film 27 .
  • FIG. 18 shows how a semiconductor chip 1 is mounted on a packaging substrate in the COF form.
  • the packaging substrate is a film substrate 29 in the tape form.
  • a lead wire of copper 30 lies over the film substrate 29 but unlike the TCP form, the lead wire 30 is fixed on the film substrate 29 even at the area of connection with a bump electrode 8 .
  • a semiconductor chip 1 is mounted over the film substrate 29 in a manner that the bump electrode 8 adheres to the lead wire 30 .
  • FIG. 19 shows an example in which a semiconductor chip 1 is mounted between a glass substrate 17 a and a printed circuit board 28 in the COF form. As illustrated in FIG.
  • the glass substrate 17 a is connected with a lead wire 30 formed over a film substrate 29 through anisotropic conductive film 26 and similarly the lead wire 30 formed over the film substrate 29 is connected with the printed circuit board 28 through anisotropic conductive film 27 .
  • a semiconductor chip 1 as an LCD driver may be packaged in various forms as mentioned above.
  • the second embodiment concerns a semiconductor device with wide layout latitude which optimizes pad positions regardless of bump electrode positions.
  • FIG. 20 is a fragmentary plan view of a semiconductor chip according to the second embodiment.
  • a pad 10 is connected with a pad connection portion 8 a as a part of a bump electrode 8 through an opening 13 made in a surface protective film 12 .
  • the bump electrode 8 consists of: a pad connection portion 8 a to be connected with the pad 10 ; a terminal connection portion 8 c to be connected with a terminal of a packaging substrate; and a wiring portion 8 b which connects the pad connection portion 8 a and the terminal connection portion 8 c .
  • a conventional bump electrode consists of only a terminal connection portion which is connected with a pad.
  • the terminal connection portion also functions as a pad connection portion, which means that the pad connection portion and the terminal connection portion overlap each other as seen in a plan view.
  • the pad connection portion 8 a and the terminal connection portion 8 c are formed in different places as seen in a plan view and the pad connection portion 8 a and the terminal connection portion 8 c in different places as seen in a plan view are connected by the wiring portion 8 b .
  • the pad connection portion 8 a and the terminal connection portion 8 c are larger than the wiring portion 8 b in terms of wire width, as seen in a plan view.
  • the pad connection portion 8 a and the terminal connection portion 8 c have to be connected with the pad 10 and the lead wire on the glass substrate (or film substrate) respectively and therefore their flat surfaces must be large enough to secure the connections. Since the wire width of the wiring portion 8 b is relatively small, contact with other wiring portions 8 b is less likely, permitting greater latitude in interconnection wiring arrangement.
  • pads 10 can be arranged not in a zigzag pattern but in one row in the X direction while terminal connection portions 8 c of bump electrodes 8 are arranged in a zigzag pattern. This means that the positions of pads can be determined regardless of the positions of bump electrodes.
  • bump electrodes and pads overlap as seen in a plan view; and when bump electrodes are arranged in a zigzag pattern in the y direction, pads should also be arranged in a zigzag pattern in the y direction. In this case, pads are arranged in two rows and wires different from the pads cannot be laid in areas where the pads lie.
  • pads 10 need not be arranged in a zigzag pattern and can be arranged in one row in the x direction as shown in FIG. 20 . Therefore, space occupied by pads 10 is smaller than when pads 10 are arranged in two rows.
  • the space occupied by pads 10 is smaller, it is possible to leave enough space to form wires different from pads 10 , 11 a to 11 k , under bump electrodes 8 in the same layer in which the pads 10 lie. Therefore, the semiconductor chip size can be further reduced.
  • the wires 11 a to 11 k which are formed just beneath bump electrodes 8 need not be linear; they may be folded or curved.
  • a bump electrode 8 consists of a pad connection portion 8 a , a wiring portion 8 b , and a terminal connection portion 8 c , and the pad connection portion 8 a and the terminal connection portion 8 c do not overlap as seen in a plan view.
  • the pad connection portion 8 a , wiring portion 8 b and terminal connection portion 8 c are in the same layer. This make it possible that bump electrodes 8 , extending in they direction, are arranged in a zigzag pattern while pads 10 are arranged in one row in the x direction.
  • a bump electrode 8 consists of a pad connection portion 8 a , a wiring portion 8 b , and a terminal connection portion 8 c may be interpreted as follows: a bump electrode 8 includes a narrower wiring portion (first portion) 8 b and a terminal connection portion (second portion) 8 which is wider than the wiring portion 8 b .
  • the terminal connection portion 8 c of a bump electrode 8 is relatively wide because the terminal connection portion 8 c is to be bonded to a packaging substrate while the width of the wiring portion 8 b is relatively small because the wiring portion 8 b is only intended to connect the pad connection portion and the terminal connection portion, so that bump electrodes 8 are arranged in a zigzag pattern at small intervals.
  • the positions of pads can be determined so as to reduce the semiconductor chip size efficiently regardless of bump electrode positions. In other words, since greater latitude in pad arrangement is permitted, the semiconductor chip size can be reduced efficiently. In addition, since the area of the terminal connection portion 8 c of a bump electrode 8 may be increased regardless of the pad 10 , the area of contact with the packaging substrate can be changed flexibly.
  • the method of manufacturing a semiconductor device according to the second embodiment is almost the same as in the first embodiment.
  • a bump electrode 8 consists of a pad connection portion 8 a , a wiring portion 8 b , and a terminal connection portion 8 c , and the pad connection portion 8 a and the terminal connection portion 8 c do not overlap as seen in a plan view.
  • the width of the terminal connection portion 8 c should be larger than that of the wiring portion 8 b .
  • a semiconductor device according to the second embodiment is manufactured with these points into consideration.
  • FIG. 21 is a plan view of a variation of the second embodiment.
  • FIG. 21 shows a case that pads 10 are arranged in one row in the x direction and the terminal connection portions 8 c of bump electrodes 8 are arranged in one row in the y direction.
  • a bump electrode 8 which consists of a pad connection portion 8 a , a wiring portion 8 b , and a terminal connection portion 8 c .
  • pads 10 can be arranged in one row in the x direction.
  • the positions of pads 10 can be determined irrespective of where the terminal connection portions 8 c are formed. Again, though not shown in FIG. 21 , wires different from pads 10 are formed just beneath the bump electrodes 8 in the same layer in which the pads 10 lie. Therefore, space just beneath the bump electrodes 8 can be used effectively so that the semiconductor chip size is reduced. Furthermore, since this permits greater latitude in the layout arrangement of pads 10 , the semiconductor chip size can be further reduced by optimizing the positions of pads 10 .
  • FIG. 21 indicates that the wiring portions 8 b of the bump electrodes 8 are bent at right angles; however, instead it is also possible that they are curved.
  • FIG. 22 is a plan view showing another variation of the second embodiment.
  • FIG. 22 shows a case that pads 10 are arranged in one row in the x direction and the terminal connection portions 8 c of bump electrodes 8 are arranged in a zigzag pattern in the y direction.
  • a bump electrode 8 which consists of a pad connection portion 8 a , a wiring portion 8 b , and a terminal connection portion 8 c .
  • pads 10 can be arranged in one row in the x direction.
  • the positions of pads 10 can be determined irrespective of where the terminal connection portions 8 c are formed. Again, though not shown in FIG. 22 , wires different from pads 10 are formed just beneath the bump electrodes 8 in the same layer in which the pads 10 lie. Therefore, space just beneath the bump electrodes 8 can be used effectively so that the semiconductor chip size is reduced. Furthermore, since this permits greater latitude. in the layout arrangement of pads 10 , the semiconductor chip size can be further reduced by optimizing the positions of pads 10 .
  • bump electrodes 8 and pads 10 are located along the four edges of a semiconductor chip in the abovementioned embodiments, obviously the invention is not limited thereto.
  • pads 10 are located in the vicinities of the four edges of the semiconductor chip 1 and bump electrodes 8 extend to the center of the semiconductor chip 1 .
  • pads 10 are located in the center of the semiconductor chip 1 and bump electrodes 8 extend to the four edges of the semiconductor chip 1 .
  • the present invention may be used widely in the semiconductor manufacturing industry.

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  • Engineering & Computer Science (AREA)
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US11/953,068 US7728442B2 (en) 2005-10-07 2007-12-09 Semiconductor device and a method of manufacturing the same
US11/953,055 US7538430B2 (en) 2005-10-07 2007-12-09 Semiconductor device and a method of manufacturing the same
US12/766,567 US8183142B2 (en) 2005-10-07 2010-04-23 Semiconductor device and a method of manufacturing the same
US13/396,456 US8338968B2 (en) 2005-10-07 2012-02-14 Semiconductor device and a method of manufacturing the same
US13/682,672 US8624403B2 (en) 2005-10-07 2012-11-20 Semiconductor device and a method of manufacturing the same
US14/109,827 US9159650B2 (en) 2005-10-07 2013-12-17 Semiconductor device and a method of manufacturing the same
US14/836,342 US9576924B2 (en) 2005-10-07 2015-08-26 Semiconductor device and a method of manufacturing the same
US15/366,794 US9929185B2 (en) 2005-10-07 2016-12-01 Semiconductor device and a method of manufacturing the same
US15/898,975 US10304867B2 (en) 2005-10-07 2018-02-19 Semiconductor device and a method of manufacturing the same
US16/385,129 US20190244978A1 (en) 2005-10-07 2019-04-16 Semiconductor device and a method of manufacturing the same
US16/842,315 US10957719B2 (en) 2005-10-07 2020-04-07 Semiconductor device and a method of manufacturing the same

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US11/953,068 Active US7728442B2 (en) 2005-10-07 2007-12-09 Semiconductor device and a method of manufacturing the same
US12/766,567 Active 2027-04-05 US8183142B2 (en) 2005-10-07 2010-04-23 Semiconductor device and a method of manufacturing the same
US13/396,456 Active US8338968B2 (en) 2005-10-07 2012-02-14 Semiconductor device and a method of manufacturing the same
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US14/109,827 Active 2026-10-30 US9159650B2 (en) 2005-10-07 2013-12-17 Semiconductor device and a method of manufacturing the same
US14/836,342 Active US9576924B2 (en) 2005-10-07 2015-08-26 Semiconductor device and a method of manufacturing the same
US15/366,794 Active US9929185B2 (en) 2005-10-07 2016-12-01 Semiconductor device and a method of manufacturing the same
US15/898,975 Active US10304867B2 (en) 2005-10-07 2018-02-19 Semiconductor device and a method of manufacturing the same
US16/385,129 Abandoned US20190244978A1 (en) 2005-10-07 2019-04-16 Semiconductor device and a method of manufacturing the same
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US12/766,567 Active 2027-04-05 US8183142B2 (en) 2005-10-07 2010-04-23 Semiconductor device and a method of manufacturing the same
US13/396,456 Active US8338968B2 (en) 2005-10-07 2012-02-14 Semiconductor device and a method of manufacturing the same
US13/682,672 Active US8624403B2 (en) 2005-10-07 2012-11-20 Semiconductor device and a method of manufacturing the same
US14/109,827 Active 2026-10-30 US9159650B2 (en) 2005-10-07 2013-12-17 Semiconductor device and a method of manufacturing the same
US14/836,342 Active US9576924B2 (en) 2005-10-07 2015-08-26 Semiconductor device and a method of manufacturing the same
US15/366,794 Active US9929185B2 (en) 2005-10-07 2016-12-01 Semiconductor device and a method of manufacturing the same
US15/898,975 Active US10304867B2 (en) 2005-10-07 2018-02-19 Semiconductor device and a method of manufacturing the same
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US7728442B2 (en) 2010-06-01
US20200235131A1 (en) 2020-07-23
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