US20060035437A1 - Semiconductor device having dual-STI and manufacturing method thereof - Google Patents
Semiconductor device having dual-STI and manufacturing method thereof Download PDFInfo
- Publication number
- US20060035437A1 US20060035437A1 US11/200,262 US20026205A US2006035437A1 US 20060035437 A1 US20060035437 A1 US 20060035437A1 US 20026205 A US20026205 A US 20026205A US 2006035437 A1 US2006035437 A1 US 2006035437A1
- Authority
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- United States
- Prior art keywords
- area
- film
- isolation structure
- insulating film
- silicon
- Prior art date
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- Abandoned
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H10W10/00—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
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- H10W10/01—
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- H10W10/0143—
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- H10W10/17—
Definitions
- Dual-STI has normally been formed in the following manner. Initially, a shallow trench portion is formed in the memory cell area and the peripheral circuit area with the conventional method of manufacturing the STI. Thereafter, the memory cell area is covered with a resist. Using the resist and a silicon nitride film as a mask, the semiconductor substrate is anisotropically etched, so as to form a deep trench portion within the shallow trench portion in the peripheral circuit area. After the resist is removed, the silicon oxide film is deposited on the entire surface. Extra silicon oxide film is removed by CMP, using the silicon nitride film as a stopper, so as to form Dual-STI having the shallow trench portion and the deep trench portion embedded with the silicon oxide film. After the Dual-STI is formed, the silicon oxide film, polysilicon, and the silicon nitride film formed on the silicon substrate are removed.
- a semiconductor device has a first area and a second area.
- the semiconductor device includes a silicon substrate, and an isolation structure implemented by a silicon insulating film formed on a surface of the silicon substrate.
- a depth of the isolation structure in the first area is smaller than that in the second area, and an isolation height of the isolation structure in the first area is substantially the same as that in the second area.
- FIGS. 2 to 8 are cross-sectional views sequentially showing a method of manufacturing a semiconductor device in the first embodiment of the present invention.
- FIG. 16 is a cross-sectional view along the line XVI-XVI in FIG. 15 .
- FIG. 21 is a cross-sectional view along the line XXI-XXI in FIG. 15 .
- FIGS. 22 to 28 are cross-sectional views sequentially showing a method of manufacturing a semiconductor device in the third embodiment of the present invention.
- FIG. 31 is an enlarged cross-sectional view of a state in which a silicide layer is formed in the semiconductor device when a silicon oxide film is not formed on a silicon nitride film.
- the method of manufacturing a semiconductor device having the memory cell area and the peripheral circuit area includes the following steps.
- Silicon oxide film 5 is formed on silicon substrate 1 .
- Trenches 15 a, 15 b are formed in silicon oxide film 5 and silicon substrate 1 in the memory cell area and the peripheral circuit area respectively.
- Resist 20 b is formed in trench 15 a formed in the memory cell area and on silicon oxide film 5 in the memory cell area.
- Silicon substrate 1 is etched, using resist 20 b and silicon oxide film 5 as a mask, so as to form trench 15 c in trench 15 b in the peripheral circuit area.
- Resist 20 b is removed.
- Second silicon oxide film 6 is formed on silicon oxide films 5 a, 5 b so as to bury trenches 15 a, 15 c.
- Silicon oxide films 5 a, 5 b and second silicon oxide film 6 on silicon substrate 1 are removed, so as to form isolation structures 6 a, 6 b in trenches 15 a, 15 c respectively.
- an isolation height h 4 of isolation structure 206 b becomes lower than an isolation height h 3 of isolation structure 206 a. More specifically, when depth d 3 of isolation structure 206 a is set to a value not smaller than 100 nm and less than 200 nm and depth d 4 of isolation structure 206 b is set to 200-400 nm, a difference of approximately 30 to 80 nm is produced between isolation height h 3 of isolation structure 206 a and isolation height h 4 of isolation structure 206 b. Moreover, if a gate oxide film in the peripheral circuit area is newly deposited, the difference is further increased.
- the height of the isolation structure in the present embodiment is preferably set to approximately 0 to 60 nm, and more preferably to approximately 20 to 40 nm.
- the active region at the boundary between the memory cell area and the peripheral circuit area serves as a dummy pattern.
- the dummy pattern is not necessary or can be made smaller, and therefore an element area can further be reduced.
- isolation structures having two types of depths that is, isolation structure 6 a having depth d 1 and isolation structure 6 b having depth d 2 , are formed, however, the present invention is not limited as such.
- isolation structures set to a plurality of depths may be formed.
- isolation structures having three or four types of depths may be formed.
- gate structures 132 , 133 of memory cell transistors are formed.
- floating gate electrodes implemented by a polysilicon film 108 (first conductive film) are formed on silicon substrate 101 , with a silicon oxide film 102 (first gate insulating film) being interposed.
- gate structures 134 , 135 of transistors for the peripheral circuit are formed.
- gate structures 134 , 135 of transistors gate electrodes implemented by polysilicon film 111 and tungsten silicide film 112 are formed on silicon substrate 101 with a silicon oxide film 110 (second gate insulating film) being interposed. Silicon oxide film 113 is formed on tungsten silicide film 112 .
- source/drain regions 116 , 117 of the transistor are formed on the surface of silicon substrate 101 .
- Sacrificial oxide film 102 is formed on a main surface of silicon substrate 101 , for example, using thermal oxidation or the like. Then, impurity ions are implanted into the prescribed area on the surface of silicon substrate 101 through sacrificial oxide film 102 , and heat treatment is performed so as to form P-type well 107 and embedded N-type well 106 . Thereafter, sacrificial oxide film 102 is removed, and the surface of silicon substrate 101 is subjected to oxidation. Then, silicon oxide film 102 is newly formed.
- a photoresist pattern (not shown) is formed on silicon oxide film 113 , and using this photoresist pattern as a mask, silicon oxide film 113 is anisotropically etched, whereby silicon oxide film 113 is patterned. Thereafter, the photoresist pattern is removed. Then, using patterned silicon oxide film 113 as a mask, tungsten silicide film 112 and polysilicon film 111 are anisotropically etched.
- the floating gate electrode implemented by polysilicon film 108 is formed on silicon oxide film 102 in the memory cell area.
- ONO film 109 and polysilicon film 108 implementing the dummy gate structure 131 are formed in the memory cell area around the boundary between the memory cell area and the peripheral circuit area.
- a prescribed ion implantation process is carried out, so as to form low-concentration impurity region 114 a serving as the drain region in an element forming area in the memory cell area.
- photoresist pattern 104 d is removed.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
- Non-Volatile Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/076,038 US7858490B2 (en) | 2004-08-12 | 2008-03-13 | Semiconductor device having dual-STI and manufacturing method thereof |
| US12/946,311 US8294236B2 (en) | 2004-08-12 | 2010-11-15 | Semiconductor device having dual-STI and manufacturing method thereof |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004235434 | 2004-08-12 | ||
| JP2004-235434(P). | 2004-08-12 | ||
| JP2005-214776(P). | 2005-07-25 | ||
| JP2005214776A JP4947931B2 (ja) | 2004-08-12 | 2005-07-25 | 半導体装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/076,038 Division US7858490B2 (en) | 2004-08-12 | 2008-03-13 | Semiconductor device having dual-STI and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20060035437A1 true US20060035437A1 (en) | 2006-02-16 |
Family
ID=35800496
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/200,262 Abandoned US20060035437A1 (en) | 2004-08-12 | 2005-08-10 | Semiconductor device having dual-STI and manufacturing method thereof |
| US12/076,038 Expired - Lifetime US7858490B2 (en) | 2004-08-12 | 2008-03-13 | Semiconductor device having dual-STI and manufacturing method thereof |
| US12/946,311 Expired - Fee Related US8294236B2 (en) | 2004-08-12 | 2010-11-15 | Semiconductor device having dual-STI and manufacturing method thereof |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/076,038 Expired - Lifetime US7858490B2 (en) | 2004-08-12 | 2008-03-13 | Semiconductor device having dual-STI and manufacturing method thereof |
| US12/946,311 Expired - Fee Related US8294236B2 (en) | 2004-08-12 | 2010-11-15 | Semiconductor device having dual-STI and manufacturing method thereof |
Country Status (4)
| Country | Link |
|---|---|
| US (3) | US20060035437A1 (zh) |
| JP (1) | JP4947931B2 (zh) |
| KR (1) | KR101166268B1 (zh) |
| TW (1) | TWI390665B (zh) |
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-
2005
- 2005-07-25 JP JP2005214776A patent/JP4947931B2/ja not_active Expired - Fee Related
- 2005-08-10 TW TW094127098A patent/TWI390665B/zh not_active IP Right Cessation
- 2005-08-10 US US11/200,262 patent/US20060035437A1/en not_active Abandoned
- 2005-08-11 KR KR1020050073625A patent/KR101166268B1/ko not_active Expired - Fee Related
-
2008
- 2008-03-13 US US12/076,038 patent/US7858490B2/en not_active Expired - Lifetime
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2010
- 2010-11-15 US US12/946,311 patent/US8294236B2/en not_active Expired - Fee Related
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Also Published As
| Publication number | Publication date |
|---|---|
| TW200614418A (en) | 2006-05-01 |
| JP2006080492A (ja) | 2006-03-23 |
| KR20060050398A (ko) | 2006-05-19 |
| KR101166268B1 (ko) | 2012-07-17 |
| US8294236B2 (en) | 2012-10-23 |
| US20110057287A1 (en) | 2011-03-10 |
| TWI390665B (zh) | 2013-03-21 |
| US20080213971A1 (en) | 2008-09-04 |
| JP4947931B2 (ja) | 2012-06-06 |
| US7858490B2 (en) | 2010-12-28 |
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