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US20050280459A1 - Flip-flop circuit - Google Patents

Flip-flop circuit Download PDF

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Publication number
US20050280459A1
US20050280459A1 US11/136,557 US13655705A US2005280459A1 US 20050280459 A1 US20050280459 A1 US 20050280459A1 US 13655705 A US13655705 A US 13655705A US 2005280459 A1 US2005280459 A1 US 2005280459A1
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Prior art keywords
state
signal
inverter
timing signal
tri
Prior art date
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Abandoned
Application number
US11/136,557
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English (en)
Inventor
Genichiro Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
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Matsushita Electric Industrial Co Ltd
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Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INOUE, GENICHIRO
Publication of US20050280459A1 publication Critical patent/US20050280459A1/en
Priority to US11/978,201 priority Critical patent/US7492202B2/en
Assigned to PANASONIC CORPORATION reassignment PANASONIC CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the primary-secondary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the primary-secondary type
    • H03K3/35625—Bistable circuits of the primary-secondary type using complementary field-effect transistors

Definitions

  • the present invention mainly relates to flip-flop circuits constituted by transistors formed as semiconductor integrated circuits (LSIs).
  • LSIs semiconductor integrated circuits
  • LSI circuits for use in synchronous digital signal processing are designed to use flip-flop circuits as necessary components. Therefore, to achieve faster LSI circuits, every manufacturer has to increase the speed of flip-flop circuits.
  • the flip-flop circuit includes: a master portion 205 including a master latch; a slave portion 206 including a slave latch; and a bypass 207 , as shown in FIG. 5 of this patent.
  • the master portion 205 includes a pass gate 310 , an inverter 311 and an inverter 312 .
  • the master portion 205 holds data input from a data input terminal 209 in synchronization with a clock signal input from a clock signal input terminal while the clock signal is at an H (high) level.
  • the slave portion 206 holds data output from the master portion 205 and allows the data to be output via an inverter 315 and a pass gate 519 while the clock signal is at an L (low) level.
  • the bypass 207 includes an inverter 316 and a pass gate 317 .
  • the bypass 207 outputs data held in the master portion 205 while the clock signal is at the H (high) level.
  • the pass gate 317 of the bypass 207 allows data to pass through.
  • the pass gate 519 of the slave portion 206 allows data to pass through and to be output from a data output terminal 208 . In this manner, at the rising edge of the clock signal, data from the master portion 205 is output via the bypass 207 , which operates faster than the slave portion 206 , thereby enabling the data to be output from the data output terminal 208 in a short time.
  • the flip-flop circuit has a drawback in which it is difficult to design and develop a circuit including such a flip-flop circuit in a short period.
  • the input capacitance at the data input terminal 209 is described as follows.
  • the clock signal is “1” (e.g., at the H level)
  • the pass gate 310 at the input of the master portion 205 is closed. Accordingly, the input capacitance at the data input terminal 209 is equal to the source capacitance of the pass gate 310 .
  • the clock signal is “0” (e.g., at the L level)
  • the pass gate 310 is open.
  • the input capacitance at the data input terminal 209 is equal to the sum of the source and drain capacitances of the pass gate 310 , the gate capacitance of the inverter 311 , the gate capacitance of the inverter 316 and the drain capacitance of the inverter 312 , i.e., is different from that when the clock signal is “1”.
  • the driving capability at the data output terminal 208 is described as follows.
  • the inverter 315 of the slave portion 206 drives a subsequent circuit connected to the data output terminal 208 (via the pass gate 519 ).
  • the inverter 316 of the bypass 207 drives the subsequent circuit (via the pass gate 317 ) with a driving capability different from that when the clock signal is “0”.
  • a circuit design technique using physical-characteristic-extracted data at a logic gate level i.e., at the level of a circuit such as a flip-flop circuit
  • a circuit design technique using physical-characteristic-extracted data at a transistor level is generally more advantageous than a circuit design technique using physical-characteristic-extracted data at a transistor level.
  • standard cells corresponding to logic gates such as a flip-flop, a NAND, an inverter and an AND are registered in a library. Then, a cell-base design combining these standard cells is applied to design an LSI circuit, thus enabling the LSI circuit to be designed in a short period.
  • a flip-flop circuit includes: an input terminal to which an input signal is input; a master latch portion for holding a signal input from the input terminal immediately before a timing signal changes from a first state to a second state, while the timing signal is in the second state; a slave latch portion for holding a signal input from the master latch portion immediately before the timing signal changes from the second state to the first state, while the timing signal is in the first state; and an output terminal from which a signal according to a signal held in the master latch portion is output when the timing signal is in the second state and a signal according to a signal held in the slave latch portion is output when the timing signal is in the first state.
  • At least one of an input capacitance at the input terminal and a driving capability at the output terminal when the timing signal is in the first state is equal to that when the timing signal is in the second state.
  • a signal input immediately before a timing signal changes from a first state to a second state is output with a short delay and, in addition, input capacitance and/or driving capability are/is constant irrespective of the state of the timing signal. Accordingly, the input capacitance and the driving capability are easily extracted as those of a standard cell and circuit design is completed in a short period.
  • the flip-flop circuit may include a selecting portion for selecting a signal according to a signal held in the master latch portion or the slave latch portion and outputting the selected signal.
  • the selecting portion may be configured by using tri-state elements which have the same driving capability in their active states (i.e., in the states where the outputs thereof are not in high-impedance states) and only one which is active at a time.
  • the selecting portion may be configured by using pass gates only one of which is active at a time and a driver receiving the outputs of these pass gates.
  • An input signal may be input to, for example, a tri-state element, which is not an element such as a pass gate whose electrical connecting state changes, i.e., may be input not to the sources and drains of transistors constituting an element, for example, but only to the gates thereof.
  • a tri-state inverter or an inverter is used as the tri-state element or the driver described above, a signal at a desired level is easily held and output without the use of additional inverter.
  • FIG. 1 is a circuit diagram illustrating a configuration of a flip-flop circuit according to a first embodiment.
  • FIG. 2 is a circuit diagram illustrating a configuration of a flip-flop circuit according to a second embodiment.
  • FIG. 3 is a circuit diagram illustrating a configuration of a flip-flop circuit according to a third embodiment.
  • FIG. 4 is a circuit diagram illustrating a configuration of a flip-flop circuit according to a modified example of the third embodiment.
  • FIG. 5 is a circuit diagram illustrating a configuration of a flip-flop circuit according to a fourth embodiment.
  • FIG. 6 is a circuit diagram illustrating a configuration of a flip-flop circuit according to a fifth embodiment.
  • FIG. 7 is a circuit diagram illustrating a configuration of a flip-flop circuit according to a sixth embodiment.
  • FIG. 1 is a circuit diagram illustrating a flip-flop circuit according to a first embodiment of the present invention.
  • a master latch portion 101 includes: a tri-state inverter 111 ; an inverter 112 ; and an inverter 113 .
  • the master latch portion 101 performs latch operation for allowing data to be written therein when a timing signal input from a timing signal input terminal 104 is “0” (e.g., at an L level) and holding data when the timing signal is “1” (e.g., at an H level).
  • the inverter 112 has a driving capability lower than that of the tri-state inverter 111 .
  • a slave latch portion 102 includes: a pass gate 114 ; an inverter 115 ; and an inverter 116 .
  • the slave latch portion 102 holds data when the timing signal is “0” and allows data to be written therein when the timing signal is “1”.
  • the inverter 116 has a driving capability lower than that of the tri-state inverter 113 connected thereto via the pass gate 114 .
  • a bypass 103 is a signal line for outputting data written and held in the master latch portion 101 such that the data does not pass through the slave latch portion 102 , thus reducing the delay time, as compared to a case where the data is output by way of the slave latch portion 102 .
  • a data output selecting portion 107 includes: a pass gate 117 ; a pass gate 118 ; and an inverter 119 .
  • the data output selecting portion 107 selects one of the output of the slave latch portion 102 and the output of the bypass 103 according to a timing signal input from the timing signal input terminal 104 and allows the selected signal to be output from a data output terminal 106 . More specifically, the output of the slave latch portion 102 is selected when the timing signal is “0” and the output of the bypass 103 is selected when the timing signal is “1”.
  • An inverter 120 generates an inverted signal of a timing signal input from the timing signal input terminal 104 .
  • data (a signal) input from a data input terminal 105 is input to a latch constituted by the inverters 112 and 113 via the tri-state inverter 111 . That is, only the gate terminals of transistors constituting the tri-state inverter 111 are electrically connected to the data input terminal 105 irrespective of the state of the timing signal, so that the input capacitance is kept constant.
  • the output signal from the pass gate 117 or 118 is output to the data output terminal 106 via the inverter 119 . That is, the driving capability of the flip-flop circuit is determined by the driving capability of the inverter 119 and, therefore, is kept constant irrespective of the state of the timing signal.
  • the characteristics of a flip-flop circuit as described above are easily extracted so that the flip-flop circuit is used for a cell-base deign as a standard cell.
  • the use of a cell library including the flip-flop circuit used as such a standard cell enables circuit design to be completed in a short period.
  • the master latch portion 101 When the timing signal is “0”, the master latch portion 101 performs data writing operation so that a signal input from the data input terminal 105 is written in the master latch portion 101 .
  • the slave latch portion 102 performs data holding operation so that the output of the slave latch portion 102 does not change from the state immediately before the timing signal changes to “0”.
  • the bypass 103 transmits the signal written in the master latch portion 101 to the data output selecting portion 107 .
  • the data output selecting portion 107 selects the data output from the slave latch portion 102 and causes the selected data to be output from the data output terminal 106 . That is, irrespective of the value input to the data input terminal 105 , data held in the slave latch portion 102 is continuously output from the data output terminal 106 .
  • the master latch portion 101 shifts from data writing operation to data holding operation so that the value input to the data input terminal 105 immediately before the timing signal transitions from “0” to “1” is held in the master latch portion 101 .
  • the slave latch portion 102 shifts from data holding operation to data writing operation and, after the timing signal has transitioned from “0” to “1”, the output of the master latch portion 101 is written in the slave latch portion 102 .
  • the bypass 103 transmits the signal held in the master latch portion 101 to the data output selecting portion 107 .
  • the data output selecting portion 107 shifts from the state of selecting the output of the slave latch portion 102 to the state of selecting the signal transmitted from the bypass 103 .
  • the state where the value held in the slave latch portion 102 is output from the data output terminal 106 changes to the state where the value input to the data input terminal 105 immediately before the timing signal transitions from “0” to “1” is output by way of the master latch portion 101 and the bypass 103 (i.e., is not output by way of the slave latch portion 102 ).
  • the signal is transmitted by way of the bypass 103 , so that the delay time from the rising edge of the timing signal to the time when the value input to the data input terminal 105 at the rising edge is output from the data output terminal 106 is reduced as compared to the case where the signal is transmitted by way of the slave latch portion 102 .
  • the master latch portion 101 When the timing signal is “1”, the master latch portion 101 performs data holding operation, so that the output of the master latch portion 101 is unchanged.
  • the slave latch portion 102 performs data writing operation. However, since the output of the master latch portion 101 as an input does not change, the output of the slave latch portion 102 does not change either.
  • the bypass 103 continues to transmit the signal held in the master latch portion 101 to the data output selecting portion 107 .
  • the data output selecting portion 107 selects the output of the bypass 103 and outputs the data held in the master latch portion 101 to the data output terminal 106 . That is, irrespective of the value at the data input terminal 105 , data held in the master latch portion 101 is continuously output.
  • the master latch portion 101 shifts from data holding operation to data writing operation. After the timing signal has transitioned from “1” to “0”, the value input to the data input terminal 105 is written in the master latch portion 101 .
  • the slave latch portion 102 shifts from data writing operation to data holding operation and the output of the master latch portion 101 immediately before the timing signal transitions from “1” to “0” is written and held in the slave latch portion 102 .
  • the bypass 103 transmits the signal written in the master latch portion 101 .
  • the data output selecting portion 107 shifts from the state of selecting the signal transmitted from the bypass 103 to the state of selecting the output of the slave latch portion 102 .
  • the value held in the master latch portion 101 when the timing signal is “1” comes to be held in the slave latch portion 102 and is selected by the data output selecting portion 107 . Accordingly, the output from the data output terminal 106 does not change from the state when the timing signal is “1”.
  • the input capacitance and the driving capability are kept constant as described above, so that circuit design is completed in a short period with physical characteristics extracted as those of a standard cell.
  • a master latch portion 201 and a slave latch portion 202 including tri-state inverters 212 and 216 , respectively, may be used as shown in FIG. 2 .
  • the tri-state inverters 212 and a tri-state inverter 111 operate at different states of a timing signal, and the tri-state inverter 216 and a pass gate 114 also operate at different states of the timing signal. Accordingly, the outputs of the tri-state inverter 212 and the tri-state inverter 111 do not conflict with each other, and the outputs of the tri-state inverter 216 and the pass gate 114 do not conflict with each other.
  • a data output selecting portion 307 including tri-state inverters 317 and 318 may be provided as shown in FIG. 3 .
  • the tri-state inverters 317 and 318 select the output of a slave latch portion 102 (i.e., the tri-state inverter 317 is active and the tri-state inverter 318 is in a high-impedance state).
  • the tri-state inverters 317 and 318 select the output from a bypass 103 (i.e., the tri-state inverter 317 is in a high-impedance state and the tri-state inverter 318 is active).
  • the tri-state inverters 317 and 318 have the same driving capability (physical characteristic). Specifically, elements (transistors) constituting these inverters are designed to have the same size and shape, for example. That is, the driving capability of the tri-state inverter 317 does not affect the response ability when the timing signal rises and, therefore, the driving capability can be set small.
  • the tri-state inverter 317 is intentionally designed to have the same driving capability as that of the tri-state inverter 318 so that the driving capability of the flip-flop circuit is unchanged irrespective of which of the tri-state inverters 317 and 318 is active. This also enables easy extraction of physical characteristics as those of a standard cell. The use of a cell library including the flip-flop circuit as such a standard cell enables circuit design to be completed in a short period.
  • an output driver such as an inverter 119 or a buffer may be provided between the tri-state inverters 317 and 318 and a data output terminal 106 as shown in FIG. 4 , as in the first and second embodiments.
  • the driving capability of the flip-flop circuit is kept constant.
  • the tri-state inverters 317 and 318 are designed to have the same driving capability and the inverter 119 and other elements are not provided, the flip-flop circuit operates at a higher speed because of the absence of a delay caused by the inverter 119 and other elements.
  • this flip-flop circuit includes a master latch portion 401 including a tri-state selector 430 instead of the master latch portion 101 including the tri-state inverter 111 of the second embodiment ( FIG. 2 ).
  • An inverted data output terminal 410 is connected to the output of a slave latch portion 202 via serially-connected inverters 431 and 432 so as to output an inverted signal of a signal output from a data output terminal 106 .
  • the tri-state selector 430 includes PMOS transistors (p-type MOS transistors) 420 through 424 and NMOS transistors (n-type MOS transistors) 425 through 429 .
  • PMOS transistors p-type MOS transistors
  • NMOS transistors n-type MOS transistors
  • the tri-state selector 430 outputs an inverted signal of one of a data signal input from a data input terminal 105 and a scanning test signal input from a scanning input terminal 408 according to a scanning control signal input from a scanning control terminal 409 (i.e., operates as a tri-state inverter having a selecting function). More specifically, when the scanning control signal is “0”, the tri-state selector 430 operates as the tri-state inverter 111 shown in FIG. 2 and when the scanning control signal is “1”, the tri-state selector 430 operates in the same manner with respect to a signal input from the scanning input terminal 408 .
  • the inverted signal output from the inverted data output terminal 410 may be generated based on the output of a pass gate 117 or the inverter 119 so as to reduce a delay in the same manner as that for an output signal from the data output terminal 106 .
  • this signal can be generated based on the output of the slave latch portion 202 as described above. This suppresses loads such as a pass gate 118 and easily ensures a high-speed output of a signal from the data output terminal 106 without the need for increasing the driving capability.
  • the output of the inverter 431 may be directly connected to the output terminal (i.e., without insertion of the inverter 432 ) so that signals having the same logic value are individually output from the inverted data output terminal 410 and the data output terminal 106 .
  • the signal output from the data output terminal 106 is only used for driving circuits which need high speed operation whereas the signal output from the inverted data output terminal 410 is used for driving circuits which do not need especially high speed operation.
  • a master latch portion 501 and a slave latch portion 502 including a tri-state inverter 512 and a NAND 515 , respectively, may be provided to implement a reset function.
  • reset operation in which “0” is output from a data output terminal 106 is performed, as in a conventional flip-flop circuit having a reset function.
  • a data input terminal 105 and a scanning input terminal 408 are connected to a tri-state selector 430 and the data output terminal 106 is connected to an inverter 119 as in the fourth embodiment, so that the input capacitance and the driving capability are kept constant irrespective of the state of a timing signal.
  • a master latch portion 601 and a slave latch portion 602 including a NAND 613 and a tri-state NAND 616 , respectively, are provided to implement a set function.
  • set operation in which “1” is output from a data output terminal 106 is performed as in a conventional flip-flop circuit having a set function.
  • the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal, as in the fifth embodiment and other embodiments.
  • a flip-flop circuit operating at the rising edge of a timing signal has been described.
  • a flip-flop circuit operating at a falling edge may be configured.
  • a signal input from the timing signal input terminal 104 and a signal inverted by the inverter 120 from the signal input from the timing signal input terminal 104 may be replaced with each other, for example.
  • a timing signal input from the timing signal input terminal 104 and a signal inverted by the inverter 120 from the timing signal are used as an example.
  • the present invention is not limited to this.
  • a signal inverted by the inverter 120 from the timing signal input from the timing signal input terminal 104 and a further-inverted signal thereof may be used, for example.
  • a signal having the same logic value as that of the signal input from the data input terminal 105 when the timing signal rises is output from the data output terminal 106 .
  • a signal having an inverted logic value thereof may be output.
  • the inverter 119 and tri-state selector 430 for an inverted output for example, a tri-state buffer, a buffer and a tri-state selector for a non-inverted output may be used or an odd number of inverters may be inserted.
  • an element having a function as an inverter or an element having a function as a buffer may be used to make the input capacitance constant irrespective of the state of a timing signal as long as the data input terminal 105 is connected only to the gates of transistors constituting the element.
  • an inverted signal having a small delay may be output based on the output of one of the pass gate 117 and the inverter 119 or a signal having the same logic value as that of a signal output from the data output terminal 106 may be output based on the output of the slave latch portion 102 , in the fifth and sixth embodiments.
  • a signal having the same logic value as that of a signal output from the data output terminal 106 and having a small delay or a signal having the same or inverted logic value and having a relatively large delay may be output in the same manner.
  • the reset state or the set state is established when a signal at the reset terminal 531 or the set terminal 631 is “0”.
  • the present invention is not limited to this, and the reset state or the set state may be established when the signal is “1”.
  • the data output selecting portion 307 including the tri-state inverters 317 and 318 of the third embodiment may be applied to the configuration of the second embodiment ( FIG. 2 ) in which the master latch portion 201 and the slave latch portion 202 including the tri-state inverters 212 and 216 , respectively, are used.
  • the configurations of the fifth and sixth embodiments may be combined together to configure a flip-flop circuit enabling both reset and set. The configuration enabling reset and/or set may be applied to the configurations of the first through third embodiments.
  • the flip-flop circuit including no bypass as described above may be configured by using a tri-state element, for example, at the input of the master latch portion such that the input capacitance does not depend on a timing signal.
  • the flip-flop circuit according to the present invention has an advantage in which physical characteristics at the input and output terminals of the flip-flop circuit are kept constant irrespective of the state of a timing signal such as a clock signal.
  • This flip-flop circuit is useful as a flip-flop circuit constituted by transistors formed as a semiconductor integrated circuit, for example.

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JP2004179954A JP2006005661A (ja) 2004-06-17 2004-06-17 フリップフロップ回路
JP2004-179954 2004-06-17

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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070080714A1 (en) * 2005-09-29 2007-04-12 Hynix Semiconductor Inc. Flip-flop circuit
US7256620B2 (en) * 2002-11-28 2007-08-14 Fujitsu Limited Selector circuit and semiconductor device
US20070247197A1 (en) * 2006-03-31 2007-10-25 Masleid Robert P Multi-write memory circuit with a data input and a clock input
US20080007312A1 (en) * 2006-07-06 2008-01-10 Clark Lawrence T Sequential circuit design for radiation hardened multiple voltage integrated circuits
US20080048758A1 (en) * 2006-07-13 2008-02-28 Daisuke Matsuoka Output control circuit
EP2309281A1 (fr) * 2009-10-09 2011-04-13 STMicroelectronics SA Bascule à phase d'horloge unique et à puissance dynamique réduite.
US20110202805A1 (en) * 2010-02-16 2011-08-18 Seningen Michael R Pulse Dynamic Logic Gates With Mux-D Scan Functionality
US20120146697A1 (en) * 2010-12-13 2012-06-14 Leach Derrick A Scannable flip-flop with hold time improvements
US20120212269A1 (en) * 2011-02-18 2012-08-23 Oracle International Corporation Single-inversion pulse flop
US20140359385A1 (en) * 2013-05-29 2014-12-04 Qualcomm Incorporated Circuit and layout techniques for flop tray area and power otimization
US20190126631A1 (en) * 2016-04-29 2019-05-02 Hewlett-Packard Development Company, L.P. Printing apparatus and methods for detecting fluid levels
US20190372563A1 (en) * 2018-06-04 2019-12-05 Little Dragon IP Holding LLC Low power flip-flop circuit
US20200106424A1 (en) * 2018-09-27 2020-04-02 Apple Inc. Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges
EP3751298A1 (en) * 2019-06-09 2020-12-16 NXP USA, Inc. Register for at-speed scan testing
US11115009B2 (en) 2018-01-16 2021-09-07 Nuvoton Technology Corporation Japan Semiconductor integrated circuit
US20240014811A1 (en) * 2020-03-31 2024-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Gated tri-state inverter, and method of operating same

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7776037B2 (en) * 2006-07-07 2010-08-17 Covidien Ag System and method for controlling electrode gap during tissue sealing
US7855574B2 (en) * 2006-10-10 2010-12-21 Altera Corporation Programmable multiple supply regions with switched pass gate level converters
JP4297159B2 (ja) * 2006-12-08 2009-07-15 ソニー株式会社 フリップフロップおよび半導体集積回路
JP5223302B2 (ja) * 2007-11-08 2013-06-26 富士通セミコンダクター株式会社 半導体装置
US8072252B2 (en) * 2008-07-11 2011-12-06 Advanced Micro Devices, Inc. Compound logic flip-flop having a plurality of input stages
TWI632551B (zh) * 2010-12-03 2018-08-11 半導體能源研究所股份有限公司 積體電路，其驅動方法，及半導體裝置
KR101247268B1 (ko) * 2011-08-01 2013-03-25 에스케이하이닉스 주식회사 반도체 장치
WO2013177759A1 (en) * 2012-05-30 2013-12-05 Qualcomm Incorporated. Reduced dynamic power d flip-flop
US9793881B2 (en) * 2013-08-05 2017-10-17 Samsung Electronics Co., Ltd. Flip-flop with zero-delay bypass mux
CN104796113A (zh) * 2014-01-17 2015-07-22 苏州芯动科技有限公司 降低亚稳态发生式d触发器设备
CN104796132B (zh) * 2014-01-22 2017-12-22 陈祺琦 一种触发器电路
CN103996371B (zh) * 2014-05-30 2016-04-13 京东方科技集团股份有限公司 显示驱动电路、阵列基板及触摸显示装置
CN104360781B (zh) * 2014-11-12 2017-10-03 京东方科技集团股份有限公司 触控电极的驱动单元、驱动电路、触控面板及驱动方法
CN104658508B (zh) * 2015-03-24 2017-06-09 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN105096900B (zh) 2015-09-23 2019-01-25 深圳市华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
TWI575875B (zh) * 2015-10-29 2017-03-21 智原科技股份有限公司 正反器電路
US9787292B2 (en) * 2016-01-21 2017-10-10 Globalfoundries Inc. High performance multiplexed latches
CN108494382B (zh) * 2018-02-05 2019-10-25 宁波大学 一种基于FinFET晶体管的钟控D触发器
CN108494383A (zh) * 2018-02-11 2018-09-04 宁波大学 一种基于FinFET器件的钟控D触发器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656962A (en) * 1994-11-30 1997-08-12 Intel Corporation Master-slave flip-flop circuit with bypass
US5905393A (en) * 1997-10-06 1999-05-18 Motorola, Inc. Unbuffered latch resistant to back-writing and method of operation therefor
US6614276B2 (en) * 2000-06-06 2003-09-02 Texas Instruments Incorporated Flip-flop design
US20030218231A1 (en) * 2002-05-24 2003-11-27 Sani Mehdi Hamidi Non-volatile multi-threshold CMOS latch with leakage control

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224319A (ja) 1984-04-20 1985-11-08 Seiko Epson Corp フリツプ・フロツプ回路
JP3204690B2 (ja) 1991-09-03 2001-09-04 株式会社東芝 マルチモード入力回路
JPH05152904A (ja) 1991-11-27 1993-06-18 Fujitsu Ltd 半導体装置
EP0567716A1 (en) * 1992-04-30 1993-11-03 STMicroelectronics S.r.l. Static edgetriggered D flip-flop with a low power consumption
JPH08195650A (ja) 1995-01-13 1996-07-30 Nec Corp マスタスレーブ方式フリップフロップ回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656962A (en) * 1994-11-30 1997-08-12 Intel Corporation Master-slave flip-flop circuit with bypass
US5905393A (en) * 1997-10-06 1999-05-18 Motorola, Inc. Unbuffered latch resistant to back-writing and method of operation therefor
US6614276B2 (en) * 2000-06-06 2003-09-02 Texas Instruments Incorporated Flip-flop design
US20030218231A1 (en) * 2002-05-24 2003-11-27 Sani Mehdi Hamidi Non-volatile multi-threshold CMOS latch with leakage control

Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7256620B2 (en) * 2002-11-28 2007-08-14 Fujitsu Limited Selector circuit and semiconductor device
US7427875B2 (en) * 2005-09-29 2008-09-23 Hynix Semiconductor Inc. Flip-flop circuit
US20070080714A1 (en) * 2005-09-29 2007-04-12 Hynix Semiconductor Inc. Flip-flop circuit
US8067970B2 (en) * 2006-03-31 2011-11-29 Masleid Robert P Multi-write memory circuit with a data input and a clock input
US20070247197A1 (en) * 2006-03-31 2007-10-25 Masleid Robert P Multi-write memory circuit with a data input and a clock input
US20080007312A1 (en) * 2006-07-06 2008-01-10 Clark Lawrence T Sequential circuit design for radiation hardened multiple voltage integrated circuits
US7622976B2 (en) * 2006-07-06 2009-11-24 Stc.Unm Sequential circuit design for radiation hardened multiple voltage integrated circuits
US20080048758A1 (en) * 2006-07-13 2008-02-28 Daisuke Matsuoka Output control circuit
US20100109703A1 (en) * 2006-07-13 2010-05-06 Panasonic Corporation Output control circuit
US8339172B2 (en) 2009-10-09 2012-12-25 Stmicroelectronics Sa Flip-flop with single clock phase and with reduced dynamic power
FR2951337A1 (fr) * 2009-10-09 2011-04-15 St Microelectronics Sa Bascule a phase d'horloge unique et a puissance dynamique reduite
US20110084748A1 (en) * 2009-10-09 2011-04-14 Stmicroelectronics Sa Flip-flop with single clock phase and with reduced dynamic power
EP2309281A1 (fr) * 2009-10-09 2011-04-13 STMicroelectronics SA Bascule à phase d'horloge unique et à puissance dynamique réduite.
US20110202805A1 (en) * 2010-02-16 2011-08-18 Seningen Michael R Pulse Dynamic Logic Gates With Mux-D Scan Functionality
US20110202810A1 (en) * 2010-02-16 2011-08-18 Seningen Michael R Pulse dynamic logic gates with lssd scan functionality
US8555121B2 (en) 2010-02-16 2013-10-08 Apple Inc. Pulse dynamic logic gates with LSSD scan functionality
US8677199B2 (en) 2010-02-16 2014-03-18 Apple Inc. Pulse dynamic logic gates with mux-D scan functionality
US20120146697A1 (en) * 2010-12-13 2012-06-14 Leach Derrick A Scannable flip-flop with hold time improvements
US8493119B2 (en) * 2010-12-13 2013-07-23 Apple Inc. Scannable flip-flop with hold time improvements
US20120212269A1 (en) * 2011-02-18 2012-08-23 Oracle International Corporation Single-inversion pulse flop
US8674739B2 (en) * 2011-02-18 2014-03-18 Oracle International Corporation Single-inversion pulse flop
US9024658B2 (en) * 2013-05-29 2015-05-05 Qualcomm Incorporated Circuit and layout techniques for flop tray area and power otimization
US20140359385A1 (en) * 2013-05-29 2014-12-04 Qualcomm Incorporated Circuit and layout techniques for flop tray area and power otimization
US20190126631A1 (en) * 2016-04-29 2019-05-02 Hewlett-Packard Development Company, L.P. Printing apparatus and methods for detecting fluid levels
US10926548B2 (en) * 2016-04-29 2021-02-23 Hewlett-Packard Development Company, L.P. Printing apparatus and methods for detecting fluid levels
US11115009B2 (en) 2018-01-16 2021-09-07 Nuvoton Technology Corporation Japan Semiconductor integrated circuit
US20190372563A1 (en) * 2018-06-04 2019-12-05 Little Dragon IP Holding LLC Low power flip-flop circuit
US10715119B2 (en) * 2018-06-04 2020-07-14 Little Dragon IP Holding LLC Low power flip-flop circuit
US20200106424A1 (en) * 2018-09-27 2020-04-02 Apple Inc. Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges
US11303268B2 (en) * 2018-09-27 2022-04-12 Apple Inc. Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges
EP3751298A1 (en) * 2019-06-09 2020-12-16 NXP USA, Inc. Register for at-speed scan testing
US10948538B2 (en) * 2019-06-09 2021-03-16 Nxp Usa, Inc. Register for at-speed scan testing
US20240014811A1 (en) * 2020-03-31 2024-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Gated tri-state inverter, and method of operating same
US12362737B2 (en) * 2020-03-31 2025-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Gated tri-state inverter, and method of operating same

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US7492202B2 (en) 2009-02-17
JP2006005661A (ja) 2006-01-05

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