[go: up one dir, main page]

US20050180205A1 - Magnetic random access memory and method of reading data from the same - Google Patents

Magnetic random access memory and method of reading data from the same Download PDF

Info

Publication number
US20050180205A1
US20050180205A1 US11/025,841 US2584104A US2005180205A1 US 20050180205 A1 US20050180205 A1 US 20050180205A1 US 2584104 A US2584104 A US 2584104A US 2005180205 A1 US2005180205 A1 US 2005180205A1
Authority
US
United States
Prior art keywords
cell
mtj
memory cell
reference cell
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/025,841
Other languages
English (en)
Inventor
Wan-jun Park
Tae-Wan Kim
Sang-jin Park
Dae-Jeong Kim
Seung-Jun Lee
Hyung-soon Shin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, DAE-JEONG, KIM, TAE-WAN, LEE, SEUNG-JUN, PARK, SANG-JIN, PARK, WAN-JUN, SHIN, HYUNG-SOON
Publication of US20050180205A1 publication Critical patent/US20050180205A1/en
Priority to US12/230,855 priority Critical patent/US8320166B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators

Definitions

  • the present invention relates to a semiconductor memory device and a method of reading data from the same. More particularly, the present invention relates to a magnetic random access memory (MRAM) having a reference cell that is capable of maintaining a middle resistance between a high resistance and a low resistance of a magnetic tunneling junction (MTJ) layer according to changes in a resistance of the MTJ layer caused by an applied voltage and a method of reading data from the MRAM.
  • MRAM magnetic random access memory
  • MTJ magnetic tunneling junction
  • a magnetic tunneling junction (MTJ) layer of a memory cell of an MRAM has a resistance that varies according to the direction of magnetization of a free magnetic film.
  • the MTJ layer has a low resistance R L .
  • the MTJ layer has a high resistance R H .
  • the high resistance is referred to as a maximum resistance of the MTJ layer, and the low resistance is referred to as a minimum resistance of the MTJ layer.
  • An MRAM is a memory device that stores data “1” and “0” using the fact that the resistance of the MTJ layer is different according to the state of magnetization of the free magnetic film.
  • the MRAM includes a reference cell having a resistance (R H +R L )/2 (hereinafter, referred to as a middle resistance) that corresponds to an average resistance of the high resistance R H and the low resistance R L of the MTJ layer.
  • the reference cell includes a transistor and an MTJ layer connected to the transistor.
  • the middle resistance of the reference cell is the resistance of the MTJ layer provided in the reference cell.
  • the resistances R H and R L of the MTJ layer vary according to a voltage applied to the MTJ layer.
  • FIG. 1 which is a graph of an ideal voltage versus resistance of a magnetic tunneling junction (MTJ) layer of a memory cell of an MRAMand an MTJ layer of a reference cell
  • the resistance of the MTJ layer of the reference cell of the MRAM which is represented by a solid line, should be constant at a middle resistance (R H +R L )/2 between a low resistance R L ( ⁇ ) and a high resistance R H ( ⁇ ) of the MTJ layer of the memory cell according to a voltage applied to the reference cell.
  • FIGS. 2, 5 , and 7 are circuit diagrams of a memory cell and a reference cell of a conventional MRAM.
  • FIG. 3 is a graph of voltage versus resistance of an MTJ layer of a memory cell and an MTJ layer of a reference cell of the conventional MRAM of FIG. 2 .
  • FIG. 4 is a graph of voltage versus current of an MTJ layer of a memory cell and an MTJ layer of a reference cell of the conventional MRAM of FIG. 2 .
  • FIG. 6 is a graph of voltage versus current of an MTJ layer of a memory cell and an MTJ layer of a reference cell of the conventional MRAM of FIG. 5 .
  • the reference cell of the conventional MRAM includes first through fourth MTJ layers 12 , 14 , 16 , and 18 and a first transistor 10 , as shown on the left side of a sensor amplifier (SA) in FIG. 2 .
  • a memory cell including a fifth MTJ layer 20 and a second transistor 24 is shown on the right side of the sensor amplifier SA in FIG. 2 .
  • a resistance is measured from an MTJ layer. Accordingly, in FIG. 2 , each of the MTJ layers is indicated by a resistance.
  • MTJ layers in all circuits are indicated by a resistance.
  • the first and second MTJ layers 12 and 14 have a high resistance R H and a low resistance R L , respectively.
  • the third and fourth MTJ layers 16 and 18 have a low resistance R L and a high resistance R H , respectively.
  • the first and second MTJ layers 12 and 14 are connected in series to each other.
  • the third and fourth MTJ layers 16 and 18 are also connected in series to each other.
  • the first and second MTJ layers 12 and 14 and the third and fourth MTJ layers 16 and 18 are connected in parallel to each other.
  • the first transistor 10 is connected between the second and fourth MTJ layers 14 and 18 .
  • V Ref and V Cell are a voltage measured in the reference cell and a voltage measured in the memory cell, respectively.
  • a conventional MRAM including the reference cell and the memory cell shown in FIG. 2 reads information stored in the memory cell using a difference between the voltages V Ref and V Cell .
  • the current I s supplied to the reference cell from a current source is divided by two such that a current I s /2 is supplied to each of the first and second MTJ layers 12 and 14 and the third and fourth MTJ layers 16 and 18 .
  • the voltage applied to each MTJ layer of the reference cell is about half of the voltage applied to the fifth MTJ layer 20 of the memory cell. For this reason, it is difficult to maintain the equivalent resistance of the reference cell at (R H +R L )/2, as shown in FIG. 3 .
  • symbol ⁇ is a graph showing a voltage V Cell, H measured when the fifth MTJ layer 20 has a high resistance
  • symbol ⁇ is a graph showing a voltage V Cell, L measured when the fifth MTJ layer 20 has a low resistance
  • a solid line is a graph showing a voltage V Ref measured in the reference cell.
  • the voltage V Ref measured in the reference cell is different from (V Cell, H+V cell, L)/2.
  • the voltage measured in the reference cell does not have a middle value between a maximum voltage and a minimum voltage measured in the memory cell, in a case of the conventional MRAM having the memory cell and the reference cell of FIG. 2 , a sensing margin is reduced such that noise or malfunction may occur.
  • the reference cell and the memory cell of FIG. 5 are the same as the reference cell and the memory cell of FIG. 2 in constitution, but a voltage V s instead of a current is applied to the reference cell and the memory cell.
  • an MRAM having the reference cell and the memory cell of FIG. 5 reads information recorded in the memory cell using a difference between a current I Ref measured in the reference cell and a current I Cell measured in the memory cell.
  • voltages applied to each of the first through fourth MTJ layers 12 , 14 , 16 , and 18 of the reference cell are about half of a voltage applied to the fifth MTJ layer 20 of the memory cell.
  • symbol ⁇ is a graph showing maximum currents I Cell, H measured in the memory cell
  • symbol ⁇ is a graph showing minimum currents I Cell, L measured in the memory cell
  • a solid line is a graph showing a current I Ref measured in the reference cell.
  • the current I Ref measured in the reference cell is very different from a middle value (I Cell, H+I Cell, L)/2 between the maximum currents I Cell, H and the minimum currents I Cell, L measured in the memory cell according to an applied voltage.
  • FIG. 7 shows an MRAM having a reference cell including sixth and seventh MTJ layers 26 and 28 , and the first transistor 10 .
  • the sixth MTJ layer 26 has a low resistance R L
  • the seventh MTJ layer 28 has a resistance R H higher than the resistance of the sixth MTJ layer 26 .
  • the sixth and seventh MTJ layers 26 and 28 are connected in parallel to each other, and the first transistor 10 is connected between the sixth and seventh MTJ layers 26 and 28 .
  • a voltage 0.5Vs which corresponds to 1 ⁇ 2 of a voltage V s supplied to the memory cell, is applied to the reference cell.
  • the voltage 0.5V s applied to the two MTJ layers 26 and 28 of the reference cell is about half of the voltage V s applied to the fifth MTJ layer 20 of the memory cell, it is difficult to maintain the equivalent resistance of the reference cell at (R H +R L )/2.
  • the current I Ref measured in the reference cell of the MRAM of FIG. 7 cannot be maintained at a middle value (I Cell, H+I Cell, L)/ 2 between the maximum current I Cell, H and the minimum current I Cell, L measured in the memory cell, as shown in FIG. 6 .
  • a sensing margin is reduced such that noise or malfunction may occur.
  • the present invention is therefore directed to a magnetic random access memory (MRAM) and a method of reading data from the MRAM, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
  • MRAM magnetic random access memory
  • MRAM magnetic random access memory
  • MRAM magnetic random access memory
  • MTJ magnetic tunneling junction
  • reference cell includes first and second MTJ layers provided in parallel to each other, and first and second transistors provided in parallel to each other, the first and second transistors being respectively connected in series to the first and second MTJ layers.
  • a magnetic random access memory including a memory cell having one transistor and one magnetic tunneling junction (MTJ) layer, and a reference cell that is operable for use as a basis when reading data stored in the memory cell, wherein the reference cell includes first and second MTJ layers provided in parallel to each other, and a first transistor connected in series to the first and second MTJ layers, and wherein a driving capability of the first transistor of the reference cell is twice a driving capability of the transistor of the memory cell.
  • MRAM magnetic random access memory
  • MTJ magnetic tunneling junction
  • one of the first and second MTJ layers of the reference cell may have a maximum resistance of the MTJ layer of the memory cell, and the other of the first and second MTJ layers of the reference cell may have a minimum resistance of the MTJ layer of the memory cell.
  • At least one of the above and other features and advantages of the present invention may be realized by providing a method of reading data from a magnetic random access memory (MRAM) including a memory cell having one transistor and one magnetic tunneling junction (MTJ) layer, and a reference cell having first and second MTJ layers provided in parallel to each other and first and second transistors provided in parallel to each other, the first and second transistors of the reference cell being connected in series to the first and second MTJ layers, respectively, the method including applying a read current I s to the memory cell, and applying a current 21 , corresponding to twice the read current to the reference cell.
  • MRAM magnetic random access memory
  • MTJ magnetic tunneling junction
  • At least one of the above and other features and advantages of the present invention may be realized by providing a method of reading data from a magnetic random access memory (MRAM) including a memory cell having one transistor and one magnetic tunneling junction (MTJ) layer, and a reference cell having first and second MTJ layers connected in parallel to each other and a first transistor which is connected in series to the first and second MTJ layers, the first transistor having a driving capability corresponding to twice a driving capability of the transistor of the memory cell, the method including applying a read current I s to the memory cell, and applying a current 2 I s corresponding to twice the read current to the reference cell.
  • MRAM magnetic random access memory
  • MTJ magnetic tunneling junction
  • the equivalent resistance of the MTJ layer of the reference cell is maintained at the middle value between the maximum resistance and the minimum resistance of the MTJ layer of the memory cell even though the applied voltage varies, thereby sufficiently providing a sensing margin and preventing a malfunction caused by noise.
  • FIG. 1 is a graph of an ideal voltage versus resistance of a magnetic tunneling junction (MTJ) layer of a memory cell of an MRAM and an MTJ layer of a reference cell;
  • MTJ magnetic tunneling junction
  • FIGS. 2, 5 , and 7 are circuit diagrams of a memory cell and a reference cell of conventional MRAMs
  • FIG. 3 is a graph of voltage versus resistance of an MTJ layer of a memory cell and an MTJ layer of a reference cell of the conventional MRAM of FIG. 2 ;
  • FIG. 4 is a graph of voltage versus current of an MTJ layer of a memory cell and an MTJ layer of a reference cell of the conventional MRAM of FIG. 2 ;
  • FIG. 6 is a graph of voltage versus current of an MTJ layer of a memory cell and an MTJ layer of a reference cell of the conventional MRAM of FIG. 5 ;
  • FIG. 8 is a circuit diagram of a memory cell and a reference cell of an MRAM according to an embodiment of the present invention.
  • FIG. 9 is a graph of voltage versus resistance of an MTJ layer of a memory cell and an MTJ layer of a reference cell of the MRAM of FIG. 8 ;
  • FIG. 10 is a graph of voltage versus current of an MTJ layer of a memory cell and an MTJ layer of a reference cell of the MRAM of FIG. 8 ;
  • FIG. 11 is a circuit diagram of an array of a memory cell and a reference cell of an MRAM according to an embodiment of the present invention.
  • FIG. 12 is a circuit diagram showing the flow of a current applied to a memory cell and a reference cell corresponding to the memory cell in the memory cell array of FIG. 11 .
  • FIG. 8 is a circuit diagram of a memory cell and a reference cell of an MRAM according to an embodiment of the present invention.
  • FIG. 8 shows a circuit constitution for a memory cell C 2 and a reference cell C 1 corresponding to the memory cell C 2 of the MRAM according to an embodiment of the present invention.
  • the reference cell is operable for use as a basis when reading data stored in the memory cell.
  • the reference cell Cl includes first and second MTJ layers 50 and 52 and first and second transistors 54 and 56 .
  • the memory cell C 2 includes a third MTJ layer 58 and a third transistor 60 .
  • the first MTJ layer 50 has a low resistance and may be the same resistance as a minimum resistance of the third MTJ layer 58 of the memory cell C 2 .
  • the second MTJ layer 52 of the reference cell C 1 has a resistance higher than the resistance of the first MTJ layer 50 .
  • the resistance of the second MTJ layer 52 may be the same as a maximum resistance of the third MTJ layer 58 .
  • the above-described relation between the first and second MTJ layers 50 and 52 of the reference cell C 1 may be reversed.
  • the first and second MTJ layers 50 and 52 of the reference cell C 1 are connected in parallel to each other, and the first and second transistors 54 and 56 of the reference cell C 1 are connected in parallel to each other.
  • the first MTJ layer 50 and the first transistor 54 are connected in series to each other.
  • the second MTJ layer 52 and the second transistor 56 are also connected in series to each other.
  • the first and second transistors 54 and 56 of the reference cell C 1 may be the same as the third transistor 60 of the memory cell C 2 .
  • a predetermined read current I s is applied to the memory cell C 2 from a current source and, simultaneously, a current 2 I s which corresponds to twice the read current I s , is applied to the reference cell C 1 .
  • Voltages V Ref and V Cell measured in the reference cell C 1 and the memory cell C 2 are compared with each other to read data stored in the memory cell C 2 .
  • the current 2 I s applied to the reference cell C 1 is divided so that the same current as the current I s applied to the memory cell C 2 is applied to each of the first and second MTJ layers 50 and 52 .
  • the first and second transistors 54 and 56 which are the same as a pass transistor of the memory cell C 2 , i.e., the third transistor 60 , are respectively connected in series to the first and second MTJ layers 50 and 52 of the reference cell C 1 , the voltage applied to the first and second MTJ layers 50 and 52 of the reference cell C 1 is substantially similar to the voltage applied to the third MTJ layer 58 of the memory cell C 2 .
  • the equivalent resistance of the reference cell C 1 may be maintained at a middle value between a maximum resistance R H and a minimum resistance R L of the third MTJ layer 58 of the memory cell C 1 even though an applied voltage varies.
  • FIG. 9 shows this result in the reference cell C 1 .
  • FIG. 9 is a graph of voltage versus resistance of the MTJ layer of the memory cell and the MTJ layers of the reference cell of the MRAM of FIG. 8 .
  • symbol ⁇ plots changes in the maximum resistance of the third MTJ layer 58 of the memory cell C 2 according to an applied voltage
  • symbol ⁇ plots changes in the minimum resistance of the third MTJ layer 58
  • a solid line shows changes in the resistance measured in the reference cell C 1 .
  • the resistance measured in the reference cell C 1 is maintained at a middle value between the maximum resistance and the minimum resistance of the third MTJ layer 58 of the memory cell C 2 , even though the applied voltage varies.
  • the voltage V Ref of the reference cell C 1 can be constantly maintained at a middle value (V Cell, H+V Cell, L)/2 between the maximum voltage V Cell, H and the minimum voltage V Cell, L of the memory cell C 2 even though the applied voltage varies.
  • FIG. 10 shows this result.
  • FIG. 10 is a graph of voltage versus current of the MTJ layer of the memory cell and the MTJ layers of the reference cell of the MRAM of FIG. 8 .
  • symbol ⁇ plots changes in the maximum resistance V Cell, H of the memory cell C 2 according to an applied voltage
  • symbol ⁇ plots changes in the minimum resistance V Cell, L of the memory cell C 2 according to the applied voltage
  • a solid line shows changes in the resistance measured in the reference cell C 1 according to the applied voltage.
  • the voltage of the reference cell C 1 is a middle value between the maximum voltage V Cell, H and the minimum voltage V Cell, L of the memory cell C 2 at any applied voltage. Based on this result, by using an MRAM according to an embodiment of the present invention, a sufficient sensing margin can be obtained so that data can be stably read without malfunction.
  • a reference cell according to an alternative embodiment of the present invention may substitute one transistor for the first and second transistors 54 and 56 in the reference cell C 1 of FIG. 8 .
  • the one transistor is a pass transistor. Since a current that passes through two MTJ layers 50 and 52 connected in parallel passes through the one substituted transistor, the driving capability of the one substituted transistor may be twice the driving capability of the third transistor 60 in the memory cell C 2 .
  • a process of reading data from the memory cell C 2 is the same as a process to be performed by the MRAM including the reference cell C 1 .
  • each MTJ layer and the position of each transistor may be reversed from the reference cell C 1 of FIG. 8 .
  • FIG. 11 is a circuit diagram of an array of a memory cell and a reference cell of an MRAM according to an embodiment of the present invention.
  • FIG. 12 is a circuit diagram showing the flow of a current applied to a memory cell and a reference cell corresponding to the memory cell in a memory cell array of FIG. 11 .
  • FIG. 11 shows a cell array of an MRAM including the above-described alternative reference cell and memory cell.
  • a reference cell column 100 includes a plurality of alternative reference cells.
  • One reference cell column 100 is disposed in each memory cell block.
  • a current 2 I s which corresponds to twice a current I s applied to a memory cell column, is applied to the reference cell column 100 .
  • One column of a memory cell block is selected by column select transistors Y 0 , Y 1 , Y 2 , and Y 3 disposed under the cell array and is compared with the reference cell column 100 .
  • a digit line DL is used in recording data in an MTJ layer of the memory cell. When a current is applied to the digit line DL, a ground line GL is floated so that a current does not flow through a pass transistor connected to the MTJ layer.
  • FIG. 12 shows a path through which a current applied to a corresponding memory cell and the reference cell column 100 flows, so as to read data stored in a memory cell connected to a predetermined selected word line, e.g., a first word line WL 0 , of the MRAM array of FIG. 11 .
  • a left circuit is a memory cell of a memory cell column to which a read current I s is applied and which is connected to the first word line WL 0
  • a right circuit is the alternative reference cell of the reference cell column 100 to which a current 2 I s corresponding to twice the read current I s is applied and which is connected to the first word line WL 0 .
  • the read current I s applied to the memory cell connected to the first word line WL 0 passes through an MTJ layer 102 of the memory cell and a transistor MT 1 connected in series to the MTJ layer 102 and flows through a ground line GL connected to the transistor MT 1 .
  • the current 2 I s applied to the reference cell column 100 is divided into two at a first node N 1 so that first and second currents I 1 s and I 2 s are applied to two parallel-connected MTJ layers 106 and 108 .
  • the first and second currents I 1 s and I 2 s have the same value.
  • the first current I 2 s applied to the MTJ layer 106 connected to a transistor CT 1 flows through the ground line GL via the transistor CT 1 in an “on” state.
  • the second current I 2 s passes through a second node N 2 , an MTJ layer 108 connected in series to a transistor CT 2 in an off state connected to a second word line WL 1 , a third node N 3 , which is a connection point between the transistor CT 2 and the MTJ layer 108 , a fourth node N 4 , which is a connection point between the transistor CT 1 and the MTJ layer 106 , and the transistor CT 1 connected to the first word line WL 0 and flows through the ground line GL.
  • the driving capability of the transistor CT 1 of the alternative reference cell may be twice the driving capability of a transistor MT 1 of the memory cell.
  • a transistor of the memory cell MT 2 and a transistor of the reference cell CT 2 are connected to the second word line WL 1 .
  • An MTJ layer 104 of the memory cell is connected to the second word line WL 1 .
  • the reference cell of the MRAM according to the present invention includes an MTJ layer having a maximum resistance of an MTJ layer of a memory cell and an MTJ layer having a minimum resistance of an MTJ layer of the memory cell, which are connected in parallel to each other, and two pass transistors connected in series to each MTJ layer and having the same driving capability as the driving capability of a pass transistor of the memory cell.
  • the two pass transistors of the reference cell may be substituted for one pass transistor having a driving capability corresponding to twice a driving capability of the pass transistor of the memory cell.
  • the same current as the current applied to the MTJ layer of the memory cell is applied to each MTJ layer of the reference cell.
  • the equivalent resistance measured in the reference cell is a middle value between the maximum resistance and the minimum resistance measured in the memory cell.
  • a voltage V Ref measured in the reference cell has a middle value between a maximum voltage V Cell, H and a minimum voltage V Cell, L measured in the memory cell even though the applied voltage varies.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)
US11/025,841 2003-12-30 2004-12-30 Magnetic random access memory and method of reading data from the same Abandoned US20050180205A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/230,855 US8320166B2 (en) 2003-12-30 2008-09-05 Magnetic random access memory and method of reading data from the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2003-0100617 2003-12-30
KR10-2003-0100617A KR100528341B1 (ko) 2003-12-30 2003-12-30 자기 램 및 그 읽기방법

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/230,855 Division US8320166B2 (en) 2003-12-30 2008-09-05 Magnetic random access memory and method of reading data from the same

Publications (1)

Publication Number Publication Date
US20050180205A1 true US20050180205A1 (en) 2005-08-18

Family

ID=34698782

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/025,841 Abandoned US20050180205A1 (en) 2003-12-30 2004-12-30 Magnetic random access memory and method of reading data from the same
US12/230,855 Active 2026-02-14 US8320166B2 (en) 2003-12-30 2008-09-05 Magnetic random access memory and method of reading data from the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/230,855 Active 2026-02-14 US8320166B2 (en) 2003-12-30 2008-09-05 Magnetic random access memory and method of reading data from the same

Country Status (5)

Country Link
US (2) US20050180205A1 (zh)
EP (1) EP1564750B1 (zh)
JP (1) JP4634153B2 (zh)
KR (1) KR100528341B1 (zh)
CN (1) CN1681040A (zh)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070268741A1 (en) * 2006-05-22 2007-11-22 Freescale Semiconductor, Inc. Non-volatile memory cell and methods thereof
US20090067233A1 (en) * 2003-12-30 2009-03-12 Samsung Electronics Co., Ltd. Magnetic random access memory and method of reading data from the same
US20100315858A1 (en) * 2009-02-20 2010-12-16 John Lynch Memory architecture with a current controller and reduced power requirements
US20110188305A1 (en) * 2010-02-04 2011-08-04 Magic Technologies, Inc. Read disturb free SMT MRAM reference cell circuit
US20150287458A1 (en) * 2006-07-27 2015-10-08 Micron Technology, Inc. Phase change memory device
US20150302912A1 (en) * 2014-04-21 2015-10-22 Qualcomm Incorporated Method and apparatus for generating a reference for use with a magnetic tunnel junction
US20150332760A1 (en) * 2014-05-19 2015-11-19 Dong-Keun Kim Electronic device
US20180342307A1 (en) * 2016-04-14 2018-11-29 HangZhou HaiCun Information Technology Co., Ltd. Three-Dimensional One-Time-Programmable Memory Comprising Dummy Bit Lines
US11080229B2 (en) * 2016-02-13 2021-08-03 HangZhou HaiCun Information Technology Co., Ltd. Processor for calculating mathematical functions in parallel
US11139025B2 (en) 2020-01-22 2021-10-05 International Business Machines Corporation Multi-level cell threshold voltage operation of one-selector-one-resistor structure included in a crossbar array
US20220180913A1 (en) * 2020-12-07 2022-06-09 Everspin Technologies, Inc. Midpoint sensing reference generation for stt-mram
CN116312677A (zh) * 2021-12-21 2023-06-23 浙江驰拓科技有限公司 Mram阵列结构

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7321507B2 (en) * 2005-11-21 2008-01-22 Magic Technologies, Inc. Reference cell scheme for MRAM
US7453740B2 (en) * 2007-01-19 2008-11-18 International Business Machines Corporation Method and apparatus for initializing reference cells of a toggle switched MRAM device
US7929334B2 (en) * 2009-01-29 2011-04-19 Qualcomm Incorporated In-situ resistance measurement for magnetic random access memory (MRAM)
KR101068573B1 (ko) * 2009-04-30 2011-09-30 주식회사 하이닉스반도체 반도체 메모리 장치
KR101604042B1 (ko) 2009-12-30 2016-03-16 삼성전자주식회사 자기 메모리 및 그 동작방법
US8576617B2 (en) * 2011-11-10 2013-11-05 Qualcomm Incorporated Circuit and method for generating a reference level for a magnetic random access memory element
US8687412B2 (en) * 2012-04-03 2014-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Reference cell configuration for sensing resistance states of MRAM bit cells
CN103035290B (zh) * 2012-11-30 2016-03-30 珠海艾派克微电子有限公司 Eeprom电路、数据读取方法以及非易失性存储器
KR20140108800A (ko) 2013-02-28 2014-09-15 에스케이하이닉스 주식회사 기준 컬럼, 반도체 장치 및 프로세서와 시스템
US9142293B2 (en) * 2013-09-10 2015-09-22 Kabushiki Kaisha Toshiba Resistance change type memory
US8891326B1 (en) * 2013-09-11 2014-11-18 Avalanche Technology, Inc. Method of sensing data in magnetic random access memory with overlap of high and low resistance distributions
KR102169681B1 (ko) 2013-12-16 2020-10-26 삼성전자주식회사 감지 증폭기, 그것을 포함하는 불휘발성 메모리 장치 및 그것의 센싱 방법
US10490270B2 (en) 2015-10-28 2019-11-26 Hewlett Packard Enterprise Development Lp Reference column sensing for resistive memory
US9754639B2 (en) 2015-10-30 2017-09-05 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and reference circuit thereof
CN108288481B (zh) * 2018-01-19 2021-10-01 上海磁宇信息科技有限公司 一种可调电压的mram读出电路
CN108847262A (zh) * 2018-06-05 2018-11-20 王梅玉 存储器的读取电路
CN110277490B (zh) * 2019-06-24 2023-06-09 中国科学院微电子研究所 Stt-mram参考单元及其制备方法及包含该参考单元的芯片
CN114639410A (zh) * 2020-12-15 2022-06-17 浙江驰拓科技有限公司 一种磁性随机存储器及其读电路
JP7789427B1 (ja) * 2024-12-17 2025-12-22 国立大学法人東北大学 不揮発集積回路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020172073A1 (en) * 2001-04-26 2002-11-21 Mitsubishi Denki Kabushiki Kaisha Thin film magnetic memory device capable of conducting stable data read and write operations
US20030103395A1 (en) * 2001-12-03 2003-06-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device reading data based on memory cell passing current during access
US6600690B1 (en) * 2002-06-28 2003-07-29 Motorola, Inc. Sense amplifier for a memory having at least two distinct resistance states
US20030223268A1 (en) * 2002-05-30 2003-12-04 Mitsubishi Denki Kabushiki Kaisha Thin film magnetic memory device having dummy cell

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3127953B2 (ja) * 1996-08-09 2001-01-29 日本電気株式会社 半導体記憶装置
US5734605A (en) * 1996-09-10 1998-03-31 Motorola, Inc. Multi-layer magnetic tunneling junction memory cells
US5953248A (en) * 1998-07-20 1999-09-14 Motorola, Inc. Low switching field magnetic tunneling junction for high density arrays
US6111781A (en) * 1998-08-03 2000-08-29 Motorola, Inc. Magnetic random access memory array divided into a plurality of memory banks
US6055178A (en) * 1998-12-18 2000-04-25 Motorola, Inc. Magnetic random access memory with a reference memory array
US6317376B1 (en) * 2000-06-20 2001-11-13 Hewlett-Packard Company Reference signal generation for magnetic random access memory devices
US6426907B1 (en) * 2001-01-24 2002-07-30 Infineon Technologies North America Corp. Reference for MRAM cell
JP4434527B2 (ja) * 2001-08-08 2010-03-17 株式会社東芝 半導体記憶装置
US6445612B1 (en) * 2001-08-27 2002-09-03 Motorola, Inc. MRAM with midpoint generator reference and method for readout
TWI223259B (en) * 2003-01-07 2004-11-01 Ind Tech Res Inst A reference mid-point current generator for a magnetic random access memory
KR100528341B1 (ko) * 2003-12-30 2005-11-15 삼성전자주식회사 자기 램 및 그 읽기방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020172073A1 (en) * 2001-04-26 2002-11-21 Mitsubishi Denki Kabushiki Kaisha Thin film magnetic memory device capable of conducting stable data read and write operations
US20030103395A1 (en) * 2001-12-03 2003-06-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device reading data based on memory cell passing current during access
US20030223268A1 (en) * 2002-05-30 2003-12-04 Mitsubishi Denki Kabushiki Kaisha Thin film magnetic memory device having dummy cell
US6600690B1 (en) * 2002-06-28 2003-07-29 Motorola, Inc. Sense amplifier for a memory having at least two distinct resistance states

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090067233A1 (en) * 2003-12-30 2009-03-12 Samsung Electronics Co., Ltd. Magnetic random access memory and method of reading data from the same
US8320166B2 (en) 2003-12-30 2012-11-27 Samsung Electronics Co., Ltd. Magnetic random access memory and method of reading data from the same
US7697321B2 (en) * 2006-05-22 2010-04-13 Everspin Technologies, Inc. Non-volatile memory cell and methods thereof
US20070268741A1 (en) * 2006-05-22 2007-11-22 Freescale Semiconductor, Inc. Non-volatile memory cell and methods thereof
US10482954B2 (en) 2006-07-27 2019-11-19 Micron Technology, Inc. Phase change memory device
US9779805B2 (en) * 2006-07-27 2017-10-03 Micron Technology, Inc. Phase change memory device
US20150287458A1 (en) * 2006-07-27 2015-10-08 Micron Technology, Inc. Phase change memory device
US20100315858A1 (en) * 2009-02-20 2010-12-16 John Lynch Memory architecture with a current controller and reduced power requirements
US8169812B2 (en) * 2009-02-20 2012-05-01 Lynch John K Memory architecture with a current controller and reduced power requirements
US8274819B2 (en) * 2010-02-04 2012-09-25 Magic Technologies Read disturb free SMT MRAM reference cell circuit
US20110188305A1 (en) * 2010-02-04 2011-08-04 Magic Technologies, Inc. Read disturb free SMT MRAM reference cell circuit
US20150302912A1 (en) * 2014-04-21 2015-10-22 Qualcomm Incorporated Method and apparatus for generating a reference for use with a magnetic tunnel junction
US9336847B2 (en) * 2014-04-21 2016-05-10 Qualcomm Incorporated Method and apparatus for generating a reference for use with a magnetic tunnel junction
US9535834B2 (en) * 2014-05-19 2017-01-03 SK Hynix Inc. Electronic device including memory arrays with variable resistance storage elements arranged on different sides of a word line driving unit
US20170076793A1 (en) * 2014-05-19 2017-03-16 SK Hynix Inc. Electronic device
US9865345B2 (en) * 2014-05-19 2018-01-09 SK Hynix Inc. Electronic device including a semiconductor memory having memory arrays with variable resistance storage elements and a bias voltage generator arranged between the arrays
US20150332760A1 (en) * 2014-05-19 2015-11-19 Dong-Keun Kim Electronic device
US11080229B2 (en) * 2016-02-13 2021-08-03 HangZhou HaiCun Information Technology Co., Ltd. Processor for calculating mathematical functions in parallel
US20180342307A1 (en) * 2016-04-14 2018-11-29 HangZhou HaiCun Information Technology Co., Ltd. Three-Dimensional One-Time-Programmable Memory Comprising Dummy Bit Lines
US10573399B2 (en) * 2016-04-14 2020-02-25 HangZhou HaiCun Information Technology Co., Ltd. Three-dimensional one-time-programmable memory comprising dummy bit lines
US11139025B2 (en) 2020-01-22 2021-10-05 International Business Machines Corporation Multi-level cell threshold voltage operation of one-selector-one-resistor structure included in a crossbar array
US11557342B2 (en) 2020-01-22 2023-01-17 International Business Machines Corporation Multi-level cell threshold voltage operation of one-selector-one-resistor structure included in a crossbar array
US20220180913A1 (en) * 2020-12-07 2022-06-09 Everspin Technologies, Inc. Midpoint sensing reference generation for stt-mram
US11651807B2 (en) * 2020-12-07 2023-05-16 Everspin Technologies, Inc. Midpoint sensing reference generation for STT-MRAM
US12165684B2 (en) 2020-12-07 2024-12-10 Everspin Technologies, Inc. Midpoint sensing reference generation for STT-MRAM
CN116312677A (zh) * 2021-12-21 2023-06-23 浙江驰拓科技有限公司 Mram阵列结构

Also Published As

Publication number Publication date
CN1681040A (zh) 2005-10-12
JP2005196956A (ja) 2005-07-21
US20090067233A1 (en) 2009-03-12
EP1564750B1 (en) 2011-06-15
EP1564750A3 (en) 2007-07-04
EP1564750A2 (en) 2005-08-17
KR20050068806A (ko) 2005-07-05
KR100528341B1 (ko) 2005-11-15
JP4634153B2 (ja) 2011-02-16
US8320166B2 (en) 2012-11-27

Similar Documents

Publication Publication Date Title
US8320166B2 (en) Magnetic random access memory and method of reading data from the same
US6678189B2 (en) Method and system for performing equipotential sensing across a memory array to eliminate leakage currents
US6512690B1 (en) High sensitivity common source amplifier MRAM cell, memory array and read/write scheme
US7161861B2 (en) Sense amplifier bitline boost circuit
US6990015B2 (en) Semiconductor memory device using tunneling magnetoresistive elements
US20050036376A1 (en) Magnetic random access memory
CN1412777A (zh) 高密度存储器读出放大器
US6930910B2 (en) Magnetic random access memory cell device using magnetic tunnel junction
US6982909B2 (en) System and method for reading a memory cell
JP5093234B2 (ja) 磁気ランダムアクセスメモリ
US20030179602A1 (en) Magneto-resistive random access memory
US20070195585A1 (en) Toggle-Type Magnetoresistive Random Access Memory
JP5135609B2 (ja) 半導体装置
CN100505087C (zh) 磁性随机处理存储器装置
JP3803503B2 (ja) 磁気ランダムアクセスメモリ回路
JP5288103B2 (ja) 磁気ランダムアクセスメモリ及びデータ読み出し方法
JP4775926B2 (ja) 磁気メモリ装置の読み出し回路
US6958933B2 (en) Memory cell strings
US20050094445A1 (en) Magnetic random access memory using memory cells with rotated magnetic storage elements
JP3427974B2 (ja) 磁気ランダムアクセスメモリ回路
JP3808835B2 (ja) 半導体装置間信号伝送システム
JP2003085968A (ja) 磁気メモリ装置の読み出し回路

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PARK, WAN-JUN;KIM, TAE-WAN;PARK, SANG-JIN;AND OTHERS;REEL/FRAME:016498/0263

Effective date: 20050421

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION