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US20050162835A1 - Production of via hole in flexible circuit printable board - Google Patents

Production of via hole in flexible circuit printable board Download PDF

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Publication number
US20050162835A1
US20050162835A1 US10/512,204 US51220404A US2005162835A1 US 20050162835 A1 US20050162835 A1 US 20050162835A1 US 51220404 A US51220404 A US 51220404A US 2005162835 A1 US2005162835 A1 US 2005162835A1
Authority
US
United States
Prior art keywords
via hole
metal
laser
polyimide film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/512,204
Other languages
English (en)
Inventor
Ryuichiro Kogure
Tadahiro Yokozawa
Hiroaki Yamaguchi
Osamu Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ube Corp
Original Assignee
Ube Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ube Industries Ltd filed Critical Ube Industries Ltd
Assigned to UBE INDUSTRIES, LTD. reassignment UBE INDUSTRIES, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KOGURE, RYUICHIRO, NAKAYAMA, OSAMU, YAMAGUCHI, HIROAKI, YOKOZAWA, TADAHIRO
Publication of US20050162835A1 publication Critical patent/US20050162835A1/en
Priority to US12/169,850 priority Critical patent/US7918021B2/en
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • the present invention relates to a process for producing a via hole in a flexible circuit (or wiring) printable board and further relates to a process for producing a flexible circuit (or wiring) printed board.
  • the sequential build-up boards are made of a plurality of circuit printed boards placed one on another.
  • the circuit printed board is produced by producing electroconductive via holes such as blind holes or through holes in a circuit board having on each surface side a predetermined circuit pattern.
  • the blind holes are produced by forming holes in a metal coat of a circuit printable board by etching and then forming holes in an insulating substrate of the circuit printable board by means of a punch, a drill, a carbon dioxide laser, a UV-YAG laser, or an excimer laser.
  • Japanese Patent Provisional Publication 10-154730 describes a process for producing a blind via hole which comprises the steps of patterning a copper layer of a two layer-CCL (Copper Clad Laminate employing a polyimide film) utilizing a photoresist coat placed on the copper layer; removing the polyimide film in the patterned area by CO 2 laser to form a blind hole; desmearing a polyimide resin deposited in the bottom of the blind hole; removing a portion of the copper layer and a small amount of polyimide resin by means of etching and desmearing; making the blind hole electroconductive by copper-plating to convert a blind via hole.
  • CCL Copper Clad Laminate employing a polyimide film
  • metal flashes are generally generated.
  • the metal flashes are then removed by buffing or dry-blasting.
  • the desmear (clearing the inside of the via hole) is performed by a wet desmear method using an aqueous alkaline manganese salt solution.
  • the buffing inadvertently causes elongation in the machine direction and then brings about anisotropic dimensional variation of the metal/polyimide film composite film.
  • the polyimide wall in the via hole should be cleaned by an additional desmear procedure.
  • the dry blasting may produce dusts in the blasting procedure. Therefore, the dry blasting is not advantageously employed in a clean room.
  • abrasive grains attached to the metal/polyimide film composite in the course of the blasting procedure disturbs adhesion of a photoresist in the following photolithographic procedure.
  • the wet desmear is carried out under heating in a strong alkaline solution. Therefore, the polyimide film is likely damaged and cracks may be produced in the polyimide film.
  • the present invention resides in a process for producing a flexible circuit printable board which comprises the steps of:
  • the application of a mixture of liquid and abrasive grains under pressure can be named “wet blasting”.
  • the smoothing the edge of the via hole can be done by removing flashes of the metal film which are produced in the via-producing procedure. In the course of the clearing of the via hole, polyimide flashes are mainly removed from the via hole.
  • the invention further resides in a process for producing a flexible circuit printed board which comprises the steps of:
  • FIG. 1 is a flexible circuit printed board produced by the process of the invention.
  • FIG. 2 is a photograph showing a section of the via hole which has been treated by the wet blasting of the invention.
  • FIG. 3 is a photograph showing a section of the via hole which has not been subjected to the wet blasting.
  • FIG. 4 is a photograph showing a section of the copper-plated via hole of the flexible printable circuit board produced in Example 1.
  • FIG. 5 is a photograph showing a section of the copper-plated via hole of the flexible printable circuit board produced in Comparison Example 1.
  • the present invention is further described by referring to FIG. 1 .
  • a flexible circuit printed board 1 of the invention is prepared by the following steps:
  • solder mask 7 is further formed on the circuit pattern. On the solder mask 7 is formed an opening, and a gold layer 8 is then plated in the opening.
  • the solder mask is preferably formed by laminating on the circuit pattern a photosensitive resist film under vacuum and subjecting the laminated resist film to predetermined patterning.
  • the metal coat on the polyimide film is a metal foil or film comprising copper, aluminum, iron, gold, or one of their alloys.
  • the metal coat preferably is made of a rolled copper foil, an electrolytic copper foil, a deposited copper film and/or a plated copper film.
  • the copper foil preferably has a moderate roughness of 3 ⁇ m or less in terms of Rz, more preferably in the range of 0.3 to 3 ⁇ m, most preferably in the range of 1.5 to 3 ⁇ m. Copper foils having such roughness are commercially available by the trade names of VLP, LP (or HIE).
  • the metal coat preferably has a thickness of 1 to 12 ⁇ m, more preferably 2 to 9 ⁇ m. A metal coat having a large thickness is not appropriate for fine-patterning. A metal foil having a small Rz can be employed after surface treatment.
  • the polyimide film can be a heat resistant, flexible single layer polyimide film having a glass transition temperature in the range of 275 to 375° C. It is preferred, however, that a three layer polyimide composite film having a core polyimide film having a glass transition temperature of 300° C. or higher and a pair of thermoplastic and/or flexible polyimide surface layers having a glass transition temperature of 200 to 300° C.
  • the three layer polyimide composite film preferably has a thickness of 7 to 50 ⁇ m and an elastic modulus in tension in the range 400 to 1,000 kgf/mm 2 (at 25° C.).
  • the polyimide film having a metal coat on each surface side is preferably manufactured by pressing a three layer polyimide composite film between a pair of metal foils under heating, for instance, by means of a double belt press. Otherwise, a metal is vapor deposited on both surfaces of the single polyimide film or the three layer polyimide composite film and then on the deposited metal layer is placed a copper layer by electrolytic plating (i.e., metal vapor deposition—electrolytic copper plating process).
  • the polyimide film is preferably subjected to vacuum discharge treatment so as to produce a chain of protrusions in the form of a network on the film surface before the vapor deposition is made.
  • the discharge treated polyimide film is then cleaned by plasma cleaning directly or after it is once placed under atmospheric conditions.
  • On the cleaned polyimide film surface at least two vapor-deposited metal layers are preferably formed, and subsequently copper metal-plating is performed on the metal deposited layers.
  • the above-mentioned metal vapor deposition—electrolytic copper plating process can be carried out utilizing various combinations of metals.
  • the metal deposited film is preferably made of two deposited layers, namely, a subbing layer and a surface layer.
  • the subbing layer can be made of chromium, titanium, palladium, zinc, molybdenum, nickel, cobalt, zirconium, iron, nickel-copper alloy, nickel-gold alloy, or nickel-molybdenum alloy.
  • the surface layer (or an intermediate layer) can be made of copper.
  • the metal plated layer which is formed on the metal deposited layer is preferably made of copper, copper alloy, or silver. Copper is most appropriate.
  • the copper plated layer can be formed by electroless plating, so as to cover pin-holes.
  • the metal deposited layer can have a large thickness such as 0.1 to 1.0 ⁇ m, and an electrolytic plated copper can be directly placed on the thick deposited layer.
  • the copper electrolytic plating can be preferably carried out in an aqueous bath containing 50 to 200 g/L of copper sulfate, 100 to 250 g/L of sulfuric acid, and a small amount of a brightener (preferably further an appropriate amount of chlorine) under the conditions of a temperature of 15 to 45° C., an electric current density of 0.1 to 10 A (ampere)/dm 2 , air agitation, transfer rate of 0.1 to 2 m/min., and the use of copper negative electrode.
  • a brightener preferably further an appropriate amount of chlorine
  • a via hole is produced in at least one metal coat and the polyimide film.
  • the via hole can be produced by means of a punch, a drill, a carbon dioxide laser, a UV-YAG laser, or an excimer laser.
  • the use of a punch or UV-YAG laser is preferred.
  • the UV-YAG laser can emit a laser in the UV region (oscillation wavelength region of 260 to 400 nm).
  • the layer can be applied on one metal coat of the metal coat polyimide film to produce a via hole having a diameter of 20 to 200 ⁇ m, preferably approx. 30 to 100 ⁇ m.
  • the laser is simultaneously applied to the polyimide film layer after de-focusing to produce in the polyimide film a hole of the same diameter.
  • flashes of metal are produced around the via hole, and metal flashes are deposited in the via hole. Further, polyimide dust is deposited in the via hole. These flashes and dust are cleaned by a wet-blasting which is performed by applying a mixture of liquid and abrasive grains under pressure onto the via hole.
  • the wet-blasting can be carried out by placing the metal-coated polyimide film on a blasting apparatus having a magnetic element and then placing a metal mask having a predetermined opening closely on the metal-coated polyimide film by the use of magnetic power.
  • the metal mask preferably has on its bottom surface an elastic layer such as urethane rubber layer so as not to damage the metal coat on the polyimide film.
  • An example of such wet-blasting apparatus is described in Japanese Patent Provisional Publication No. 9-295266.
  • the mixture for the wet-blasting preferably comprises water and 5 to 20 vol. % of abrasive grains (such as alumina grains) having a diameter of 1 to 10 ⁇ m.
  • abrasive grains such as alumina grains
  • the mixture was applied under high pressure onto the via hole at a flow rate of approx. 10 to 300 m/sec.
  • the via hole having been subjected to the wet-blasting procedure is then plated with metal so as to connect a metal coat on one surface side to a metal coat on another surface side.
  • the metal plating in the via hole can be carried out in the manner described in Japanese Patent Provisional Publication No. 11-51425.
  • the inner wall of the via hole is activated by forming Pd—Sn film and then plated with metal preferably by electrolytic copper plating.
  • the Pd—Sn film is produced by use of a palladium-tin colloidal catalyst and activated by immersing the Pd—Sn film in an alkali accelerator bath containing a reducing agent. This procedure is generally carried out in DPS (Direct Plating System).
  • the DPS is carried out by the following steps.
  • the via hole is washed with monoethanol amine, a nonionic surfactant, a cationic surfactant, and the like to defat the metal and polyimide areas of the via hole, desmeared using an alkaline permanganate solution, soft-etched using a sodium persulfate solution, and then pre-dipped in a mixture of sodium chloride and hydrochloric acid.
  • the treated via hole is immersed in a palladium-tin colloidal solution to form a Pd—Sn film which is then activated in an alkaline accelerator bath containing sodium carbonate, potassium carbonate, copper ion and a reducing agent, and further in an acidic accelerator bath containing sulfuric acid.
  • alkaline accelerator bath containing sodium carbonate, potassium carbonate, copper ion and a reducing agent
  • acidic accelerator bath containing sulfuric acid.
  • the reducing agents include aldehydes such as formaldehyde, acetaldehyde, propionaldehyde, and benzaldehyde, catechol, resorcinol and ascorbic acid.
  • the inner wall of the via hole is coated with a low electric resistant Pd—Sn film, and the following copper plating procedure can be carried out within a shorter period of time.
  • the via hole is then washed with an acid and electrolytically plated with copper.
  • the electrolytic plating is preferably carried out in a bath containing 180-240 g/L of copper sulfate, 45-60 g/L of sulfuric acid, 20-80 g/L of chloride ion, and additives such as thiourea, dextrin, or a combination of thiourea and molasses at an electric current density of 2 to 8 A/dm 2 .
  • a copper plated layer having a thickness of 3 to 30 ⁇ m is formed on the wall of the via hole (or through-hole).
  • a ground wiring layer having a predetermined pattern is formed on a metal coat on one surface side by a combination of photo-processing and etching. Further, a signal wiring layer having a predetermined pattern is formed on a metal coat on another surface side by a combination of photo-processing and etching.
  • a photosensitive solder resist preferably in the form of a dry photosensitive resist film, is laminated preferably by vacuum laminating.
  • the laminated photosensitive solder resist is then exposed to light to form a solder mask layer having the predetermined pattern on the signal wiring layer and the ground wiring layer.
  • the photosensitive solder resist can be a photosensitive ink resist, for instance, a photosensitive resin composition of polyimide (precursor) type, preferably a photosensitive resin composition of imidesiloxane type described in Japanese Patent Provisional Publication 2000-212446, and a photosensitive heat-setting resin composition of an epoxy-acrylate type described in Japanese Patent Provisional Publication 2000-109541.
  • a photosensitive solder resist of a dry film type is preferred.
  • a solder resist which shows an elastic modulus in tension of 100 kgf/mm 2 or lower after setting is preferred because it serves as a protective film showing no deformation.
  • Preferred examples of the dry type photosensitive solder resists which can serve as protective film after setting include a dry film solder mask for FPC use (photosensitive resin composition mainly composed of urethane rubber and epoxy acrylate, containing a flame retardant and a polymerization initiator, which shows an elastic modulus in tension of approx.
  • photosensitive resin composition described in Japanese Patent Application 2001-359790 which is composed of epoxy acrylate resin, a reaction product (oligomer) of an asymmetric aromatic tetracarboxylic dianhydride and ⁇ , ⁇ -bis(3-amino-propyl)polydimethylsiloxane, an epoxy resin, and a photopolymerization initiator (which shows an elastic modulus in tension of approx. 60 kgf/mm 2 after setting).
  • photosensitive solder resist of dry type is favorably employable in comparison with the previously employed composition of cover-lay type from the view-points of resistance to plating, no requirement of blanking, formation of fine pattern, and no exudation of adhesive.
  • the copper layer within the opening of the solder mask is plated with nickel/gold alloy or tin/gold alloy by a known electrolytic plating procedure.
  • the desired flexible circuit printed board is produced.
  • a metal-coated composite (trade name Upicel N, available from Ube Industries, Ltd.) composed of a three layer polyimide film (thickness: 25 ⁇ m) having a thermoplastic surface on each surface side and an electrolytic copper foil (thickness: 9 ⁇ m, trade name USLPR2, available from Nippon Electrolytic Co., Ltd.) which was placed on each of the thermoplastic surfaces under pressure and heating is exposed to a UV-YAG laser (Model 5320 available from ESI, wavelength 355 ⁇ m), to form simultaneously holes in one copper layer and in the polyimide film. To the holes were subsequently applied a mixture of water and alumina grains (alumina content: 16 vol. %) under an air pressure of 0.2 MPa using a wet-blasting apparatus (available Mako Co., Ltd.), whereby metal flashes and dust in the holes were removed.
  • a UV-YAG laser Model 5320 available from ESI, wavelength 355 ⁇ m
  • FIG. 2 shows a section of the hole having been subjected to the above-mentioned wet-blasting.
  • FIG. 3 shows a section of the hole before having been subjected to the wet-blasting.
  • FIG. 4 shows a section of thus formed via hole having a plated copper layer.
  • a ground wiring layer having the predetermined pattern (wiring pitch: 80 ⁇ m) was formed on one copper foil layer by photo-processing and etching.
  • a signal wiring layer having the predetermined pattern (wiring pitch: 40 ⁇ m) by photo-processing and etching.
  • FIGS. 2, 3 and 4 indicate that the wet-blasted hole has smooth edge and has almost no metal flashes and polyimide dusts.
  • Example 1 The procedures of Example 1 were repeated except for omitting the wet-blasting, to give via holes and copper foil having thereon a copper plated layer having a thickness of 12 ⁇ m.
  • FIG. 5 shows a section of thus formed via hole having a plated copper layer.
  • Example 1 Example 1
  • the procedures of Example 1 were repeated to produce a flexible circuit printed board.
  • the copper foils were not satisfactorily connected to the copper plated layer, so that separation was observed at their interfaces when the board was heated.
  • Example 1 The procedures of Example 1 were repeated except for producing through-holes in the metal-coated polyimide composite film by means of a punch. Thus produced through-holes were then subjected to wet-blasting in the same manner as in Example 1, to give via holes and copper foil having thereon a copper plated layer having a thickness of 12 ⁇ m.
  • Example 1 Then, the procedures of Example 1 were repeated to produce a flexible circuit printed board.
  • the copper foils were firmly connected to the copper plated layer, so that no separation was observed at their interfaces when it was heated.
  • the present invention provides an improved process for producing a via hole in a flexible circuit (or wiring) printable board, and further provides an improved process for producing a flexible circuit (or wiring) printed board.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Electroplating Methods And Accessories (AREA)
US10/512,204 2002-04-24 2003-04-24 Production of via hole in flexible circuit printable board Abandoned US20050162835A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/169,850 US7918021B2 (en) 2002-04-24 2008-07-09 Production of via hole in a flexible printed circuit board by applying a laser or punch

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002122256A JP3941573B2 (ja) 2002-04-24 2002-04-24 フレキシブル両面基板の製造方法
JP2002-122256 2002-04-24
PCT/JP2003/005289 WO2003092344A1 (en) 2002-04-24 2003-04-24 Production of via hole in flexible circuit printable board

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/169,850 Division US7918021B2 (en) 2002-04-24 2008-07-09 Production of via hole in a flexible printed circuit board by applying a laser or punch

Publications (1)

Publication Number Publication Date
US20050162835A1 true US20050162835A1 (en) 2005-07-28

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Application Number Title Priority Date Filing Date
US10/512,204 Abandoned US20050162835A1 (en) 2002-04-24 2003-04-24 Production of via hole in flexible circuit printable board
US12/169,850 Expired - Fee Related US7918021B2 (en) 2002-04-24 2008-07-09 Production of via hole in a flexible printed circuit board by applying a laser or punch

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/169,850 Expired - Fee Related US7918021B2 (en) 2002-04-24 2008-07-09 Production of via hole in a flexible printed circuit board by applying a laser or punch

Country Status (6)

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US (2) US20050162835A1 (zh)
JP (1) JP3941573B2 (zh)
KR (2) KR20040097387A (zh)
CN (1) CN1663329B (zh)
AU (1) AU2003222457A1 (zh)
WO (1) WO2003092344A1 (zh)

Cited By (14)

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EP1770776B1 (en) * 2005-09-28 2015-08-12 TDK Corporation Method for manufacturing semiconductor ic-embedded substrate
US20110023297A1 (en) * 2005-12-30 2011-02-03 Industrial Technology Research Institute and Unimicron Technology Corp. Multi-layered printed circuit board and method for fabricating the same
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EP2139305A1 (fr) * 2008-06-23 2009-12-30 Commissariat à l'Energie Atomique Procédé d'élimination de défaut de gravure d'une couche métallique déposée sur un support souple
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CN103369864A (zh) * 2012-03-27 2013-10-23 珠海方正科技高密电子有限公司 加工电路板上通孔的方法
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US20170318674A1 (en) * 2014-10-24 2017-11-02 Sumitomo Electric Printed Circuits, Inc. Flexible printed circuit board and method for producing the same
US10426031B2 (en) * 2014-10-24 2019-09-24 Sumitomo Electric Printed Circuits, Inc. Flexible printed circuit board and method for producing the same
US20240206048A1 (en) * 2018-02-02 2024-06-20 Kuprion Inc. Thermal Management in Circuit Board Assemblies
US12426148B2 (en) * 2018-02-02 2025-09-23 Kuprion Inc. Thermal management in circuit board assemblies
CN110430669A (zh) * 2019-08-13 2019-11-08 福建世卓电子科技有限公司 基于激光钻孔碳化导电直接金属化孔的电路板及生产工艺
US20220394842A1 (en) * 2021-05-31 2022-12-08 Fujifilm Corporation Wiring board and method for manufacturing wiring board
US12160949B2 (en) * 2021-05-31 2024-12-03 Fujifilm Corporation Wiring board and method for manufacturing wiring board
US20240360562A1 (en) * 2021-09-30 2024-10-31 Mitsui Chemicals, Inc. Method for manufacturing composite material to be plated and method for manufacturing anisotropic electroconductive sheet
CN114340161A (zh) * 2021-12-20 2022-04-12 安捷利电子科技（苏州）有限公司 一种5g高频多层fpc及其制备方法
EP4557896A1 (en) * 2023-11-20 2025-05-21 Mitsubishi Electric R&D Centre Europe B.V. Method for manufacturing vias in a multi-layered pcb stack
WO2025110253A1 (en) * 2023-11-20 2025-05-30 Mitsubishi Electric R&D Centre Europe Bv Method for manufacturing vias in multi-layered pcb stack, and multi-layered pcb stack

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CN1663329A (zh) 2005-08-31
US7918021B2 (en) 2011-04-05
US20090002953A1 (en) 2009-01-01
WO2003092344A1 (en) 2003-11-06
KR20100101018A (ko) 2010-09-15
JP3941573B2 (ja) 2007-07-04
AU2003222457A1 (en) 2003-11-10
JP2003318519A (ja) 2003-11-07
KR20040097387A (ko) 2004-11-17

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