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US20040227557A1 - Level shift circuit - Google Patents

Level shift circuit Download PDF

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Publication number
US20040227557A1
US20040227557A1 US10/796,060 US79606004A US2004227557A1 US 20040227557 A1 US20040227557 A1 US 20040227557A1 US 79606004 A US79606004 A US 79606004A US 2004227557 A1 US2004227557 A1 US 2004227557A1
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US
United States
Prior art keywords
node
circuit
level shift
input
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/796,060
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English (en)
Inventor
Tomoya Ishikawa
Hirofumi Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ISHIKAWA, TOMOYA, NAKAGAWA, HIROFUMI
Publication of US20040227557A1 publication Critical patent/US20040227557A1/en
Priority to US11/261,518 priority Critical patent/US7176741B2/en
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B43—WRITING OR DRAWING IMPLEMENTS; BUREAU ACCESSORIES
    • B43K—IMPLEMENTS FOR WRITING OR DRAWING
    • B43K23/00—Holders or connectors for writing implements; Means for protecting the writing-points
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
    • H03K3/356191—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes with synchronous operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B3/00—Measuring instruments characterised by the use of mechanical techniques
    • G01B3/02—Rulers with scales or marks for direct reading
    • G01B3/04—Rulers with scales or marks for direct reading rigid
    • G01B3/06—Rulers with scales or marks for direct reading rigid folding
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F1/00—Cardboard or like show-cards of foldable or flexible material
    • G09F1/04—Folded cards

Definitions

  • the present invention relates to a level shift circuit functioning as an interface between circuits operating at different power supply voltages.
  • An LCD driver needs level shift circuits in the number obtained by multiplying the number of outputs by the number of bits. For example, an LCD driver having 8 bits and 384 outputs uses as many as 3072 level shift circuits.
  • An application in which such a large number of level shift circuits are used has a drawback of increased power consumption caused by feed-through current in each of the level shift circuits and also has a drawback of a system malfunction occurring when an increase in the ground potential caused by the feed-through current is output as a noise to the outside of the chip.
  • a level shift circuit including: a level shift basic circuit for translating an input signal to an output signal which has a difference of a voltage between a first power supply and a second power supply having a lower voltage than that of the first power supply; and a control circuit including a first circuit for disconnecting a feed-through current path in said level shift basic circuit between the first power supply and the second power supply in response to a first control input, and a second circuit for fixing a voltage of an output node from which the output signal is output in response to a second control input.
  • the control circuit includes: a first circuit for disconnecting a feed-through current path between the first power supply and the second power supply; and a second circuit for fixing a voltage of the output node while the first circuit disconnects the feed-through current path, and is configured such that the disconnection of the feed-through current path by the first circuit is canceled after the fixing of the voltage by the second circuit has terminated and the input signal transitions while the first circuit disconnects the feed-through current path.
  • FIG. 1 is a circuit diagram showing an example of a configuration of a level shift circuit according to the present invention.
  • FIG. 2 is a time chart showing an example of operation of the level shift circuit shown in FIG. 1.
  • FIG. 3 is a circuit diagram showing a modified example of the level shift circuit shown in FIG. 1.
  • FIG. 4 is a circuit diagram showing another example of the configuration of the level shift circuit of the present invention.
  • FIG. 5 is a time chart showing an example of operation of the level shift circuit shown in FIG. 4.
  • FIG. 6 is a block diagram showing a modified example of the level shift circuit shown in FIG. 4.
  • FIG. 1 shows an example of a configuration of a level shift circuit according to the present invention.
  • reference numeral 10 denotes a level shift basic circuit having a CMOS configuration
  • reference numeral 20 denotes a control circuit for preventing feed-through current.
  • the level shift basic circuit 10 includes two n-MOS transistors M 1 and M 2 and two p-MOS transistors M 3 and M 4 .
  • the control circuit 20 includes two p-MOS transistors M 5 and M 6 and two n-MOS transistors M 7 and M 8 .
  • Reference signs Vin 1 and Vin 2 denote complementary data inputs
  • reference signs VS 1 and VS 2 respectively denote control inputs
  • reference signs Vout 1 and Vout 2 respectively denote data outputs
  • reference sign VDD denotes a first power supply
  • reference sign VSS denotes a second power supply (ground: 0V) having a voltage lower than VDD.
  • Vin 1 and Vin 2 are connected to the gates of the n-MOS transistors M 1 and M 2 , respectively.
  • the source of the n-MOS transistor M 1 is connected to the drain of the n-MOS transistor M 7 whose gate is connected to VS 1 .
  • the source of the n-MOS transistor M 7 is connected to VSS.
  • the source of the n-MOS transistor M 2 is connected to the drain of the n-MOS transistor M 8 whose gate is connected to VS 1 .
  • the source of the n-MOS transistor M 8 is connected to VSS.
  • the drain of the n-MOS transistor M 1 is connected to the drain of the p-MOS transistor M 3 .
  • the drain of the n-MOS transistor M 2 is connected to the drain of the p-MOS transistor M 4 .
  • the sources of the p-MOS transistors M 3 and M 4 are respectively connected to VDDs.
  • the gate of the p-MOS transistor M 3 is connected to the drain of the p-MOS transistor M 4 at a connection point, which will be referred to as a first data output node Vout 1 .
  • the gate of the p-MOS transistor M 4 is connected to the drain of the p-MOS transistor M 3 at a connection point, which will be referred to as a second data output node Vout 2 .
  • the sources of the p-MOS transistors M 5 and M 6 whose respective gates are connected to VS 2 are respectively connected to VDDs.
  • the drain of the p-MOS transistor M 5 is connected to Vout 1
  • the drain of the p-MOS transistor M 6 is connected to Vout 2 .
  • FIG. 2 shows an example of operation of the level shift circuit shown in FIG. 1.
  • VS 1 and VS 2 are at H levels, Vin 1 is at an L level and Vin 2 is at an H level.
  • Vout 1 outputs VSS and Vout 2 outputs VDD. Since the n-MOS transistor M 1 and the p-MOS transistor M 4 are OFF, no feed-through current flows between VDDs and VSSs.
  • the transitions of Vin 1 and Vin 2 are made in a period in which the n-MOS transistors M 7 and M 8 for control are turned OFF by changing VS 1 to an L level (switch-off period).
  • the sources of the n-MOS transistors M 1 and M 2 are respectively disconnected from VSSs.
  • VS 2 is changed to an L level so that the p-MOS transistors M 5 and M 6 for control turn ON. While the control p-MOS transistors M 5 and M 6 are ON, Vout 1 and Vout 2 are both precharged to VDD (precharge period). Accordingly, Vout 1 transitions from VSS to VDD at the beginning of the precharge period.
  • Vout 2 transitions from VDD to VSS at the point of time when the disconnections by the n-MOS transistors M 7 and M 8 are canceled by returning VS 1 to the H level.
  • the n-MOS transistor M 1 and the p-MOS transistor M 3 do not turn ON at the same time, and the n-MOS transistor M 2 and the p-MOS transistor M 4 also do not turn ON at the same time. Accordingly, no feed-through current flows through these transistors. While Vout 1 and Vout 2 output VDD due to turning ON of the control p-MOS transistors M 5 and M 6 , the sources of the n-MOS transistors M 1 and M 2 are respectively disconnected from VSSs by the control n-MOS transistors M 7 and M 8 . As a result, no feed-through current flows through the control p-MOS transistors M 5 and M 6 .
  • the level shift circuit shown in FIG. 1 does not include the control circuit 20 , when Vin 1 and Vin 2 transition from the L level to the H level and from the H level to the L level, respectively, the n-MOS transistor M 1 changes from the OFF-state to the ON-state and the n-MOS transistor M 2 changes from the ON-state to the OFF-state. In this case, both the n-MOS transistor M 1 and the p-MOS transistor M 3 are ON, so that feed-through current occurs between VDDs and VSSs.
  • the current driving capability (gate width) of the n-MOS transistor M 1 in the ON-state has been designed higher than that of the p-MOS transistor M 3 such that the potential of Vout 2 is gradually reduced by the n-MOS transistor M 1 and eventually the feed-through current is shut off.
  • the current driving capability (gate width) of the n-MOS transistor M 2 in the ON-state has been designed higher than that of the p-MOS transistor M 4 .
  • the level shift circuit shown in FIG. 1 and provided with the control circuit 20 for preventing feed-through current it is unnecessary for the n-MOS transistors M 1 and M 2 to shut off the feed-through current.
  • the current driving capabilities (gate widths) of the n-MOS transistors M 1 and M 2 are not necessarily higher than those of the p-MOS transistors M 3 and M 4 . Accordingly, the circuit area of the level shift basic circuit 10 can be reduced.
  • the level shift circuit is configured such that Vout 1 and Vout 2 are fixed at VDD by the p-MOS transistors M 5 and M 6 in accordance with VS 2 .
  • Vout 1 and Vout 2 may be fixed at VSS in accordance with the polarity of a required output node.
  • the fixing at VDD has the advantage of smaller size of the n-MOS transistors M 1 and M 2 because the p-MOS transistors M 3 and M 4 are OFF both at the falling edge of Vout 1 and at the falling edge of Vout 2 .
  • control n-MOS transistors M 7 and M 8 shown in FIG. 1 may be replaced with one n-MOS transistor.
  • the two n-MOS transistors M 7 and M 8 are preferably adopted.
  • FIG. 3 shows a modified example of the level shift circuit shown in FIG. 1.
  • one control circuit 20 for preventing feed-through current is provided for n level shift basic circuits 10 where n is an integer of two or more. Then, the area penalty due to provision of the control circuit 20 can be reduced.
  • FIG. 4 shows another example of the configuration of the level shift circuit of the present invention.
  • reference numeral 10 denotes a level shift basic circuit having a CMOS configuration
  • reference numeral 21 denotes a control circuit for preventing feed-through current.
  • the level shift basic circuit 10 includes two n-MOS transistors M 1 and M 2 and two p-MOS transistors M 3 and M 4 .
  • the control circuit 21 includes two two-input NOR circuits N 1 and N 2 and two p-MOS transistors M 5 and M 6 .
  • Reference signs Vin 1 and Vin 2 denote complementary data inputs
  • reference signs VS 1 and VS 2 respectively denote control inputs
  • reference signs Vout 1 and Vout 2 respectively denote data outputs
  • reference sign VDD denotes a first power supply
  • reference sign VSS denotes a second power supply (ground: 0V) having a voltage lower than VDD.
  • the NOR circuit N 1 receives Vin 1 and VS 1
  • the NOR circuit N 2 receives Vin 2 and VS 1
  • the gate of the n-MOS transistor M 1 is connected to an output V 1 of the NOR circuit N 1
  • the gate of the n-MOS transistor M 2 is connected to an output V 2 of the NOR circuit N 2
  • the sources of the n-MOS transistors M 1 and M 2 are respectively connected to VSSs.
  • the drain of the n-MOS transistor M 1 is connected to the drain of the p-MOS transistor M 3
  • the drain of the n-MOS transistor M 2 is connected to the drain of the p-MOS transistor M 4 .
  • the sources of the p-MOS transistors M 3 and M 4 are respectively connected to VDDs.
  • the gate of the p-MOS transistor M 3 is connected to the drain of the p-MOS transistor M 4 at a connection point, which will be referred to as a first data output node Vout 1 .
  • the gate of the p-MOS transistor M 4 is connected to the drain of the p-MOS transistor M 3 at a connection point, which will be referred to as a second data output node Vout 2 .
  • the sources of the p-MOS transistors M 5 and M 6 whose respective gates are connected to VS 2 are respectively connected to VDDs.
  • the drain of the p-MOS transistor M 5 is connected to Vout 1
  • the drain of the p-MOS transistor M 6 is connected to Vout 2 .
  • FIG. 5 shows an example of operation of the level shift circuit shown in FIG. 4.
  • VS 1 is at an L level
  • VS 2 is at an H level
  • Vin 1 is at an L level
  • Vin 2 is at an H level.
  • V 1 is at an H level
  • V 2 is at an L level
  • Vout 1 outputs VDD and Vout 2 outputs VSS. Since the n-MOS transistor M 2 and the p-MOS transistor M 3 are OFF, no feed-through current flows between VDDs and VSSs.
  • transitions of Vin 1 and Vin 2 are made in a period in which VS 1 is changed to an H level and thereby the gate voltages V 1 and V 2 of the n-MOS transistors M 1 and M 2 are reduced to L levels so that the n-MOS transistors M 1 and M 2 are forced to turn OFF (switch-off period).
  • VS 2 is changed to an L level so that the p-MOS transistors M 5 and M 6 for control turn ON.
  • both Vout 1 and Vout 2 are precharged to VDD (precharge period). Accordingly, Vout 2 transitions from VSS to VDD at the beginning of the precharge period.
  • the n-MOS transistor M 1 and the p-MOS transistor M 3 do not turn ON at the same time, and the n-MOS transistor M 2 and the p-MOS transistor M 4 also do not turn ON at the same time. Accordingly, no feed-through current flows through these transistors.
  • the control p-MOS transistors M 5 and M 6 makes Vout 1 and Vout 2 output VDD
  • the n-MOS transistors M 1 and M 2 are in the forced OFF-states. Accordingly, no feed-through current flows through the control p-MOS transistors M 5 and M 6 .
  • the current driving capabilities (gate widths) of the n-MOS transistors M 1 and M 2 are not necessarily higher than those of the p-MOS transistors M 3 and M 4 , either. Accordingly, the circuit area of the level shift basic circuit 10 can be reduced.
  • FIG. 6 shows a modified example of the level shift circuit shown in FIG. 4.
  • one control circuit 22 for preventing feed-through current is provided for n level shift basic circuits 10 where n is an integer of two or more. Then, the area penalty due to provision of the control circuit 22 can be reduced.
  • Inverters may be appropriately added to an output stage of the level shift basic circuit 10 in the above embodiments depending on whether the subsequent circuit is a p-channel type or an n-channel type.
  • the inventive level shift circuit is useful as a level shift circuit functioning as an interface between circuits operating at different power supply voltages.

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  • Logic Circuits (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
US10/796,060 2003-05-15 2004-03-10 Level shift circuit Abandoned US20040227557A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/261,518 US7176741B2 (en) 2003-05-15 2005-10-31 Level shift circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003-137124 2003-05-15
JP2003137124A JP2004343396A (ja) 2003-05-15 2003-05-15 レベルシフト回路

Related Child Applications (1)

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US10/796,060 Abandoned US20040227557A1 (en) 2003-05-15 2004-03-10 Level shift circuit
US11/261,518 Expired - Lifetime US7176741B2 (en) 2003-05-15 2005-10-31 Level shift circuit

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JP (1) JP2004343396A (zh)
KR (1) KR20040098566A (zh)
CN (1) CN1311635C (zh)
TW (1) TW200425641A (zh)

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US9246493B2 (en) 2012-08-01 2016-01-26 Renesas Electronics Corporation Level shift circuit and semiconductor device
WO2016160236A1 (en) * 2015-04-01 2016-10-06 Qualcomm Incorporated Low-power wide-range level shifter
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JP4832146B2 (ja) * 2005-04-19 2011-12-07 株式会社半導体エネルギー研究所 レベルシフタ回路、駆動回路、ディスプレイ、表示モジュール、電子機器
WO2006137232A1 (ja) * 2005-06-22 2006-12-28 Sharp Kabushiki Kaisha レベルシフタ回路およびそれを備える表示装置
KR100884001B1 (ko) * 2006-02-22 2009-02-17 삼성전자주식회사 입력 차단 모드에서 전류가 흐르지 않으며 고정된 출력값을발생하는 레벨 쉬프터 및 레벨 쉬프팅 방법
JP4724578B2 (ja) * 2006-03-23 2011-07-13 Ｏｋｉセミコンダクタ株式会社 レベルシフト回路
JP2007306042A (ja) * 2006-05-08 2007-11-22 Sony Corp レベル変換回路及びこれを用いた入出力装置
CN100521478C (zh) * 2006-07-03 2009-07-29 立锜科技股份有限公司 电位移转电路与方法
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CN1889363B (zh) * 2006-07-26 2010-10-06 友达光电股份有限公司 电平移动电路
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CN101202723B (zh) * 2006-12-11 2010-09-08 硅谷数模半导体（北京）有限公司 电平转换电路及具有该电路的ic芯片
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US7466183B2 (en) * 2006-12-19 2008-12-16 Himax Technologies Limited Level shift circuit
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US7583126B2 (en) * 2007-05-24 2009-09-01 Nvidia Corporation Apparatus and method for preventing current leakage when a low voltage domain is powered down
TWI346453B (en) 2007-12-17 2011-08-01 Richtek Technology Corp Level shift circuit and method for the same
KR100950476B1 (ko) * 2008-01-21 2010-03-31 주식회사 하이닉스반도체 시프트 회로
US8587359B2 (en) * 2009-08-07 2013-11-19 Atmel Corporation Level shifter with output latch
JP5491319B2 (ja) * 2010-08-16 2014-05-14 ルネサスエレクトロニクス株式会社 表示ドライバ回路
US8860488B2 (en) * 2013-03-06 2014-10-14 Micron Technology, Inc. Apparatuses and method for shifting a voltage level
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CN107317578B (zh) * 2016-04-26 2020-06-02 台湾类比科技股份有限公司 电压准位移位电路

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Publication number Priority date Publication date Assignee Title
US20050280461A1 (en) * 2004-06-21 2005-12-22 Oki Electric Industry Co., Ltd. Level shifter circuit with stress test function
US7180355B2 (en) * 2004-06-21 2007-02-20 Oki Electric Industry Co., Ltd. Level shifter circuit with stress test function
US20070085591A1 (en) * 2004-06-21 2007-04-19 Toshio Teraishi Level shifter circuit with stress test function
US7298196B2 (en) 2004-06-21 2007-11-20 Oki Electric Industry Co., Ltd. Level shifter circuit with stress test function
US20110224484A1 (en) * 2004-11-03 2011-09-15 Case Brian C Methods for modifying vascular vessel walls
US9246493B2 (en) 2012-08-01 2016-01-26 Renesas Electronics Corporation Level shift circuit and semiconductor device
WO2016160236A1 (en) * 2015-04-01 2016-10-06 Qualcomm Incorporated Low-power wide-range level shifter
US9559673B2 (en) 2015-04-01 2017-01-31 Qualcomm Incorporated Low-power wide-range level shifter
US9553585B1 (en) 2015-08-03 2017-01-24 SK Hynix Inc. Level shifter and parallel-to-serial converter including the same

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CN1551502A (zh) 2004-12-01
US7176741B2 (en) 2007-02-13
TW200425641A (en) 2004-11-16
KR20040098566A (ko) 2004-11-20
JP2004343396A (ja) 2004-12-02
US20060033550A1 (en) 2006-02-16
CN1311635C (zh) 2007-04-18

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